Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria 10 Devices

Transcription

1 Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML

2 Contents Contents 1 Quick Start Guide Directory Structure Generating the Design Procedure Design Example Parameters Compiling and Simulating the Design Procedure Testbench Compiling and Testing the Design in Hardware Procedure Hardware Setup M/100M/1G/10G Ethernet Design Example Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Simulation Test Case Design Example with the IEEE 1588v2 Feature Test Case Design Example without the IEEE 1588v2 Feature Hardware Testing Test Cases Signal Tap Debug Signals Interface Signals Configuration Registers G/10G Ethernet Design Example Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Simulation Test Case Design Example with the IEEE 1588v2 Feature Test Case Design Example without the IEEE 1588v2 Feature Hardware Testing Test Cases Signal Tap Debug Signals Interface Signals Configuration Registers GBASE-R Ethernet Design Example Features Hardware and Software Requirements Functional Description

3 Contents Design Components Clocking and Reset Scheme Simulation Hardware Testing Test Cases Signal Tap Debug Signals Interface Signals Configuration Registers G/2.5G Ethernet Design Example Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Partial Reconfiguration Ready Simulation Test Case Design Example with the IEEE 1588v2 Feature Test Case Design Example without the IEEE 1588v2 Feature Hardware Testing Test Procedure Interface Signal Configuration Registers G/2.5G/10G Ethernet Design Example Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Partial Reconfiguration Ready Simulation Hardware Testing Test Procedure Interface Signals Configuration Registers G USXGMII Ethernet Design Example Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Simulation Hardware Testing Test Procedure Interface Signals Configuration Registers

4 Contents A Interface Signals Description...85 A.1 Clock and Reset Interface Signals A.2 Avalon-MM Interface Signals A.3 Avalon-ST Interface Signals A.4 PHY Interface Signals A.5 Status Interface A.6 IEEE 1588v2 Timestamp Interface Signals A.7 Packet Classifier Interface Signals A.8 ToD Interface Signals B Configuration Registers Description B.1 Low Latency Ethernet 10G MAC B.2 PHY B.3 Transceiver Reconfiguration B.4 TOD C Document Revision History for Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria 10 Devices

5 1 Quick Start Guide The Intel FPGA Low Latency 10G Ethernet (LL 10GbE) MAC IP core for Intel Arria 10 provides the capability of generating design examples for selected configurations. Figure 1. Development Stages for the Design Example Compilation (Simulator) Functional Simulation Design Example Generation Compilation (Quartus Prime) Hardware Testing Related Links 10M/100M/1G/10G Ethernet Design Example on page 14 Provides details on the 10M/100M/1G/10G Ethernet design examples. 1G/10G Ethernet Design Example on page 30 Provides details on the 1G/10G Ethernet design examples. 10GBASE-R Ethernet Design Example on page 44 Provides details on the 10GBASE-R Ethernet design examples. 1G/2.5G Ethernet Design Example on page 51 Provides details on the 1G/2.5G Ethernet design examples. 1G/2.5G/10G Ethernet Design Example on page 67 Provides details on the 1G/2.5G/10G Ethernet design example. 10G USXGMII Ethernet Design Example on page 77 Provides details on the 10G USXGMII Ethernet design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

6 1 Quick Start Guide 1.1 Directory Structure Figure 2. Directory Structure for the Design Example <Design Example> rtl altera_eth_multi_channel.sv altera_eth_channel.sv <Design Component> simulation ed_sim models cadence mentor hwtesting system_console output_files altera_eth_top.sof altera_eth_top.qpf altera_eth_top.qsf altera_eth_top.sv altera_eth_top.sdc <Design Component> synopsys vcs Table 1. Directory and File Description Directory/File Description altera_eth_top.qpf altera_eth_top.qsf altera_eth_top.sv altera_eth_top.sdc rtl rtl/ altera_eth_10g_mac_base_r.sv rtl/ altera_10g_mac_base_r_wrap.v rtl/altera_mge_rd.sv rtl/altera_mge_channel.v rtl/altera_eth_channel.v rtl/ altera_eth_multi_channel.sv rtl/altera_eth_channel_1588.v rtl/ altera_eth_multi_channel_1588.sv rtl/ altera_mge_multi_channel.sv rtl/altera_mge_channel.v rtl/<design Component> simulation/ed_sim/models simulation/ed_sim/cadence simulation/ed_sim/mentor Intel Quartus Prime project file. Intel Quartus Prime settings file. Design example top-level HDL. Synopsys Design Constraints (SDC) file. The folder that contains the design example synthesizable components. Design example DUT top-level files for 10GBASE-R ethernet design example. Design example DUT top-level files for the following ethernet design examples: 1G/2.5G with 1588v2 feature 1G/2.5G/10G Design example DUT top-level files for the following ethernet design examples: 10M/100M/1G/10G 1G/10G Design example DUT top-level files for the following ethernet design examples: 10M/100M/1G/10G with with 1588v2 feature 1G/10G with 1588v2 feature Design example DUT top-level files for 10G USXGMII ethernet design example. The folder for each synthesizable component including Platform Designer generated IPs, such as LL10GbE MAC, PHY, and FIFO. The folder that contains the testbench files. The folder that contains the simulation script. It also serves as a working area for the simulator. continued... 6

7 1 Quick Start Guide Directory/File Description simulation/ed_sim/ synopsys/vcs hwtesting/system_console output_files The folder that contains system console scripts for hardware testing. The folder that contains Intel Quartus Prime output files including Intel Quartus Prime compilation reports and design programing file (.sof file). 7

8 1 Quick Start Guide 1.2 Generating the Design Procedure You can generate the design example from the IP Parameter Editor. Start Parameter Editor Specify IP Variation and Select Device Select Design Parameters Specify Example Design Initiate Design Generation Figure 3. Example Design Tab 1. Select Tools IP Catalog to open the IP Catalog and select Low Latency Ethernet 10G MAC. The IP parameter editor appears. 2. Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK. 3. To generate a design example, select a design example preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The Parameter Editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab. 4. Specify the parameters in the Example Design tab. 5. Click the Generate Example Design button. The software generates all design files in sub-directories. You require these files to run simulation, compilation, and hardware testing. Related Links Directory Structure on page 6 Provides more information about the generated design example directories and files. 8

9 1 Quick Start Guide Design Example Parameters Table 2. Parameters in the Example Design Tab Parameter Description Select Design Example Design Files for Simulation or Synthesis Generate File Format Select Board Change Target Device Specify Number of Channels Enable ADME support Partial Reconfiguration Ready Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design. The files to generate for the different development phase. Simulation generates the necessary files for simulating the example design. Synthesis generates the synthesis files. Use these files to compile the design in the Intel Quartus Prime software for hardware testing and perform static timing analysis. The format of the RTL files for simulation Verilog or VHDL. Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit. If this menu is grayed out, there is no supported board for the options that you select. Intel Arria 10 GX Transceiver Signal Integrity Development Kit: This option allows you to test the design example on selected Intel FPGA IP development kit. This selection automatically selects the Target Device to match the device on the Intel FPGA IP development kit. If your board revision has a different device grade, you can change the target device. Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel FPGA IP device, a custom designed board with Intel FPGA IP device, or a standard Intel FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit. No Development Kit: This option excludes the hardware aspects for the design example. Select this parameter to display and select all devices for the Intel FPGA IP development kit. The number of Ethernet channels. Turn on this option to enable Transceiver ADME feature. When this option is enabled, the generated hierarchy of the design example is compliance with the partial reconfiguration flow, where there is clear separation between hard IP and soft IP, without any functionality changes. Hard IPs such as Native PHY, JTAG, transmitter PLL, and FPLL are instantiated at the top-level wrapper of design example. 9

10 1 Quick Start Guide 1.3 Compiling and Simulating the Design Procedure You can compile and simulate the design by running a simulation script from the command prompt. Change to Testbench Directory Run <Simulation Script> Analyze Results 1. At the command prompt, change the working directory to <Example Design> \simulation\ed_sim\<simulator>. 2. Run the simulation script for the simulator of your choice. Simulator Working Directory Command Modelsim* <Example Design>/simulation/ed_sim/mentor vsim -c -do tb_run.tcl VCS* <Example Design>/simulation/ed_sim/ synopsys/vcs sh tb_run.sh NCSim* <Example Design>/simulation/ed_sim/cadence sh tb_run.sh A successful simulation ends with the following message: Simulation stopped due to successful completion! Simulation passed. After successful completion, you can analyze the results. 10

11 1 Quick Start Guide Testbench Figure 4. Block Diagram of the Testbench Testbench Avalon-MM Control Register Ethernet Packet Monitor Avalon-MM Avalon-ST Transmit Frame Generator Avalon-ST Receive Frame Monitor avalon_bfm_wrapper.sv Avalon Driver TX data RX data Ethernet Packet Monitor DUT Ordinary Clock Channel 0 Channel 1... Channel n-1 Channel n Loopback on Serial Table 3. Testbench Components Component Description Device under test (DUT) Avalon driver Ethernet packet monitors The design example. Consists of Avalon-ST master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon-MM interface of the DUT. Monitor TX and RX datapaths, and display the frames in the simulator console. 11

12 1 Quick Start Guide 1.4 Compiling and Testing the Design in Hardware Procedure You can compile and test the design in the supported Intel FPGA development kit. Compile Design in Quartus Prime Software Set up Hardware Program Device Test Design in Hardware 1. Launch the Intel Quartus Prime software and select Processing Start Compilation to compile the design. The timing constraints for the design example and the design components are automatically loaded during compilation. 2. Connect the development board to the host computer. 3. Launch the Clock Control tool, which is part of the development kit, and set new frequencies for the design example. Note: For the frequencies to set, refer to the Hardware Testing section of the specific design example chapter. 4. In the Intel Quartus Prime software, select Tools Programmer to configure the FPGA on the development board using the generated.sof file. 5. Reset the system by pressing the PB0 push button. 6. In the Intel Quartus Prime software, select Tools System Debugging Tools System Console to launch the system console. 7. Change the working directory to <Example Design>\hwtesting \system_console. 8. Initialize the design command list by running this command: source main.tcl. You can now run any of the predefined hardware tests from the System Console. Note: For a design example that does not provide the main.tcl file, refer to the Hardware Testing section in the respective design example chapter. Observe the test results displayed. 12

13 1 Quick Start Guide Hardware Setup Figure 5. Block Diagram of the Hardware Setup PC Intel System Console Software Intel Arria 10 GX Transceiver Signal Integrity Development Board Intel Arria 10 GX FPGA JTAG TAP Ethernet Frame Generation Controller & Monitoring (Master) Ethernet Channel 0 System Controller Ethernet Frame Generation & Monitoring (Slave) Ethernet Frame Generation & Monitoring Ethernet Channel 1 Ethernet Channel n - 1 (2) (1) Ethernet Frame Generation & Monitoring Ethernet Channel n (1) Use this type of loopback to test IEEE 1588v2 features. (2) Use this type of loopback to test features other than IEEE 1588v2. 13

14 2 10M/100M/1G/10G Ethernet Design Example 2.1 Features The 10M/100M/10G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC IP core operating at various speeds. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. Multi-speed Ethernet operation 10M, 100M, 1G, and 10G. Support for up to 12 channels. Packet monitoring on the TX and RX datapaths. Option to generate the design example with the IEEE 1588v2 feature. Tested with the Spirent TestCenter. 2.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator Intel Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

15 2 10M/100M/1G/10G Ethernet Design Example 2.3 Functional Description The design examples consist of various components. The following block diagrams show the design components and the top-level signals of the design examples. Figure 6. Block Diagram 10M/100M/1G/10G Ethernet Design Example without IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel) Ethernet channel 0 (altera_eth_channel) Address Decoder (address_decoder_channel) S Avalon-MM Master M S S FIFO Adapter LL 10GbE MAC Adapter PHY Avalon-ST TX/RX Serial Data Transceiver Reset Controller ATX PLL fpll PLL Reset Controller Generated with Platform Designer Generated with IP Catalog Input Clock Reset Figure 7. Block Diagram 10M/100M/1G/10G Ethernet Design Example with IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel_1588) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel_1588) Ethernet channel 0 (altera_eth_channel_1588) Address Decoder (address_decoder_channel) S Avalon-MM Master M PTP Packet Classifier Adapter LL 10GbE S MAC Adapter S PHY Pulse Per Second S Local TOD TOD Sync Avalon-ST 1G/10G Pulse Per Second IEEE 1588v2 Timestamp TX/RX Serial Data Transceiver Reset Controller Generated from Platform Designer Generated from IP Catalog PLL Input Clock Reset Controller Reset ATX PLL fpll S Master TOD Pulse Per Second Master Pulse Per Second Design Components Table 4. Design Components Component LL 10GbE MAC Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: continued... 15

16 2 10M/100M/1G/10G Ethernet Design Example Component Description Speed: 10M/100M/1G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the example design with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format PHY Address decoder Multi-channel address decoder Reset controller Transceiver Reset Controller PLL ATX PLL fpll MDIO FIFO The Intel Arria 10 1G/10G and 10GBASE-KR PHY IP. The example design uses the 1G/10G IP variant. Decodes the addresses of the components in each Ethernet channel. Decodes the addresses of the components used by all channels, such as the Master TOD module. Synchronizes the reset of all design components. The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Generates clocks for all design components. Generates a TX serial clock for the Intel Arria 10 10G transceiver. Generates a TX serial clock for the Intel Arria 10 1G transceiver. Provides an MDIO interface to the external PHY. The Avalon Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH and SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv. Design Components for the IEEE 1588v2 Feature Master TOD TOD Sync Local TOD Master Pulse Per Second Pulse Per Second PTP packet classifier The master TOD for all channels. Synchronizes the Master TOD to all Local TODs. The TOD for each channel. Returns pulse per second (pps) for all channels. Returns pulse per second (pps) for each channel. Decodes the packet type of incoming PTP packets and returns the decoded information to the LL10GbE MAC IP core. Related Links Intel FPGA Low Latency Ethernet 10G MAC User Guide For more information on the MAC parameters. Intel Arria 10 Transceiver PHY User Guide For more information on the PHY parameters. 16

17 2 10M/100M/1G/10G Ethernet Design Example KDB Link: Why do I see underflow errors when receiving Jumbo frames on the Low Latency Ethernet 10G MAC Design Examples? External FIFO buffer limitation for Intel Arria 10 Low Latency Ethernet 10G MAC Design Example. 17

18 2 10M/100M/1G/10G Ethernet Design Example Clocking Scheme The following diagrams show the clocking scheme for the design example. Figure 8. Note: Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. Avalon-MM altera_eth_multi_channel_1588 address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels altera_eth_channel_1588 altera_eth_channel_1588 address_decoder_channel PTP Packet Classifier Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters tx_serial_clk_10g tx_serial_clk_1g 125 MHz tx_clkout S PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout 10G Pulse Per Second period_clk S 10G Local TOD clk Slave Master 10G TOD Sync 1G Pulse Per Second period_clk S 1G Local TOD clk Master Slave 1G TOD Sync Transceiver Reset Controller Legend MHz MHz 125 MHz 125 MHz 0x01_0000(Master TOD) Notes: 1. n = (SHARED_REFCLK_EN == 1)? 1 : NUM_CHANNELS. 2. Sampling clock for 10G TOD sync is MHz. 3. Sampling clock for 1G TOD sync is MHz. 4. For Intel Arria 10 devices, the design example uses IOPLL. (1) n Channel xgmii_clk[n] MHz PLL 1 (4) MHz pll_ref_clk_10g[n] MHz MHz pll_ref_clk_10g(0) 625 MHz pll_ref_clk_1g(0) (2) (3) (NUM CHANNEL - 1) / ATX PLL fpll (NUM CHANNEL - 1) / PLL 2 pll_ref_clk_1g[n] 125 MHz rx_recovered_clk[n] mm_clk 125 MHz period_clk S Master TOD clk Master Pulse Per Second Figure 9. Note: Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. altera_eth_multi_channel altera_eth_channel altera_eth_channel TX / RX FIFO Avalon-MM address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels address_decoder_channel Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters 125 MHz tx_serial_clk_10g tx_serial_clk_1g tx_clkout S Arria 10 PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout Transceiver Reset Controller MHz MHz MHz 625 MHz Legend MHz MHz 125 MHz 125 MHz Note: 1. n = (SHARED_REFCLK_EN == 1)? 1: NUM_CHANNELS 2. For Intel Arria 10 devices, the design example uses IOPLL. xgmii_clk[n] n Channel (1) PLL (2) pll_ref_clk_10g[n] MHz (NUM CHANNEL - 1) / ATX PLL pll_ref_clk_10g(0) fpll pll_ref_clk_1g[n] 125 MHz (NUM CHANNEL - 1) / pll_ref_clk_1g(0) rx_recovered_clk[n] dc_fifo_tx_clk MHz dc_fifo_rx_clk MHz 18

19 2 10M/100M/1G/10G Ethernet Design Example Reset Scheme The reset signals of the design example master_reset_n and channel_reset_n[n:0] are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components. Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example. Figure 10. Master Reset master_reset_n Ethernet Design Example with IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz PLL MHz Master PPS Master TOD Ethernet Channel n ATX PLL fpll master_reset_n Ethernet Design Example without IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz Ethernet Channel n ATX PLL fpll The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the PHY reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together. The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv 19

20 2 10M/100M/1G/10G Ethernet Design Example Figure 11. Channel Reset mm_reset Ethernet Design Example with IEEE 1588v2 Feature datapath_reset LL 10GbE MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller TOD 10G TOD SYN 96B_10G PPS 10G TOD SYN 64B_10G TOD 1G TOD SYN 96B_1G PPS 1G TOD SYN 64B_1G Address Decoder datapath_reset Ethernet Design Example without IEEE 1588v2 Feature mm_reset MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller Address Decoder 2.4 Simulation The simulation test cases demonstrate how the channel speed and the configuration of the PHY are changed. These test cases use circular loopback on the total number of Ethernet channels. The following table describes the steps to change the speed and configuration. Table 5. Ethernet Operations Operation Configuring the PHY speed. Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. Description Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), 1G1000Base-X or 1G/100M/10M SGMII. Write one of the following values to the PHY's register at address offset 0x12C0. 0x01: Turn on the auto-detection mode. In this mode, the PHY automatically detects the speed. 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps. 0x41: Turn off the auto-detection mode and set the speed to 10 Gbps. Example To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11 continued... 20

21 2 10M/100M/1G/10G Ethernet Design Example Operation Description To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01 Changing the speed between 1 Gbps, 100 Mbps, and 10 Mbps in SGMII. Set the port to 1000BASE-X. Write one of the following values to the PHY's register at offset 0x x01: Enable SGMII and set the speed to 10 Mbps. 0x03: Enable SGMII and auto-negotiation. 0x05: Enable SGMII mode and set the speed to 100 Mbps 0x09: Enable SGMII mode and set the speed to 1 Gbps Example: To set port 0 to SGMII and 100 Mbps: Set port 0 to 1000Base-X: write_32 0x02_52C0 0x11 Set port 0 to 100-Mbps SGMII: write_32 0x02_5290 0x05 Related Links Compiling and Simulating the Design on page 10 Provides information on the procedure and testbench Test Case Design Example with the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the design example with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the design example asserts the channel_ready signal for each channel. 4. Sends the following packets: Non-PTP No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP 5. Repeats steps 2 to 4 for other operating speeds. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 21

22 2 10M/100M/1G/10G Ethernet Design Example Figure 12. Sample Simulation Output Test Case Design Example without the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the example design asserts the channel_ready signal for each channel. 4. Sends the following packets: Normal data frame, 64Bytes SVLAN data frame, broadcast, 64Bytes VLAN data frame, unicast, 500Bytes 5. Repeats steps 2 to 4 for other operating speeds. 22

23 2 10M/100M/1G/10G Ethernet Design Example When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. Figure 13. Sample Simulation Output 2.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, and set Y5 to MHz and Y6 to 125 MHz. Related Links Test Cases Compiling and Testing the Design in Hardware on page 12 Provides information on the procedure and hardware setup. You can run any of the following tests from the System Console. 23

24 2 10M/100M/1G/10G Ethernet Design Example Table 6. Hardware Test Cases Test Case Command Example PHY internal serial loopback SMA loopback TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_size> For the design with the IEEE 1588v2 feature: TEST_SMA_LB <channel> <speed_test> <burst_size> For the design without the IEEE 1588v2 feature: TEST_SMA_LOOPBACK <channel> <speed_test> <burst_size> TEST_PHYSERIAL_LOOPBACK 0 10G 1000 TEST_SMA_LB 0 10G 1000 Table 7. Command Parameters Parameter Valid Values Description channel 0 to the number of channel specified for the design The number of channels for the test. speed_test 10G, 1G, 100M, 10M The PHY speed. burst_size The number of packets to generate for the test. When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output. Figure 14. Sample Test Output Packet Monitor 24

25 2 10M/100M/1G/10G Ethernet Design Example Figure 15. Sample Test Output Statistics Counters Signal Tap Debug Signals The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below: set_global_assignment -name ENABLE_SIGNALTAP ON Table 8. Signal Tap Debug Signals Component Module Name Signal Top-level design example altera_eth_top mm_clk ref_clk_1g ref_clk_10g channel_ready_n channel_reset_n master_reset_n Multi-channel wrapper Design example without the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel Design example with the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel_1588 pll_locked pll_1_locked pll_2_locked (only for the design example with the IEEE 1588v2 feature) pll_locked_10g pll_locked_1g continued... 25

26 2 10M/100M/1G/10G Ethernet Design Example Component Module Name Signal MAC IP core <n>.altera_eth_10g_mac (1) avalon_st_tx_startofpacket avalon_st_tx_endofpacket avalon_st_tx_data avalon_st_tx_ready avalon_st_tx_valid avalon_st_tx_error avalon_st_tx_empty avalon_st_rx_startofpacket avalon_st_rx_endofpacket avalon_st_rx_data avalon_st_rx_ready avalon_st_rx_valid avalon_st_rx_error avalon_st_rx_empty PHY <n>.altera_eth_10gkr_phy (1) led_an led_char_err led_disp_err led_link mii_speed_sel rx_analogreset rx_block_lock rx_cal_busy rx_is_lockedtodata rx_digitalreset rx_data_ready tx_analogreset tx_digitalreset continued... (1) Replace n with: altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature. altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature. 26

27 2 10M/100M/1G/10G Ethernet Design Example Component Module Name Signal XGMII <n>.altera_eth_10g_mac.alt_em xgmii_tx_control 10g32.alt_em10g32unit (1) xgmii_tx_data xgmii_rx_control xgmii_rx_data link_fault_status_xgmii_rx_ data GMII <n>.altera_eth_10g_mac (1) gmii_tx_d gmii_tx_en gmii_tx_err gmii_rx_d gmii_rx_dv gmii_rx_err MII <n>.altera_eth_10g_mac (1) mii_tx_d mii_tx_en mii_tx_err mii_rx_dv mii_rx_err 27

28 2 10M/100M/1G/10G Ethernet Design Example 2.6 Interface Signals Figure 16. Interface Signals of the 10M/100M/1G/10G Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_txstatus_valid[n] avalon_st_txstatus_data[n][40] avalon_st_txstatus_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rxstatus_valid[n] avalon_st_rxstatus_data[n][40] avalon_st_rxstatus_error[n][7] 10M/100M/1G/10G Ethernet Design Example MAC RX rx_serial_data[n] tx_serial_data[n] ethernet_1g_an[n] ethernet_1g_char_err[n] ethernet_1g_disp_err[n] channel_ready[n] read readdata[32] write writedata[32] address[20] waitrequest mm_clk pll_ref_clk_1g[s] pll_ref_clk_10g[s] cdr_ref_clk_1g[s] cdr_ref_clk_10g[s] channel_reset_n[n] master_reset_n xgmii_clk[s] rx_recovered_clk[n] PHY Interface Status Interface Avalon-MM Interface Clock and Reset IEEE 1588v2 Time-Stamp Interface Additional Signals for Example Design With IEEE 1588v2 Feature tx_egress_timestamp_96b_valid[n] tx_egress_timestamp_96b_data[n][96] tx_egress_timestamp_96b_fingerprint[n][f] tx_egress_timestamp_64b_valid[n] tx_egress_timestamp_64b_data[n][64] tx_egress_timestamp_64b_fingerprint[n][f] rx_ingress_timestamp_96b_valid[n] rx_ingress_timestamp_96b_data[n][96] rx_ingress_timestamp_64b_valid[n] rx_ingress_timestamp_64b_data[n][64] n: Number of channels s: Number of unshared channels f: Timestamp fingerprint width tx_egress_timestamp_request_in_valid[n] tx_egress_timestamp_request_in_fingerprint[n][f] clock_operation_mode_mode[n][2] pkt_with_crc_mode[n] tx_ingress_timestamp_valid[n] tx_ingress_timestamp_96b_data[n][96] tx_ingress_timestamp_64b_data[n][64] tx_ingress_timestamp_format[n] master_pulse_per_second start_tod_sync[n] pulse_per_second_10g[n] pulse_per_second_1g[n] Packet Classifier Interface TOD Interface Related Links Interface Signals Description on page 85 For more information on each interface signal. 28

29 2 10M/100M/1G/10G Ethernet Design Example 2.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 9. Register Map Byte Offset 0x00_0000 0x00_F000 0x01_0000 Block Client logic Reserved Master TOD Channel 0 0x02_0000 0x02_4000 0x02_7800 0x02_7900 0x02_8000 Reserved PHY 10G TOD 1G TOD LL 10GbE MAC Channel 1 0x03_0000 0x03_4000 0x03_7800 0x03_7900 0x03_8000 Reserved PHY 10G TOD 1G TOD LL 10GbE MAC.. and so forth up to Channel 11. 0x0E_0000 onwards Client Logic Related Links Configuration Registers Description on page 94 For more information on each configuration register. 29

30 3 1G/10G Ethernet Design Example 3.1 Features The 1G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC IP core operating at 1G and 10G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. Dual-speed Ethernet operation 1G and 10G. Support for up to 12 channels. Packet monitoring on the TX and RX datapaths. Option to generate the design example with the IEEE 1588v2 feature. Tested with the Spirent TestCenter. 3.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator Intel Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

31 3 1G/10G Ethernet Design Example 3.3 Functional Description The design example consists of various components. The following block diagrams show the design components and the top-level signals of the design example. Figure 17. Block Diagram 1G/10G EthernetEthernet Design Example with IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel_1588) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel_1588) Ethernet channel 0 (altera_eth_channel_1588) Address Decoder (address_decoder_channel) S Avalon-MM Master M PTP Packet Classifier Adapter LL 10GbE S MAC Adapter S PHY Pulse Per Second S Local TOD TOD Sync Avalon-ST 1G/10G Pulse Per Second IEEE 1588v2 Timestamp TX/RX Serial Data Transceiver Reset Controller Generated from Platform Designer Generated from IP Catalog PLL Input Clock Reset Controller Reset ATX PLL fpll S Master TOD Pulse Per Second Master Pulse Per Second Figure 18. Block Diagram 1G/10G Ethernet Design Example without IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel) Ethernet channel 0 (altera_eth_channel) Address Decoder (address_decoder_channel) S Avalon-MM Master M S S FIFO Adapter LL 10GbE MAC Adapter PHY Avalon-ST TX/RX Serial Data Transceiver Reset Controller ATX PLL fpll PLL Reset Controller Generated with Platform Designer Generated with IP Catalog Input Clock Reset Design Components Table 10. Design Components of the 1G/10G Ethernet Design Example LL 10GbE MAC Component Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: continued... 31

32 3 1G/10G Ethernet Design Example Component Description Speed: 1G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the example design with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format PHY Address Decoder Reset Controller Transceiver Reset Controller PLL ATX PLL FIFO The Intel Arria 10 1G/10G and 10GBASE-KR PHY IP. The design example uses the 1G/10G IP variant. Decodes the addresses of the components in each Ethernet channel. Synchronizes the reset of all design components. The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Generates clocks for all design components. Generates a TX serial clock for the Intel Arria 10 10G transceiver. The Avalon Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH & SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv. Related Links Intel FPGA Low Latency Ethernet 10G MAC User Guide For more information on the MAC parameters. Intel Arria 10 Transceiver PHY User Guide For more information on the PHY parameters. KDB Link: Why do I see underflow errors when receiving Jumbo frames on the Low Latency Ethernet 10G MAC Design Examples? External FIFO buffer limitation for Intel Arria 10 Low Latency Ethernet 10G MAC Design Example. 32

33 3 1G/10G Ethernet Design Example Clocking Scheme The following diagrams show the clocking scheme for the design example. Figure 19. Note: Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. Avalon-MM altera_eth_multi_channel_1588 address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels altera_eth_channel_1588 altera_eth_channel_1588 address_decoder_channel PTP Packet Classifier Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters tx_serial_clk_10g tx_serial_clk_1g 125 MHz tx_clkout S PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout 10G Pulse Per Second period_clk S 10G Local TOD clk Slave Master 10G TOD Sync 1G Pulse Per Second period_clk S 1G Local TOD clk Master Slave 1G TOD Sync Transceiver Reset Controller Legend MHz MHz 125 MHz 125 MHz 0x01_0000(Master TOD) Notes: 1. n = (SHARED_REFCLK_EN == 1)? 1 : NUM_CHANNELS. 2. Sampling clock for 10G TOD sync is MHz. 3. Sampling clock for 1G TOD sync is MHz. 4. For Intel Arria 10 devices, the design example uses IOPLL. (1) n Channel xgmii_clk[n] MHz PLL 1 (4) MHz pll_ref_clk_10g[n] MHz MHz pll_ref_clk_10g(0) 625 MHz pll_ref_clk_1g(0) (2) (3) (NUM CHANNEL - 1) / ATX PLL fpll (NUM CHANNEL - 1) / PLL 2 pll_ref_clk_1g[n] 125 MHz rx_recovered_clk[n] mm_clk 125 MHz period_clk S Master TOD clk Master Pulse Per Second Figure 20. Note: Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. altera_eth_multi_channel altera_eth_channel altera_eth_channel TX / RX FIFO Avalon-MM address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels address_decoder_channel Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters 125 MHz tx_serial_clk_10g tx_serial_clk_1g tx_clkout S Arria 10 PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout Transceiver Reset Controller MHz MHz MHz 625 MHz Legend MHz MHz 125 MHz 125 MHz Note: 1. n = (SHARED_REFCLK_EN == 1)? 1: NUM_CHANNELS 2. For Intel Arria 10 devices, the design example uses IOPLL. xgmii_clk[n] n Channel (1) PLL (2) pll_ref_clk_10g[n] MHz (NUM CHANNEL - 1) / ATX PLL pll_ref_clk_10g(0) fpll pll_ref_clk_1g[n] 125 MHz (NUM CHANNEL - 1) / pll_ref_clk_1g(0) rx_recovered_clk[n] dc_fifo_tx_clk MHz dc_fifo_rx_clk MHz 33

34 3 1G/10G Ethernet Design Example Reset Scheme The reset signals of the design example master_reset_n and channel_reset_n[n:0] are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components. Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example. Figure 21. Master Reset master_reset_n Ethernet Design Example with IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz PLL MHz Master PPS Master TOD Ethernet Channel n ATX PLL fpll master_reset_n Ethernet Design Example without IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz Ethernet Channel n ATX PLL fpll The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the PHY reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together. The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv 34

35 3 1G/10G Ethernet Design Example Figure 22. Channel Reset mm_reset Ethernet Design Example with IEEE 1588v2 Feature datapath_reset LL 10GbE MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller TOD 10G TOD SYN 96B_10G PPS 10G TOD SYN 64B_10G TOD 1G TOD SYN 96B_1G PPS 1G TOD SYN 64B_1G Address Decoder datapath_reset Ethernet Design Example without IEEE 1588v2 Feature mm_reset MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller Address Decoder 3.4 Simulation The simulation test cases demonstrate how the channel speed and the configuration of the PHY are changed. These test cases use circular loopback on the total number of Ethernet channels. The following table describes the steps to change the speed and configuration. Table 11. Ethernet Operations Operation Configuring the PHY speed. Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. Description Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), or 1G1000Base-X. Write one of the following values to the PHY's register at address offset 0x12C0. 0x01: Turn on the auto-detection mode. In this mode, the PHY automatically detects the speed. 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps. 0x41: Turn off the auto-detection mode and set the speed to 10 Gbps. Example To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11 To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01 35

36 3 1G/10G Ethernet Design Example Test Case Design Example with the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the design example with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the design example asserts the channel_ready signal for each channel. 4. Sends the following packets: Non-PTP No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP 5. Repeats steps 2 to 4 for other operating speeds. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 36

37 3 1G/10G Ethernet Design Example Figure 23. Sample Simulation Output Test Case Design Example without the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the example design asserts the channel_ready signal for each channel. 4. Sends the following packets: Normal data frame, 64Bytes SVLAN data frame, broadcast, 64Bytes VLAN data frame, unicast, 500Bytes 5. Repeats steps 2 to 4 for other operating speeds. 37

38 3 1G/10G Ethernet Design Example When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. Figure 24. Sample Simulation Output 3.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, and set Y5 to MHz and Y6 to 125 MHz. Related Links Test Cases Compiling and Testing the Design in Hardware on page 12 Provides information on the procedure and hardware setup. You can run any of the following tests from the System Console. 38

39 3 1G/10G Ethernet Design Example Table 12. Hardware Test Cases Test Case Command Example PHY internal serial loopback SMA loopback TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_size> For the design with the IEEE 1588v2 feature: TEST_SMA_LB <channel> <speed_test> <burst_size> For the design without the IEEE 1588v2 feature: TEST_SMA_LOOPBACK <channel> <speed_test> <burst_size> TEST_PHYSERIAL_LOOPBACK 0 10G 1000 TEST_SMA_LB 0 10G 1000 Table 13. Command Parameters Parameter Valid Values Description channel 0 to the number of channel specified for the design The number of channels for the test. speed_test 10G, 1G The PHY speed. burst_size The number of packets to generate for the test. When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output. Figure 25. Sample Test Output Packet Monitor 39

40 3 1G/10G Ethernet Design Example Figure 26. Sample Test Output Statistics Counters Signal Tap Debug Signals The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below: set_global_assignment -name ENABLE_SIGNALTAP ON Table 14. Signal Tap Debug Signals Component Module Name Signal Top-level design example altera_eth_top mm_clk ref_clk_1g ref_clk_10g channel_ready_n channel_reset_n master_reset_n Multi-channel wrapper Design example without the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel Design example with the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel_1588 pll_locked pll_1_locked pll_2_locked (only for the design example with the IEEE 1588v2 feature) pll_locked_10g pll_locked_1g continued... 40

41 3 1G/10G Ethernet Design Example Component Module Name Signal MAC IP core <n>.altera_eth_10g_mac (2) avalon_st_tx_startofpacket avalon_st_tx_endofpacket avalon_st_tx_data avalon_st_tx_ready avalon_st_tx_valid avalon_st_tx_error avalon_st_tx_empty avalon_st_rx_startofpacket avalon_st_rx_endofpacket avalon_st_rx_data avalon_st_rx_ready avalon_st_rx_valid avalon_st_rx_error avalon_st_rx_empty PHY <n>.altera_eth_10gkr_phy (2) led_an led_char_err led_disp_err led_link mii_speed_sel rx_analogreset rx_block_lock rx_cal_busy rx_is_lockedtodata rx_digitalreset rx_data_ready tx_analogreset tx_digitalreset XGMII <n>.altera_eth_10g_mac.alt_em xgmii_tx_control 10g32.alt_em10g32unit (2) xgmii_tx_data xgmii_rx_control xgmii_rx_data link_fault_status_xgmii_rx_ data GMII <n>.altera_eth_10g_mac (2) gmii_tx_d gmii_tx_en gmii_tx_err gmii_rx_d gmii_rx_dv gmii_rx_err (2) Replace n with: altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature. altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature. 41

42 3 1G/10G Ethernet Design Example 3.6 Interface Signals Figure 27. Interface Signals of the 1G/10G Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_txstatus_valid[n] avalon_st_txstatus_data[n][40] avalon_st_txstatus_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rxstatus_valid[n] avalon_st_rxstatus_data[n][40] avalon_st_rxstatus_error[n][7] 1G/10G Ethernet Design Example MAC RX rx_serial_data[n] tx_serial_data[n] ethernet_1g_an[n] ethernet_1g_char_err[n] ethernet_1g_disp_err[n] channel_ready[n] read readdata[32] write writedata[32] address[20] waitrequest mm_clk pll_ref_clk_1g[s] pll_ref_clk_10g[s] cdr_ref_clk_1g[s] cdr_ref_clk_10g[s] channel_reset_n[n] master_reset_n xgmii_clk[s] rx_recovered_clk[n] PHY Interface Status Interface Avalon-MM Interface Clock and Reset IEEE 1588v2 Time-Stamp Interface Additional Signals for Example Design With IEEE 1588v2 Feature tx_egress_timestamp_96b_valid[n] tx_egress_timestamp_96b_data[n][96] tx_egress_timestamp_96b_fingerprint[n][f] tx_egress_timestamp_64b_valid[n] tx_egress_timestamp_64b_data[n][64] tx_egress_timestamp_64b_fingerprint[n][f] rx_ingress_timestamp_96b_valid[n] rx_ingress_timestamp_96b_data[n][96] rx_ingress_timestamp_64b_valid[n] rx_ingress_timestamp_64b_data[n][64] n: Number of channels s: Number of unshared channels f: Timestamp fingerprint width tx_egress_timestamp_request_in_valid[n] tx_egress_timestamp_request_in_fingerprint[n][f] clock_operation_mode_mode[n][2] pkt_with_crc_mode[n] tx_ingress_timestamp_valid[n] tx_ingress_timestamp_96b_data[n][96] tx_ingress_timestamp_64b_data[n][64] tx_ingress_timestamp_format[n] master_pulse_per_second start_tod_sync[n] pulse_per_second_10g[n] pulse_per_second_1g[n] Packet Classifier Interface TOD Interface Table 15. Clock Domains Clock Frequency (MHz) Interface Signals xgmii_clk Avalon-ST interfaces Packet Classifier interface IEEE 1588v2 time-stamp interface channel_ready[n] (PHY interface) mm_clk 125 Avalon-MM interface pll_ref_clk_1g 125 master_pulse_per_second (ToD interface) Related Links Interface Signals Description on page 85 For more information on each interface signal. 42

43 3 1G/10G Ethernet Design Example 3.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 16. Register Map Byte Offset 0x00_0000 0x00_F000 0x01_0000 Block Client logic Reserved Master TOD Channel 0 0x02_0000 0x02_4000 0x02_7800 0x02_7900 0x02_8000 Reserved PHY 10G TOD 1G TOD LL 10GbE MAC Channel 1 0x03_0000 0x03_4000 0x03_7800 0x03_7900 0x03_8000 Reserved PHY 10G TOD 1G TOD LL 10GbE MAC.. and so forth up to Channel 11. 0x0E_0000 onwards Client Logic Related Links Configuration Registers Description on page 94 For more information on each configuration register. 43

44 4 10GBASE-R Ethernet Design Example 4.1 Features The 10GBASE-R design example demonstrates an Ethernet solution for Intel Arria 10 devices using the LL 10GbE MAC IP core, the native PHY IP core, and a small form factor pluggable (SFP +) module. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Supports dual Ethernet channels operating at 10G using Intel Arria 10 Native PHY. Option to generate the design example with the 10GBASE-R register mode enabled. 140 ns round-trip latency in simulation when the register mode is enabled. Packet monitoring on the TX and RX datapaths. Tested with the Spirent TestCenter. 4.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator Intel Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

45 4 10GBASE-R Ethernet Design Example 4.3 Functional Description Figure 28. Block Diagram 10GBASE-R Ethernet Design Example Design Example (altera_eth_10g_mac_base_r) Avalon-MM Address Decoder S Avalon-MM Master M altera_eth_10g_mac_base_r_wrap S S Adapter LL 10GbE MAC Adapter PHY FIFO Avalon-ST TX/RX Serial Data Transceiver Reset Controller PLL Reset Synchronizer ATX PLL Generated with Platform Designer Generated with IP Catalog Input Clock Reset Design Components Table 17. Design Components Component LL 10GbE MAC Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable 10GBASE-R register mode: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based Use legacy XGMII Interface: Selected. Use legacy Avalon Memory-Mapped Interface: Not Selected Use legacy Avalon Streaming Interface: Not selected The settings when the 10GBASE-R Register mode enabled: Enable 10GBASE-R register mode: Selected Use legacy XGMII Interface: Not selected Use legacy Avalon Memory-Mapped Interface: Selected PHY Intel FPGA Transceiver Native PHY configured for the 10GBASE-R protocol. The register mode preset sets the PHY's TX FIFO MODE to Fast Register. The non-register mode preset sets the PHY's TX FIFO MODE to Phase Compensation and RX FIFO MODE to 10GBASE-R. Transceiver Reset Controller Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. continued... 45

46 4 10GBASE-R Ethernet Design Example Component Address decoder Reset synchronizer ATX PLL Description Decodes the addresses of the components. Synchronizes the reset of all design components. Generates a TX serial clock for the Intel Arria 10 10G transceiver. FIFO Avalon Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. Related Links Intel FPGA Low Latency Ethernet 10G MAC User Guide For more information on the MAC parameters. Intel Arria 10 Transceiver PHY User Guide For more information on the PHY parameters Clocking and Reset Scheme Figure 29. Note: Clocking and Reset Scheme for 10GBASE-R Design Example The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. Generator and Checker reset_n clk rx_sc_fifo_clk_clk tx_sc_fifo_clk_clk FIFO rx_sc_fifo_clk_reset_reset tx_sc_fifo_clk_reset_reset outclk_0 Core PLL outclk_1 TX PLL (1) ref_clk_clk MHz avalon_st_rx_clk_156 avalon_st_rx_156_reset_n avalon_st_rx_clk_312 avalon_st_rx_312_reset_n Avalon-ST Adapter avalon_st_tx_clk_156 avalon_st_tx_156_reset_n avalon_st_tx_clk_312 avalon_st_tx_312_reset_n tx_312_5_clk tx_156_25_clk tx_rst_n LL 10GbE MAC rx_coreclkin tx_coreclkin tx_clkout tx_xcvr_half_clk rx_clkout tx_serial_clk PHY rx_cdr_refclk0 reconfig_clk reconfig_reset sl_clock sl_reset Avalon-MM Adapter ms_clock ms_reset csr_clk csr_rst_n rx_312_5_clk rx_156_25_clk rx_rst_n Reset Synchronizer master_reset_n rx_xcvr_clk_clk sync_rx_rst_reset_n Address Decoder tx_xcvr_half_clk_clk sync_tx_half_rst_reset_n tx_xcvr_clk_clk sync_tx_rst_reset_n clk_csr_clk csr_reset_n Transceiver Reset Controller reset clock Notes: 1. For Intel Arria 10 devices, the design example uses IOPLL. 125 MHz csr_clk 46

47 4 10GBASE-R Ethernet Design Example Figure 30. Clocking and Reset Scheme for 10GBASE-R Design Example with the Register Mode Enabled Generator and Checker reset_n clk rx_sc_fifo_clk_clk tx_sc_fifo_clk_clk FIFO rx_sc_fifo_clk_reset_reset tx_sc_fifo_clk_reset_reset PLL (1) ref_clk_clk MHz avalon_st_rx_clk_156 avalon_st_rx_156_reset_n avalon_st_rx_clk_312 avalon_st_rx_312_reset_n Adapter avalon_st_tx_clk_156 avalon_st_tx_156_reset_n avalon_st_tx_clk_312 avalon_st_tx_312_reset_n csr_clk csr_rst_n LL 10GbE MAC tx_xcvr_clk tx_rst_n rx_xcvr_clk rx_rst_n tx_clkout tx_xcvr_half_clk rx_clkout tx_serial_clk PHY rx_cdr_refclk0 reconfig_clk reconfig_reset Reset Synchronizer master_reset_n rx_xcvr_clk_clk sync_rx_rst_reset_n Address Decoder tx_xcvr_half_clk_clk sync_tx_half_rst_reset_n tx_xcvr_clk_clk sync_tx_rst_reset_n clk_csr_clk csr_reset_n Transceiver Reset Controller reset clock Notes: 1. For Intel Arria 10 devices, the design example uses IOPLL. 125-MHz csr_clk 4.4 Simulation The simulation test case demonstrates how the MAC and PHY configuration is changed at 10-Gbps throughput. The test case is for a single Ethernet channel. At the end of the simulation, the simulator generates the statistics of TX and RX packets in the Transcript window. In the Wave window, the roundtrip latency for the serial loopback is indicated by the measurement cursors that show the time taken to transmit the first data from the Avalon-ST TX interface to be available at the Avalon-ST RX interface. Related Links Compiling and Simulating the Design on page 10 Provides information on the procedure and testbench. 4.5 Hardware Testing Refer to the related links for the procedure to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, and set the following frequencies: Y MHz Y6 125 MHz Related Links Compiling and Testing the Design in Hardware on page 12 Provides information on the procedure and hardware setup. 47

48 4 10GBASE-R Ethernet Design Example Test Cases You can run any of the following tests from the System Console. Table 18. Hardware Test Cases Test Case Command Description SFP+ loopback source gen_conf.tcl The generator generates and sends about 4 billion packets. Wait 6 minutes for it to complete its tasks. source monitor_conf.tcl source show_stats.tcl The monitor checks the number of good and bad packets received. This script displays the values of the statistics counters. Avalon-ST loopback source loopback_conf.tcl This command enables the Avalon-ST loopback. This test is used with an external tester such as Spirent tester. After the test is completed, observe the output displayed in the System Console. Figure 31. Test Output Sample for SFP+ Loopback Figure 32. Test Output Sample Statistics Counters 48

49 4 10GBASE-R Ethernet Design Example Signal Tap Debug Signals The Signal Tap file is included for debugging. This feature is disabled by default. To enable it, set the following assignment: set_global_assignment -name ENABLE_SIGNALTAP ON Table 19. Signal Tap Debug Signals Component Module Name Signal Top-level design example altera_eth_top csr_clk ref_clk_clk master_reset_n block_lock_n tx_ready_export_n rx_ready_export_n Design Example MAC IP core MAC TX MAC RX PHY altera_eth_top.altera_eth_10g_mac_base_r_low_ latency altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_mac altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_mac.alt_em10g32.alt_em10g32 unit.alt_em10g32_tx_top.alt_em10g32_tx_rs_lay er.alt_em10g32_tx_rs_xgmii_layer_ultra altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_mac.alt_em10g32.alt_em10g32 unit.alt_em10g32_rx_top.alt_em10g32_rx_rs_lay er.alt_em10g32_rx_rs_xgmii_ultra altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_baser atx_pll_locked iopll_locked avalon_st_tx_startofpacket avalon_st_tx_endofpacket avalon_st_tx_data avalon_st_tx_ready avalon_st_tx_valid avalon_st_tx_error avalon_st_tx_empty avalon_st_rx_startofpacket avalon_st_rx_endofpacket avalon_st_rx_data avalon_st_rx_ready avalon_st_rx_valid avalon_st_rx_error avalon_st_rx_empty xgmii_tx_valid xgmii_tx_data xgmii_tx_control xgmii rx valid xgmii rx data xgmii rx control xgmii rx link fault status tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_is_lockedtodata tx_clkout 49

50 4 10GBASE-R Ethernet Design Example 4.6 Interface Signals Figure 33. Interface Signals of the 10GBASE-R Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface Status Interface 10GBASE-R Ethernet Design Example avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][32] avalon_st_tx_empty[n][2] avalon_st_pause_data[n][2] avalon_st_txstatus_valid[n] avalon_st_txstatus_data[n][40] avalon_st_txstatus_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][32] avalon_st_rx_empty[n][2] avalon_st_rxstatus_valid[n] avalon_st_rxstatus_data[n][40] avalon_st_rxstatus_error[n][7] tx_ready_export rx_ready_export block_lock atx_pll_locked link_fault_status_xgmii_rx_data[2] (1) Signal is present only in design example with the 10GBASE-R Register Mode enabled. (2) Signal is present only in design example with the 10GBASE-R Register Mode disabled. csr_clk csr_rst_n tx_xcvr_clk (1) tx_rst_n rx_xcvr_clk (1) rx_rst_n rx_xcvr_half_clk (1) tx_xcvr_half_clk (1) ref_clk_clk tx_clk_312 (2) tx_clk_156 (2) rx_clk_312 (2) rx_clk_156 (2) mac_csr_read mac_csr_readdata[32] mac_csr_write mac_csr_writedata[32] mac_csr_address[16] mac_csr_waitrequest phy_csr_read phy_csr_readdata[32] phy_csr_write phy_csr_writedata[32] phy_csr_address[16] phy_csr_waitrequest tx_serial_data rx_serial_data Clock and Reset Avalon-MM Interface PHY Interface 4.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 20. Register Map Byte Offset 0x0000_0000 0x0000_8000 0x0000_D400 0x0000_D600 0x0000_C000 0x0000_D000 0xFFFF_FFFF Block LL 10GbE MAC Native PHY RX SC FIFO TX SC FIFO Packet Generator and Checker Client Logic Related Links Configuration Registers Description on page 94 For more information on each configuration register. Intel FPGA Low Latency Ethernet 10G MAC User Guide For the description of the MAC registers. 50

51 5 1G/2.5G Ethernet Design Example 5.1 Features The 1G/2.5G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC IP core operating at 1G and 2.5G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. Dual-speed Ethernet operation 1G and 2.5G. Support for two channels. Option to generate the design example with the IEEE 1588v2 feature. Testbench and simulation script. Tested with the Spirent TestCenter. Option to generate design example with Partial Reconfiguration Ready. 5.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime Pro Edition software (Partial Reconfiguration Ready) ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator For hardware testing: Intel Arria 10 GX Signal Integrity Development Board (10AX115S3F45E2SGE3) for the design example with the IEEE 1588v2 feature Intel Arria 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3) for the design example without the IEEE 1588v2 feature Cables SMA cable, SFP+, and fiber optic cable Note: Partial Reconfiguration Ready feature is supported from Intel Quartus Prime Pro Edition software version 17.0 onwards. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

52 5 1G/2.5G Ethernet Design Example 5.3 Functional Description The design example consists of various components. The following block diagrams shows the design components and the top-level signals of the design example. Figure 34. Block Diagram 1G/2.5G Ethernet Design Examplewith IEEE 1588v2 Feature Design Example (alt_mge_rd) Ethernet channel 0 (alt_mge_channel) PTP Packet Classifier Pulse Per Second Avalon-ST Local TOD Pulse Per Second Avalon-MM S Address Decoder M... M M S S LL 10GbE MAC PHY S Local TOD TOD Synch TX/RX Serial Data S Avalon-MM Mux Transceiver Reconfig Transceiver Reset Controller fpll S Master TOD Transceiver Reconfig ATX PLL IO PLL Pulse Per Second Master Pulse Per Second Generated from Platform Designer Generated from IP Catalog Reset Input Clock 52

53 5 1G/2.5G Ethernet Design Example Figure 35. Block Diagram 1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature Design Example (alt_mge_rd) Ethernet channel 0 (alt_mge_channel) Avalon-MM S Address Decoder M... M M S S LL 10GbE MAC PHY Avalon-ST TX/RX Serial Data S Avalon-MM Mux Transceiver Reconfig Transceiver Reset Controller ATX PLL fpll Transceiver Reconfig Generated with Platform Designer Generated from IP Catalog Reset Input Clock Design Components Table 21. Design Components Component LL 10GbE MAC PHY Transceiver Reset Controller Avalon-MM Mux Transceiver Reconfig Transceiver Reconfig Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 1G/2.5G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the example design with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format The 1G/2.5G/10G Multi-rate Ethernet PHY IP. The IntelFPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Provides the transceiver reconfig block and system console access to the PHY's Avalon-MM interface. Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa. continued... 53

54 5 1G/2.5G Ethernet Design Example ATX PLL fpll Component Description Generates a TX serial clock for the Intel Arria G transceiver. Generates a TX serial clock for the Intel Arria 10 1G transceiver. Design Components for the IEEE 1588v2 Feature IO PLL Master TOD TOD Synch Local TOD Master Pulse Per Second Pulse Per Second PTP Packet Classifier Generates the clocks for the 1588 design components. The master TOD for all channels. Synchronizes the Master TOD to all Local TODs. The TOD for each channel. Returns pulse per second (pps) for all channels. Returns pulse per second (pps) for each channel. Decodes the packet type of incoming PTP packets and returns the decoded information to the LL10GbE MAC IP core Clocking Scheme Figure 36. Clocking Scheme for the 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature User Logic Core PLL Design Example Channel n MAC Clock PTP Packet Classifier MAC TOD 2.5G TOD 2.5G Sync PPS 2.5G CSR Clock PHY TOD 1G TOD 1G Sync PPS 1G 125 MHz Reference Clock Address Decoder Transceiver Reset Controller 1G/2.5G Reconfiguration Block 1G FPLL 2.5G ATX PLL Sampling IOPLL TOD Master PPS Master 125 MHz Reference Clock 2.5G TX Serial Clock ( MHz) 1G TX Serial Clock (625 MHz) HSSI TX Clock Out 62.5 MHz at 1G, MHz at 2.5G HSSI RX Clock Out 62.5 MHz at 1G, MHz at 2.5G 125 MHz CSR Clock MHz Sampling Clock 80 MHz Sampling Clock MHz MAC Clock 54

55 5 1G/2.5G Ethernet Design Example Figure 37. Clocking Scheme for the 1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature PLL MAC Clock Design Example Channel 0 CDR Reference Clock User Logic MAC PHY CSR Clock Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block 2.5G TX Serial Clock 1G TX Serial Clock 2.5G PLL 1G PLL 125 MHz Reference Clock Channel 1 User Logic MAC PHY CDR Reference Clock 125 MHz Reference Clock 2.5G TX Serial Clock (3125 Mbps) 1G TX Serial Clock (1250 Mbps) HSSI TX Clock Out 62.5 MHz at 1G, MHz at 2.5G 125 MHz CSR Clock MHz MAC Clock 55

56 5 1G/2.5G Ethernet Design Example Reset Scheme The global reset signal of the design example is asynchronous and active-low. Asserting this signal resets all channels and their components. Upon power-up, reset the design example. Figure 38. Reset Scheme for the 1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature Design Example Channel 0 MAC PHY User Logic 2.5G PLL Global Reset Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block User Logic 1G PLL MAC PHY Channel 1 Global Reset Analog Reset PLL Powerdown Digital Reset Reconfiguration Done (triggers reset) 56

57 5 1G/2.5G Ethernet Design Example Figure 39. Reset Scheme for the 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature Design Example Channel n PTP Packet Classifier TOD 2.5G TOD 2.5G Sync PPS 2.5G User Logic MAC PHY TOD 1G TOD 1G Sync PPS 1G TOD Master Address Decoder Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block 1G FPLL 1.5G ATX PLL Sampling IOPLL PPS Master Global Reset Global Reset Digital Reset Analog Reset PLL Powerdown Reconfiguration Done (triggers reset) Partial Reconfiguration Ready When the Partial Reconfiguration Ready option is turned on, the generated hierarchy of the design example is in compliance with the partial reconfiguration flow. There is a clear separation between the hard IP and the soft IP. Hard IPs such as Native PHY, JTAG, transmitter (TX) PLL, and fpll are instantiated at the top-level wrapper of the design example. Certain soft IPs such as transceiver reset controller and TX PLL reset controller are also instantiated at the top-level wrapper of the design example because their functions are tightly coupled to the hard IPs. A wrapper called alt_eth_pr contains the soft IP logic that you can add to the partial reconfiguration region of your design. There is no functionality change after the Partial Reconfiguration Ready option is turned on. Figure 40. 1G/2.5G Ethernet Design Example Hierarchy Without IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned Off altera_eth_top Traffic Controller Core PLL JTAG Master alt_mge_rd TX PLL/fPLL TX PLL Reset Controller mge_channel mge_phy MAC Soft PCS Native PHY Address Decoder Reconfiguration Transceiver Reset Controller Hard Logic Soft Logic 57

58 5 1G/2.5G Ethernet Design Example Figure 41. 1G/2.5G Ethernet Design Example Hierarchy Without IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned On altera_eth_top TX PLL/fPLL TX PLL Reset Controller Core PLL JTAG Master alt_eth_pr Traffic Controller Address Decoder alt_mge_rd Reconfiguration mge_channel mge_phy MAC Soft PCS Native PHY Transceiver Reset Controller Hard Logic Soft Logic Figure 42. Design Example Hierarchy With the IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned Off altera_eth_top Traffic Controller Core PLL JTAG Master alt_mge_rd TX PLL/fPLL TX PLL Reset Controller mge_channel mge_phy MAC Soft PCS Native PHY Address Decoder Master TOD & PPS Reconfiguration Slave TOD TOD Sync Packet Classifier Transceiver Reset Controller Hard Logic Soft Logic Figure 43. Design Example Hierarchy With the IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned On altera_eth_top TX PLL/fPLL TX PLL Reset Controller Core PLL JTAG Master alt_eth_pr Traffic Controller Address Decoder alt_mge_rd Master TOD & PPS Reconfiguration mge_channel MAC Slave TOD mge_phy Soft PCS TOD Sync Packet Classifier Native PHY Transceiver Reset Controller Hard Logic Soft Logic 58

59 5 1G/2.5G Ethernet Design Example Related Links Intel Quartus Prime Pro Edition Handbook Volume 1: Design and Compilation Provides information about partial reconfiguration design. 59

60 5 1G/2.5G Ethernet Design Example 5.4 Simulation Test Case Design Example with the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the design example with an operating speed of 2.5G. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for each channel. 4. Sends the following packets: Non-PTP No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP 5. Repeats steps 2 to 4 for 1G. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 60

61 5 1G/2.5G Ethernet Design Example Figure 44. Sample Simulation Output Test Case Design Example without the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 2.5G. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for both channels. 4. Sends the following packets: 64-byte packet 1518-byte packet 100-byte packet 5. Repeats steps 2 to 4 for 1G. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 61

62 5 1G/2.5G Ethernet Design Example 5.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, and set Y5 to MHz and Y6 to 125 MHz. Related Links Test Procedure Compiling and Testing the Design in Hardware on page 12 Provides information on the procedure and hardware setup. Follow these steps to test the design examples in hardware: 1. Run the following command in the system console to start the test. TEST_EXT_LB <channel> <speed> <burst_size> Example: TEST_EXT_LB 0 2.5G Table 22. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G The PHY speed. burst_size An integer value The number of packets to generate for the test. 2. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters. 62

63 5 1G/2.5G Ethernet Design Example Figure 45. Sample Output Packet Monitor 63

64 5 1G/2.5G Ethernet Design Example Figure 46. Sample Output TX and RX statistics counters 64

65 5 1G/2.5G Ethernet Design Example 5.6 Interface Signal Figure 47. TInterface Signals of the 1G/2.5G Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface PHY Interface Status Interface IEEE 1588v2 Time-Stamp Interface Related Links 1G/2.5G Ethernet Design Example csr_mac_read[n] avalon_st_tx_startofpacket[n] csr_mac_readdata[n][32] avalon_st_tx_endofpacket[n] csr_mac_write[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] csr_mac_writedata[32] avalon_st_tx_error[n] csr_mac_address[n][10] avalon_st_tx_data[n][32] csr_mac_waitrequest[n] avalon_st_tx_empty[n][2] csr_phy_read[n] csr_phy_readdata[n][32] avalon_st_pause_data[n][2] csr_phy_write[n] csr_phy_writedata[32] csr_phy_address[n][5] avalon_st_txstatus_valid[n] csr_phy_waitrequest[n] avalon_st_txstatus_data[n][40] csr_rcfg_read[n] avalon_st_txstatus_error[n][7] csr_rcfg_readdata[32] csr_rcfg_write[n] avalon_st_rx_startofpacket[n] csr_rcfg_writedata[32] avalon_st_rx_endofpacket[n] csr_rcfg_address[2] avalon_st_rx_valid[n] csr_native_phy_rcfg_read[n] avalon_st_rx_ready[n] csr_native_phy_rcfg_readdata[32] avalon_st_rx_error[n][6] csr_native_phy_rcfg_write[n] avalon_st_rx_data[n][32] csr_native_phy_rcfg_writedata[32] avalon_st_rx_empty[n][2] csr_native_phy_rcfg_address[10] csr_native_phy_rcfg_waitrequest[n] avalon_st_rxstatus_valid[n] MAC RX csr_master_tod_read[n] avalon_st_rxstatus_data[n][40] csr_master_tod_readdata[n][32] avalon_st_rxstatus_error[n][7] csr_master_tod_write[n] csr_master_tod_writedata[n][32] rx_serial_data[n] csr_master_tod_address[n][4] tx_serial_data[n] csr_master_tod_waitrequest[n] csr_clk led_link[n] mac_clk led_char_err[n] refclk led_disp_err[n] reset led_an[n] rx_pma_clkout channel_tx_ready[n] tx_digital_reset[n] channel_rx_ready[n] rx_digital_reset[n] Additional Signals for Example Design With IEEE 1588v2 Feature tx_egress_timestamp_96b_valid[n] tx_egress_timestamp_96b_data[n][96] tx_egress_timestamp_96b_fingerprint[n][f] tx_egress_timestamp_64b_valid[n] tx_egress_timestamp_64b_data[n][64] tx_egress_timestamp_64b_fingerprint[n][f] rx_ingress_timestamp_96b_valid[n] rx_ingress_timestamp_96b_data[n][96] rx_ingress_timestamp_64b_valid[n] rx_ingress_timestamp_64b_data[n][64] n: Number of channels f: Timestamp fingerprint width Interface Signals Description on page 85 For more information on each interface signal. tx_egress_timestamp_request_in_valid[n] tx_egress_timestamp_request_in_fingerprint[n][f] clock_operation_mode_mode[n][2] pkt_with_crc_mode[n] tx_ingress_timestamp_valid[n] tx_ingress_timestamp_96b_data[n][96] tx_ingress_timestamp_64b_data[n][64] tx_ingress_timestamp_format[n] master_pulse_per_second start_tod_sync[n] pps[n] Avalon-MM Interface (LL 10GbE MAC) Avalon-MM Interface (1G/2.5G/10G Multi-rate Ethernet PHY) Avalon-MM Interface (Reconfiguration) Avalon-MM Interface (Native PHY Reconfiguration) Avalon-MM Interface (Master ToD Clock) Clock and Reset Packet Classifier Interface TOD Interface 65

66 5 1G/2.5G Ethernet Design Example 5.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 23. Register Map Byte Offset 0x00_0000 0x00_4000 Block Transceiver Reconfiguration Reserved Channel 0 0x01_0000 0x01_8000 0x01_A000 MAC PHY Native PHY Reconfiguration Channel 1 0x02_0000 0x02_8000 0x02_A000 MAC PHY Native PHY Reconfiguration Traffic Controller 0x10_0000 Traffic Controller Related Links Configuration Registers Description on page 94 For more information on each configuration register. 66

67 6 1G/2.5G/10G Ethernet Design Example 6.1 Features The 1G/2.5G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC IP core operating at 1G, 2.5G, and 10G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Tri-speed Ethernet operation 1G, 2.5G, and 10G. Support for two channels. Testbench and simulation script. Tested with the Spirent TestCenter. Option to generate design example with Partial Reconfiguration Ready. 6.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime Pro Edition software (Partial Reconfiguration Ready) ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator For hardware testing: Intel Arria 10 GX SI Development Board (10AX115S4F45E3SGE3) Cables SMA cable, SFP+, and fiber optic cable Note: Partial Reconfiguration Ready feature is supported from Intel Quartus Prime Pro Edition software version 17.0 onwards. 6.3 Functional Description The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

68 6 1G/2.5G/10G Ethernet Design Example Figure 48. Block Diagram 1G/2.5G/10G Ethernet Design Example Design Example (alt_mge_rd) Ethernet channel 0..(n-1) (alt_mge_channel) Avalon-MM S Address Decoder M... M M S S LL 10GbE MAC PHY Avalon-ST TX/RX Serial Data S Avalon-MM Mux Transceiver Reconfig Transceiver Reset Controller ATX PLL (10G) ATX PLL (2.5G) fpll (1G) Transceiver Reconfig Generated with Platform Designer Generated from IP Catalog Reset 10G Input Clock 1G Input Clock Design Components Table 24. Design Components Component LL 10GbE MAC PHY Transceiver Reset Controller Avalon-MM Mux Transceiver Reconfig Transceiver Reconfig ATX PLL fpll Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 1G/2.5G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected The 1G/2.5G/10G Multi-rate Ethernet PHY IP. The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Provides the transceiver reconfig block and system console access to the PHY's Avalon-MM interface. Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa. Generates a TX serial clock for the Intel Arria G and 10G transceiver. Generates a TX serial clock for the Intel Arria 10 1G transceiver. 68

69 6 1G/2.5G/10G Ethernet Design Example Clocking Scheme Figure 49. Clocking Scheme for the 1G/2.5G/10G Ethernet Design Example PLL MAC Clock Design Example Channel 0 CDR Reference Clocks MHz Reference Clock User Logic MAC PHY 10G TX Serial Clock 10G PLL CSR Clock Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block 2.5G TX Serial Clock 1G TX Serial Clock 2.5G PLL 1G PLL 125 MHz Reference Clock Channel 1 User Logic MAC PHY CDR Reference Clock 125 MHz Reference Clock MHz Reference Clock 10G TX Serial Clock ( Mbps) 2.5G TX Serial Clock ( Mbps) MHz MAC Clock 1G TX Serial Clock (625 Mbps) HSSI TX Clock Out 62.5 MHz at 1G, MHz at 2.5G 125 MHz CSR Clock Reset Scheme The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example. 69

70 6 1G/2.5G/10G Ethernet Design Example Figure 50. Reset Scheme for the 1G/2.5G/10G Ethernet Design Example Design Example Channel 0 MAC PHY 10G PLL User Logic 2.5G PLL Global Reset Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block User Logic 1G PLL MAC PHY Channel 1 Global Reset Analog Reset PLL Powerdown Digital Reset Reconfiguration Done (triggers reset) Partial Reconfiguration Ready When the Partial Reconfiguration Ready option is turned on, the generated hierarchy of the design example is in compliance with the partial reconfiguration flow. There is a clear separation between the hard IP and the soft IP. Hard IPs such as Native PHY, JTAG, transmitter (TX) PLL, and fpll are instantiated at the top-level wrapper of the design example. Certain soft IPs such as transceiver reset controller and TX PLL reset controller are also instantiated at the top-level wrapper of the design example because their functions are tightly coupled to the hard IPs. A wrapper called alt_eth_pr contains the soft IP logic that you can add to the partial reconfiguration region of your design. There is no functionality change after the Partial Reconfiguration Ready option is turned on. 70

71 6 1G/2.5G/10G Ethernet Design Example Figure 51. 1G/2.5G/10G Ethernet Design Example Hierarchy when the Partial Reconfiguration Ready Option is Turned Off altera_eth_top Traffic Controller Core PLL JTAG Master alt_mge_rd TX PLL/fPLL TX PLL Reset Controller mge_channel mge_phy MAC Soft PCS Native PHY Address Decoder Reconfiguration Transceiver Reset Controller Hard Logic Soft Logic Figure 52. 1G/2.5G/10G Ethernet Design Example Hierarchy when the Partial Reconfiguration Ready Option is Turned On altera_eth_top TX PLL/fPLL TX PLL Reset Controller Core PLL JTAG Master alt_eth_pr Traffic Controller Address Decoder alt_mge_rd Reconfiguration mge_channel mge_phy MAC Soft PCS Native PHY Transceiver Reset Controller Hard Logic Soft Logic 6.4 Simulation Related Links Intel Quartus Prime Pro Edition Handbook Volume 1: Design and Compilation Provides information about partial reconfiguration design. The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10 Gbps. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_readysignals for both channels. 4. Sends the following packets: 64-byte packet 1518-byte packet 100-byte packet 5. Repeats steps 2 to 4 for 1G and 2.5G. 71

72 6 1G/2.5G/10G Ethernet Design Example When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. Figure 53. Sample Simulation Output 6.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, and set Y5 to MHz and Y6 to 125 MHz. Related Links Test Procedure Compiling and Testing the Design in Hardware on page 12 Provides information on the procedure and hardware setup. Follow these steps to test the design examples in hardware: 1. Run the following command in the system console to start the test. 72

73 6 1G/2.5G/10G Ethernet Design Example TEST_EXT_LB <channel> <speed> <burst_size> Example: TEST_EXT_LB 0 10G Table 25. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. 2. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters. Figure 54. Sample Output Packet Monitor 73

74 6 1G/2.5G/10G Ethernet Design Example Figure 55. Sample Output TX and RX statistics counters 74

75 6 1G/2.5G/10G Ethernet Design Example 6.6 Interface Signals Figure 56. Interface Signals of the 1G/2.5G/10G Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface PHY Interface Status Interface avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_tx_status_valid[ n] avalon_st_tx_status_data[n][40] avalon_st_tx_status_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rx_status_valid[n] avalon_st_rx_status_data[n][40] avalon_st_rx_status_error[n][7] rx_serial_data[n] tx_serial_data[n] led_link[n] led_panel_link[n] led_char_err[n] led_disp_err[n] led_an[n] rx_block_lock[n] channel_tx_ready[n] channel_rx_ready[n] n: Number of channels 1G/2.5G/10G Ethernet Design Example MAC RX csr_mac_read[n] csr_mac_readdata[n][32] csr_mac_write[n] csr_mac_writedata[32] csr_mac_address[n][10] csr_mac_waitrequest[n] csr_phy_read[n] csr_phy_readdata[n][32] csr_phy_write[n] csr_phy_writedata[32] csr_phy_address[n][11] csr_phy_waitrequest[n] csr_rcfg_read csr_rcfg_readdata[32] csr_rcfg_write csr_rcfg_writedata[32] csr_rcfg_address[2] csr_clk mac_clk mac64b_clk refclk_10g refclk_1g2p5g reset rx_pma_clkout tx_digitalreset[n] rx_digitalreset[n] Avalon-MM Interface (LL 10GbE MAC) Avalon-MM Interface (1G/2.5G/10G Multi-rate Ethernet PHY) Avalon-MM Interface (Reconfiguration) Clock and Reset Related Links Interface Signals Description on page 85 For more information on each interface signal. 6.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 26. Register Map Byte Offset 0x00_0000 0x00_4000 Block Transceiver Reconfiguration Reserved Channel 0 0x01_0000 0x01_8000 0x01_A000 MAC PHY Native PHY Reconfiguration Channel 1 0x02_0000 0x02_8000 MAC PHY continued... 75

76 6 1G/2.5G/10G Ethernet Design Example Byte Offset 0x02_A000 Block Native PHY Reconfiguration Traffic Controller 0x10_0000 Traffic Controller Related Links Configuration Registers Description on page 94 For more information on each configuration register. 76

77 7 10G USXGMII Ethernet Design Example 7.1 Features The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC IP core operating at 1G, 2.5G, 5G, and 10G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Supports dual Ethernet channel operating at 1G, 2.5G, 5G, and 10G. On the transmit and receive paths: Provides packet monitoring system. Reports Ethernet MAC statistics counter. Supports testing using different types of Ethernet packet transfer protocol. 7.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator Intel Arria 10 GX SI Development Board (10AX115S4F45E3SGE3) for hardware testing 7.3 Functional Description The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

78 7 10G USXGMII Ethernet Design Example Figure 57. Block Diagram 10G USXGMII Ethernet Design Example Design Example (alt_mge_rd) Ethernet channel 0..(n-1) (alt_mge_channel) Avalon-MM S Address Decoder M... M S S LL 10GbE MAC PHY Avalon-ST TX/RX Serial Data MHz MHz Transceiver Reset Controller ATX PLL (10G) Core PLL Generated with Platform Designer Generated from IP Catalog Reset 10G Input Clock Design Components Table 27. Design Components Component LL 10GbE MAC PHY Channel address decoder Multi-channel address decoder Top address decoder Transceiver Reset Controller ATX PLL Core PLL Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 1G/2.5G/5G/10G (USXGMII) Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based Use legacy XGMII Interface: Not selected Use legacy Avalon Memory-Mapped Interface: Not selected Use legacy Avalon Streaming Interface: Selected The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP. Decodes the addresses of the components in each Ethernet channel. Decodes the addresses of the components used by all channels, such as the Master ToD module. Decodes the addresses of the top-level components, such as the Traffic Controller. The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Generates a TX serial clock for the Intel Arria 10 transceiver. Generates clocks for all design components. 78

79 7 10G USXGMII Ethernet Design Example Clocking Scheme Figure 58. Clocking Scheme for 10G USXGMII Ethernet Design Example PLL User Logic MAC Clock Design Example MAC Channel 0 PHY CDR Reference Clock CSR Clock Transceiver Reset Controller 10G TX Serial Clock 10G PLL MHz Reference Clock Channel 1 User Logic MAC PHY CDR Reference Clock MHz Reference Clock 10G TX Serial Clock ( MHz) 125 MHz CSR Clock MHz MAC Clock Reset Scheme The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example. 79

80 7 10G USXGMII Ethernet Design Example Figure 59. Reset Scheme for 10G USXGMII Ethernet Design Example Design Example Channel 0 User Logic MAC XGMII with Data Valid PHY Global Reset Transceiver Reset Controller 10G PLL User Logic MAC XGMII with Data Valid PHY Channel 1 Global Reset Analog Reset PLL Powerdown Digital Reset 7.4 Simulation The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_readysignals for both channels. 4. Sends the following packets: 64-byte packet 1518-byte packet 100-byte packet 5. Repeats steps 2 to 4 for 1G, 2.5G, and 5G. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 80

81 7 10G USXGMII Ethernet Design Example Figure 60. Sample Simulation Output 7.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, and set Y5 to MHz and Y6 to 125 MHz. Related Links Test Procedure Compiling and Testing the Design in Hardware on page 12 Provides information on the procedure and hardware setup. Follow these steps to test the design examples in hardware: 1. Run the following command in the system console to enable PHY serial loopback on Channel 0: SET_CHANNEL_BASE_ADDR 0 SETPHY_SERIAL_LLPBK 81

82 7 10G USXGMII Ethernet Design Example Note: This step is only required if you are using Intel Arria 10 GX SI Development Board rev E and above, and on Channel 0 only. 2. Run the following command in the system console to start the test. TEST_EXT_LB <channel> <speed> <burst_size> Example: TEST_EXT_LB 0 10G Table 28. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G, 5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. 3. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters. Figure 61. Sample Output Packet Monitor 82

83 7 10G USXGMII Ethernet Design Example Figure 62. Sample Output TX and RX Statistics Counters 7.6 Interface Signals Figure 63. Interface Signals of the 10G USXGMII Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface 10G USXGMII Ethernet Design Example avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_tx_status_valid[n] avalon_st_tx_status_data[n][40] avalon_st_tx_status_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rx_status_valid[n] avalon_st_rx_status_data[n][40] avalon_st_rx_status_error[n][7] n: Number of channels csr_clk refclk_10g mac32b_clk mac64_clk rx_pma_clkout[ n] reset tx_digitalreset[ n] rx_digitalreset[ n] csr_mch_read[n] csr_mch_readdata[n][32] csr_mch_write[n] csr_mch_writedata[32] csr_mch_address[n][20] csr_mch_waitrequest[n] tx_serial_data[ n] rx_serial_data[ n] channel_tx_ready channel_rx_ready rx_block_lock led_an Clock and Reset Avalon-MM Interface PHY Interface Status Interface 83