Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide

Transcription

1 Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Latest document on the web: PDF HTML

2 Contents Contents 1. Quick Start Directory Structure Generating the Design Procedure Design Example Parameters Compiling and Simulating the Design Procedure Testbench Compiling and Testing the Design in Hardware Procedure Hardware Setup M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Simulation Test Case Design Example with the IEEE 1588v2 Feature Test Case Design Example without the IEEE 1588v2 Feature Hardware Testing Test Cases Signal Tap Debug Signals Interface Signals Configuration Registers G/10G Ethernet Design Example for Intel Arria 10 Devices Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Simulation Test Case Design Example with the IEEE 1588v2 Feature Test Case Design Example without the IEEE 1588v2 Feature Hardware Testing Test Cases Signal Tap Debug Signals Interface Signals Configuration Registers GBASE-R Ethernet Design Example for Intel Arria 10 Devices Features Hardware and Software Requirements Functional Description

3 Contents Design Components Clocking and Reset Scheme Simulation Hardware Testing Test Cases Signal Tap Debug Signals Interface Signals Configuration Registers G/2.5G Ethernet Design Example for Intel Arria 10 Devices Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Partial Reconfiguration Ready Simulation Test Case Design Example with the IEEE 1588v2 Feature Test Case Design Example without the IEEE 1588v2 Feature Hardware Testing Test Procedure Interface Signal Configuration Registers G/2.5G/10G Ethernet Design Example for Intel Arria 10 Devices Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Partial Reconfiguration Ready Timing Constraints Simulation Hardware Testing Test Procedure Interface Signals Configuration Registers M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel Arria 10 Devices Features Hardware and Software Requirements Functional Description Design Components Clocking Scheme Reset Scheme Simulation Test Case Hardware Testing Test Procedure

4 Contents 7.6. Interface Signals Configuration Registers Interface Signals Description Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals Status Interface IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals Configuration Registers Description Register Access Definition Low Latency Ethernet 10G MAC PHY G/10G PHY G/2.5G/5G/10G Multi-rate PHY Transceiver Reconfiguration TOD Archives Document Revision History for the Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User

5 1. Quick Start The Intel FPGA Low Latency 10G Ethernet (LL 10GbE) MAC Intel FPGA IP core for Intel Arria 10 devices provides the capability of generating design examples for selected configurations. Figure 1. Development Stages for the Design Example Compilation (Simulator) Functional Simulation Design Example Generation Compilation (Quartus Prime) Hardware Testing Related Information 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices on page 14 Provides details on the 10M/100M/1G/10G Ethernet design examples. 1G/10G Ethernet Design Example for Intel Arria 10 Devices on page 30 Provides details on the 1G/10G Ethernet design examples. 10GBASE-R Ethernet Design Example for Intel Arria 10 Devices on page 44 Provides details on the 10GBASE-R Ethernet design examples. 1G/2.5G Ethernet Design Example for Intel Arria 10 Devices on page 51 Provides details on the 1G/2.5G Ethernet design examples. 1G/2.5G/10G Ethernet Design Example for Intel Arria 10 Devices on page 67 Provides details on the 1G/2.5G/10G Ethernet design example. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel Arria 10 Devices on page 78 Provides details on the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered

6 1. Quick Start 1.1. Directory Structure Figure 2. Directory Structure for the Design Example <Design Example> rtl altera_eth_multi_channel.sv altera_eth_channel.sv <Design Component> simulation ed_sim models cadence mentor hwtesting system_console output_files altera_eth_top.sof altera_eth_top.qpf altera_eth_top.qsf altera_eth_top.sv altera_eth_top.sdc <Design Component> synopsys vcs xcelium Table 1. Directory and File Description Directory/File Description altera_eth_top.qpf altera_eth_top.qsf altera_eth_top.sv altera_eth_top.sdc rtl rtl/ altera_eth_10g_mac_base_r.sv rtl/ altera_10g_mac_base_r_wrap.v rtl/altera_mge_rd.sv rtl/altera_mge_channel.v rtl/altera_eth_channel.v rtl/ altera_eth_multi_channel.sv rtl/altera_eth_channel_1588.v rtl/ altera_eth_multi_channel_1588.sv rtl/ altera_mge_multi_channel.sv rtl/altera_mge_channel.v rtl/<design Component> simulation/ed_sim/models simulation/ed_sim/cadence simulation/ed_sim/mentor Intel Quartus Prime project file. Intel Quartus Prime settings file. Design example top-level HDL. Synopsys Design Constraints (SDC) file. The folder that contains the design example synthesizable components. Design example DUT top-level files for 10GBASE-R Ethernet design example. Design example DUT top-level files for the following Ethernet design examples: 1G/2.5G with 1588v2 feature 1G/2.5G/10G Design example DUT top-level files for the following Ethernet design examples: 10M/100M/1G/10G 1G/10G Design example DUT top-level files for the following Ethernet design examples: 10M/100M/1G/10G with with 1588v2 feature 1G/10G with 1588v2 feature Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example. The folder for each synthesizable component including Platform Designer generated IPs, such as LL 10GbE MAC, PHY, and FIFO. The folder that contains the testbench files. The folder that contains the simulation script. It also serves as a working area for the simulator. continued... 6

7 1. Quick Start Directory/File Description simulation/ed_sim/ synopsys/vcs simulation/ed_sim/xcelium hwtesting/system_console output_files The folder that contains system console scripts for hardware testing. The folder that contains Intel Quartus Prime output files including Intel Quartus Prime compilation reports and design programing file (.sof file). 7

8 1. Quick Start 1.2. Generating the Design Procedure You can generate the design example from the IP Parameter Editor. Start Parameter Editor Specify IP Variation and Select Device Select Design Parameters Specify Example Design Initiate Design Generation Figure 3. Example Design Tab Initiates Design Generation Preset Library 1. Select Tools IP Catalog to open the IP Catalog and select Low Latency Ethernet 10G MAC Intel FPGA IP. The IP parameter editor appears. 2. Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK. 3. To generate a design example, select a design example preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The Parameter Editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab. 4. Specify the parameters in the Example Design tab. 5. Click the Generate Example Design button. The software generates all design files in sub-directories. You require these files to run simulation, compilation, and hardware testing. 8

9 1. Quick Start Related Information Directory Structure on page 6 Provides more information about the generated design example directories and files Design Example Parameters Table 2. Parameters in the Example Design Tab Parameter Description Select Design Example Design Files for Simulation or Synthesis Generate File Format Select Board Change Target Device Specify Number of Channels Enable ADME support Partial Reconfiguration Ready Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design. The files to generate for the different development phase. Simulation generates the necessary files for simulating the example design. Synthesis generates the synthesis files. Use these files to compile the design in the Intel Quartus Prime software for hardware testing and perform static timing analysis. The format of the RTL files for simulation Verilog or VHDL. Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit. If this menu is not available, there is no supported board for the options that you select. Intel Arria 10 GX Transceiver Signal Integrity Development Kit: This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel FPGA IP development kit. If your board revision has a different device grade, you can change the target device. Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel FPGA IP device, a custom designed board with Intel FPGA IP device, or a standard Intel FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit. No Development Kit: This option excludes the hardware aspects for the design example. Select this parameter to display and select all devices for the Intel FPGA IP development kit. The number of Ethernet channels. Turn on this option to enable Transceiver ADME feature. Note: This option is only available from Intel Quartus Prime Pro Edition version 17.0 onwards When this option is enabled, the generated hierarchy of the design example is compliance with the partial reconfiguration flow, where there is clear separation between hard IP and soft IP, without any functionality changes. Hard IPs such as Native PHY, JTAG, transmitter PLL, and FPLL are instantiated at the top-level wrapper of design example. Note: This option is only available from Intel Quartus Prime Pro Edition version 17.1 onwards 9

10 1. Quick Start 1.3. Compiling and Simulating the Design Procedure You can compile and simulate the design by running a simulation script from the command prompt. Change to Testbench Directory Run <Simulation Script> Analyze Results 1. At the command prompt, change the working directory to <Example Design> \simulation\ed_sim\<simulator>. 2. Run the simulation script for the simulator of your choice. Simulator Working Directory Command ModelSim* <Example Design>/simulation/ed_sim/mentor vsim -c -do tb_run.tcl VCS* <Example Design>/simulation/ed_sim/ synopsys/vcs sh tb_run.sh NCSim <Example Design>/simulation/ed_sim/cadence sh tb_run.sh Xcelium* <Example Design>/simulation/ed_sim/xcelium sh tb_run.sh A successful simulation ends with the following message: Simulation stopped due to successful completion! Simulation passed. After successful completion, you can analyze the results. 10

11 1. Quick Start Testbench Figure 4. Block Diagram of the Testbench Testbench Avalon-MM Control Register Ethernet Packet Monitor Avalon-MM Avalon-ST Transmit Frame Generator Avalon-ST Receive Frame Monitor avalon_bfm_wrapper.sv Avalon Driver TX data RX data Ethernet Packet Monitor DUT Ordinary Clock Channel 0 Channel 1... Channel n-1 Channel n Loopback on Serial Table 3. Testbench Components Component Description Device under test (DUT) Avalon driver Ethernet packet monitors The design example. Consists of Avalon-ST master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon-MM interface of the DUT. Monitor TX and RX datapaths, and display the frames in the simulator console. 11

12 1. Quick Start 1.4. Compiling and Testing the Design in Hardware Procedure You can compile and test the design in the supported Intel FPGA development kit. Compile Design in Quartus Prime Software Set up Hardware Program Device Test Design in Hardware 1. Launch the Intel Quartus Prime software and open the design example project file. Select Processing Start Compilation to compile the design example. The timing constraints for the design example and the design components are automatically loaded during compilation. 2. Connect the development board to the host computer. 3. Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example. Note: For the frequencies to set, refer to the Hardware Testing section in the respective design example chapter. 4. In the Intel Quartus Prime software, select Tools Programmer to configure the FPGA on the development board using the generated.sof file. 5. Reset the system by pressing the PB0 push button. 6. In the Intel Quartus Prime software, select Tools System Debugging Tools System Console to launch the system console. 7. Change the working directory to <Example Design>\hwtesting \system_console. 8. Initialize the design command list by running this command: source main.tcl. Note: For a design example that does not provide the main.tcl file, refer to the Hardware Testing section in the respective design example chapter. You can now run any of the predefined hardware tests from the System Console. Observe the test results displayed. Related Information Intel Arria 10 GX Transceiver Signal Integrity Development Kit Webpage 12

13 1. Quick Start Hardware Setup Figure 5. Block Diagram of the Hardware Setup PC Intel System Console Software Intel Arria 10 GX Transceiver Signal Integrity Development Board Intel Arria 10 GX FPGA JTAG TAP Ethernet Frame Generation Controller & Monitoring (Master) Ethernet Channel 0 System Controller Ethernet Frame Generation & Monitoring (Slave) Ethernet Frame Generation & Monitoring Ethernet Channel 1 Ethernet Channel n - 1 (2) (1) Ethernet Frame Generation & Monitoring Ethernet Channel n (1) Use this type of loopback to test IEEE 1588v2 features. (2) Use this type of loopback to test features other than IEEE 1588v2. 13

14 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices 2.1. Features The 10M/100M/10G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel FPGA IP core operating at various speeds. Generate the design example from the Example Design tab of the LL 10GbE Intel FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. Multi-speed Ethernet operation 10M, 100M, 1G, and 10G. Support for up to 12 channels. Packet monitoring on the TX and RX datapaths. Option to generate the design example with the IEEE 1588v2 feature. Tested with the Spirent TestCenter Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium simulators Intel Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered

15 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices 2.3. Functional Description The design examples consist of various components. The following block diagrams show the design components and the top-level signals of the design examples. Figure 6. Block Diagram 10M/100M/1G/10G Ethernet Design Example without IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel) Ethernet channel 0 (altera_eth_channel) Address Decoder (address_decoder_channel) S Avalon-MM Master M S S FIFO Adapter LL 10GbE MAC Adapter PHY Avalon-ST TX/RX Serial Data Transceiver Reset Controller ATX PLL fpll PLL Reset Controller Generated with Platform Designer Generated with IP Catalog Input Clock Reset Figure 7. Block Diagram 10M/100M/1G/10G Ethernet Design Example with IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel_1588) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel_1588) Ethernet channel 0 (altera_eth_channel_1588) Address Decoder (address_decoder_channel) S Avalon-MM Master M PTP Packet Classifier Adapter LL 10GbE S MAC Adapter S PHY Pulse Per Second S Local TOD TOD Sync Avalon-ST 1G/10G Pulse Per Second IEEE 1588v2 Timestamp TX/RX Serial Data Transceiver Reset Controller Generated from Platform Designer Generated from IP Catalog PLL Input Clock Reset Controller Reset ATX PLL fpll S Master TOD Pulse Per Second Master Pulse Per Second Design Components Table 4. Design Components Component LL 10GbE MAC Description The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration: continued... 15

16 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Component Description Speed: 10M/100M/1G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the design example with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format PHY Address decoder Multi-channel address decoder Reset controller Transceiver Reset Controller PLL ATX PLL fpll MDIO FIFO The 1G/10G and 10GBASE-KR PHY Intel Arria 10 FPGA IP. The design example uses the 1G/10G IP variant. Decodes the addresses of the components in each Ethernet channel. Decodes the addresses of the components used by all channels, such as the Master TOD module. Synchronizes the reset of all design components. The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver. Generates clocks for all design components. Generates a TX serial clock for the Intel Arria 10 10G transceiver. Generates a TX serial clock for the Intel Arria 10 1G transceiver. Provides an MDIO interface to the external PHY. The Avalon Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH and SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv. Design Components for the IEEE 1588v2 Feature Master TOD TOD Sync Local TOD Master Pulse Per Second Pulse Per Second PTP packet classifier The master TOD for all channels. Synchronizes the Master TOD to all Local TODs. The TOD for each channel. Returns pulse per second (pps) for all channels. Returns pulse per second (pps) for each channel. Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel FPGA IP core. Related Information Low Latency Ethernet 10G MAC Intel FPGA IP Core User For more information on the MAC parameters. Intel Arria 10 Transceiver PHY User For more information on the PHY parameters. 16

17 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices KDB Link: Why do I see underflow errors when receiving Jumbo frames on the Low Latency Ethernet 10G MAC Design Examples? External FIFO buffer limitation for Intel Arria 10 Low Latency Ethernet 10G MAC Design Example. 17

18 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Clocking Scheme The following diagrams show the clocking scheme for the design example. Figure 8. Note: Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. Avalon-MM altera_eth_multi_channel_1588 address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels altera_eth_channel_1588 altera_eth_channel_1588 address_decoder_channel PTP Packet Classifier Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters tx_serial_clk_10g tx_serial_clk_1g 125 MHz tx_clkout S PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout 10G Pulse Per Second period_clk S 10G Local TOD clk Slave Master 10G TOD Sync 1G Pulse Per Second period_clk S 1G Local TOD clk Master Slave 1G TOD Sync Transceiver Reset Controller Legend MHz MHz 125 MHz 125 MHz 0x01_0000(Master TOD) Notes: 1. n = (SHARED_REFCLK_EN == 1)? 1 : NUM_CHANNELS. 2. Sampling clock for 10G TOD sync is MHz. 3. Sampling clock for 1G TOD sync is MHz. 4. For Intel Arria 10 devices, the design example uses IOPLL. (1) n Channel xgmii_clk[n] MHz PLL 1 (4) MHz pll_ref_clk_10g[n] MHz MHz pll_ref_clk_10g(0) 625 MHz pll_ref_clk_1g(0) (2) (3) (NUM CHANNEL - 1) / ATX PLL fpll (NUM CHANNEL - 1) / PLL 2 pll_ref_clk_1g[n] 125 MHz rx_recovered_clk[n] mm_clk 125 MHz period_clk S Master TOD clk Master Pulse Per Second Figure 9. Note: Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. altera_eth_multi_channel altera_eth_channel altera_eth_channel TX / RX FIFO Avalon-MM address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels address_decoder_channel Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters 125 MHz tx_serial_clk_10g tx_serial_clk_1g tx_clkout S Arria 10 PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout Transceiver Reset Controller MHz MHz MHz 625 MHz Legend MHz MHz 125 MHz 125 MHz Note: 1. n = (SHARED_REFCLK_EN == 1)? 1: NUM_CHANNELS 2. For Intel Arria 10 devices, the design example uses IOPLL. xgmii_clk[n] n Channel (1) PLL (2) pll_ref_clk_10g[n] MHz (NUM CHANNEL - 1) / ATX PLL pll_ref_clk_10g(0) fpll pll_ref_clk_1g[n] 125 MHz (NUM CHANNEL - 1) / pll_ref_clk_1g(0) rx_recovered_clk[n] dc_fifo_tx_clk MHz dc_fifo_rx_clk MHz 18

19 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Reset Scheme The reset signals of the design example master_reset_n and channel_reset_n[n:0] are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components. Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example. Figure 10. Master Reset master_reset_n Ethernet Design Example with IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz PLL MHz Ethernet Channel n Master PPS Master TOD Transceiver Reset Controller ATX PLL fpll master_reset_n Ethernet Design Example without IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz Ethernet Channel n Transceiver Reset Controller ATX PLL fpll 19

20 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the transceiver reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together. The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv Figure 11. Channel Reset mm_reset Ethernet Design Example with IEEE 1588v2 Feature datapath_reset LL 10GbE MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller TOD 10G TOD SYN 96B_10G PPS 10G TOD SYN 64B_10G TOD 1G TOD SYN 96B_1G PPS 1G TOD SYN 64B_1G Address Decoder datapath_reset Ethernet Design Example without IEEE 1588v2 Feature mm_reset MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller Address Decoder 2.4. Simulation The simulation test cases demonstrate how the channel speed and the configuration of the PHY are changed. These test cases use circular loopback on the total number of Ethernet channels. The following table describes the steps to change the speed and configuration. 20

21 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Table 5. Ethernet Operations Operation Configuring the PHY speed. Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. Changing the speed between 1 Gbps, 100 Mbps, and 10 Mbps in SGMII. Description Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), 1G1000Base-X or 1G/100M/10M SGMII. Write one of the following values to the PHY's register at address offset 0x12C0. 0x01: Turn on the auto-detection mode. In this mode, the PHY automatically detects the speed. 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps. 0x41: Turn off the auto-detection mode and set the speed to 10 Gbps. Example To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11 To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01 Set the port to 1000BASE-X. Write one of the following values to the PHY's register at offset 0x x01: Enable SGMII and set the speed to 10 Mbps. 0x03: Enable SGMII and auto-negotiation. 0x05: Enable SGMII mode and set the speed to 100 Mbps 0x09: Enable SGMII mode and set the speed to 1 Gbps Example: To set port 0 to SGMII and 100 Mbps: Set port 0 to 1000Base-X: write_32 0x02_52C0 0x11 Set port 0 to 100-Mbps SGMII: write_32 0x02_5290 0x05 Related Information Compiling and Simulating the Design on page 10 Provides information on the procedure and testbench Test Case Design Example with the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the design example with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the design example asserts the channel_ready signal for each channel. 4. Sends the following packets: Non-PTP No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP 5. Repeats steps 2 to 4 for other operating speeds. 21

22 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. Figure 12. Sample Simulation Output Test Case Design Example without the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the example design asserts the channel_ready signal for each channel. 4. Sends the following packets: 22

23 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Normal data frame, 64Bytes SVLAN data frame, broadcast, 64Bytes VLAN data frame, unicast, 500Bytes 5. Repeats steps 2 to 4 for other operating speeds. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. Figure 13. Sample Simulation Output 2.5. Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control application, which is part of the development kit, set the following frequencies: 23

24 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Y MHz Y6 125 MHz Test Cases Related Information Compiling and Testing the Design in Hardware on page 12 More information on the procedure and hardware setup. Clock Control More information on using the Clock Control application. You can run any of the following tests from the System Console. Table 6. Hardware Test Cases Test Case Command Example PHY internal serial loopback SMA loopback TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_size> For the design with the IEEE 1588v2 feature: TEST_SMA_LB <channel> <speed_test> <burst_size> For the design without the IEEE 1588v2 feature: TEST_SMA_LOOPBACK <channel> <speed_test> <burst_size> TEST_PHYSERIAL_LOOPBACK 0 10G 1000 TEST_SMA_LB 0 10G 1000 Table 7. Command Parameters Parameter Valid Values Description channel 0 to the number of channel specified for the design The number of channels for the test. speed_test 10G, 1G, 100M, 10M The PHY speed. burst_size The number of packets to generate for the test. When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output. 24

25 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Figure 14. Sample Test Output Ethernet Packet Monitor Figure 15. Sample Test Output Statistics Counters Signal Tap Debug Signals The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below: set_global_assignment -name ENABLE_SIGNALTAP ON 25

26 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Table 8. Signal Tap Debug Signals Component Module Name Signal Top-level design example altera_eth_top mm_clk ref_clk_1g ref_clk_10g channel_ready_n channel_reset_n master_reset_n Multi-channel wrapper Design example without the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel Design example with the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel_1588 pll_locked pll_1_locked pll_2_locked (only for the design example with the IEEE 1588v2 feature) pll_locked_10g pll_locked_1g MAC IP core <n>.altera_eth_10g_mac (1) avalon_st_tx_startofpacket avalon_st_tx_endofpacket avalon_st_tx_data avalon_st_tx_ready avalon_st_tx_valid avalon_st_tx_error avalon_st_tx_empty avalon_st_rx_startofpacket avalon_st_rx_endofpacket avalon_st_rx_data avalon_st_rx_ready avalon_st_rx_valid avalon_st_rx_error avalon_st_rx_empty PHY <n>.altera_eth_10gkr_phy (1) led_an led_char_err led_disp_err led_link mii_speed_sel rx_analogreset rx_block_lock rx_cal_busy rx_is_lockedtodata rx_digitalreset rx_data_ready tx_analogreset tx_digitalreset continued... (1) Replace n with: altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature. altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature. 26

27 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices Component Module Name Signal XGMII <n>.altera_eth_10g_mac.alt_em xgmii_tx_control 10g32.alt_em10g32unit (1) xgmii_tx_data xgmii_rx_control xgmii_rx_data link_fault_status_xgmii_rx_ data GMII <n>.altera_eth_10g_mac (1) gmii_tx_d gmii_tx_en gmii_tx_err gmii_rx_d gmii_rx_dv gmii_rx_err MII <n>.altera_eth_10g_mac (1) mii_tx_d mii_tx_en mii_tx_err mii_rx_dv mii_rx_err 27

28 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices 2.6. Interface Signals Figure 16. Interface Signals of the 10M/100M/1G/10G Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_txstatus_valid[n] avalon_st_txstatus_data[n][40] avalon_st_txstatus_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rxstatus_valid[n] avalon_st_rxstatus_data[n][40] avalon_st_rxstatus_error[n][7] 10M/100M/1G/10G Ethernet Design Example MAC RX rx_serial_data[n] tx_serial_data[n] ethernet_1g_an[n] ethernet_1g_char_err[n] ethernet_1g_disp_err[n] channel_ready[n] read readdata[32] write writedata[32] address[20] waitrequest mm_clk pll_ref_clk_1g[s] pll_ref_clk_10g[s] cdr_ref_clk_1g[s] cdr_ref_clk_10g[s] channel_reset_n[n] master_reset_n xgmii_clk[s] rx_recovered_clk[n] PHY Interface Status Interface Avalon-MM Interface Clock and Reset IEEE 1588v2 Time-Stamp Interface Additional Signals for Example Design With IEEE 1588v2 Feature tx_egress_timestamp_96b_valid[n] tx_egress_timestamp_96b_data[n][96] tx_egress_timestamp_96b_fingerprint[n][f] tx_egress_timestamp_64b_valid[n] tx_egress_timestamp_64b_data[n][64] tx_egress_timestamp_64b_fingerprint[n][f] rx_ingress_timestamp_96b_valid[n] rx_ingress_timestamp_96b_data[n][96] rx_ingress_timestamp_64b_valid[n] rx_ingress_timestamp_64b_data[n][64] n: Number of channels s: Number of unshared channels f: Timestamp fingerprint width tx_egress_timestamp_request_in_valid[n] tx_egress_timestamp_request_in_fingerprint[n][f] clock_operation_mode_mode[n][2] pkt_with_crc_mode[n] tx_ingress_timestamp_valid[n] tx_ingress_timestamp_96b_data[n][96] tx_ingress_timestamp_64b_data[n][64] tx_ingress_timestamp_format[n] master_pulse_per_second start_tod_sync[n] pulse_per_second_10g[n] pulse_per_second_1g[n] Packet Classifier Interface TOD Interface Related Information Interface Signals Description on page 88 For more information on each interface signal. 28

29 2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices 2.7. Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 9. Register Map Byte Offset 0x00_0000 0x00_F000 0x01_0000 Block Client logic Reserved Master TOD Channel 0 0x02_0000 0x02_4000 0x02_7800 0x02_7900 0x02_8000 Reserved PHY 10G TOD 1G TOD LL 10GbE MAC Channel 1 0x03_0000 0x03_4000 0x03_7800 0x03_7900 0x03_8000 Reserved PHY 10G TOD 1G TOD LL 10GbE MAC.. and so forth up to Channel 11. 0x0E_0000 onwards Client Logic Related Information Configuration Registers Description on page 97 For more information on each configuration register. 29

30 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices 3.1. Features The 1G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel FPGA IP core operating at 1G and 10G. Generate the design example from the Example Design tab of the LL 10GbE Intel FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. Dual-speed Ethernet operation 1G and 10G. Support for up to 12 channels. Packet monitoring on the TX and RX datapaths. Option to generate the design example with the IEEE 1588v2 feature. Tested with the Spirent TestCenter Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium simulators Intel Arria 10 GX Transceiver Signal Integrity Development Kit for hardware testing Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered

31 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices 3.3. Functional Description The design example consists of various components. The following block diagrams show the design components and the top-level signals of the design example. Figure 17. Block Diagram 1G/10G Ethernet Design Example with IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel_1588) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel_1588) Ethernet channel 0 (altera_eth_channel_1588) Address Decoder (address_decoder_channel) S Avalon-MM Master M PTP Packet Classifier Adapter LL 10GbE S MAC Adapter S PHY Pulse Per Second S Local TOD TOD Sync Avalon-ST 1G/10G Pulse Per Second IEEE 1588v2 Timestamp TX/RX Serial Data Transceiver Reset Controller Generated from Platform Designer Generated from IP Catalog PLL Input Clock Reset Controller Reset ATX PLL fpll S Master TOD Pulse Per Second Master Pulse Per Second Figure 18. Block Diagram 1G/10G Ethernet Design Example without IEEE 1588v2 Feature Avalon-MM Multi-channel Wrapper (altera_eth_multi_channel) Multi-channel Address Decoder (address_decoder_multi_channel) S Avalon-MM Master M Ethernet channel n (altera_eth_channel) Ethernet channel 0 (altera_eth_channel) Address Decoder (address_decoder_channel) S Avalon-MM Master M S S FIFO Adapter LL 10GbE MAC Adapter PHY Avalon-ST TX/RX Serial Data Transceiver Reset Controller ATX PLL fpll PLL Reset Controller Generated with Platform Designer Generated with IP Catalog Input Clock Reset Design Components Table 10. Design Components of the 1G/10G Ethernet Design Example LL 10GbE MAC Component Description The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration: continued... 31

32 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices Component Description Speed: 1G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the design example with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format PHY Address Decoder Reset Controller Transceiver Reset Controller PLL ATX PLL FIFO The 1G/10G and 10GBASE-KR PHY Intel Arria 10 FPGA IP. The design example uses the 1G/10G IP variant. Decodes the addresses of the components in each Ethernet channel. Synchronizes the reset of all design components. The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver. Generates clocks for all design components. Generates a TX serial clock for the Intel Arria 10 10G transceiver. The Avalon Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH & SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv. Related Information Low Latency Ethernet 10G MAC Intel FPGA IP Core User For more information on the MAC parameters. Intel Arria 10 Transceiver PHY User For more information on the PHY parameters. KDB Link: Why do I see underflow errors when receiving Jumbo frames on the Low Latency Ethernet 10G MAC Design Examples? External FIFO buffer limitation for Intel Arria 10 Low Latency Ethernet 10G MAC Design Example. 32

33 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices Clocking Scheme The following diagrams show the clocking scheme for the design example. Figure 19. Note: Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. Avalon-MM altera_eth_multi_channel_1588 address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels altera_eth_channel_1588 altera_eth_channel_1588 address_decoder_channel PTP Packet Classifier Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters tx_serial_clk_10g tx_serial_clk_1g 125 MHz tx_clkout S PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout 10G Pulse Per Second period_clk S 10G Local TOD clk Slave Master 10G TOD Sync 1G Pulse Per Second period_clk S 1G Local TOD clk Master Slave 1G TOD Sync Transceiver Reset Controller Legend MHz MHz 125 MHz 125 MHz 0x01_0000(Master TOD) Notes: 1. n = (SHARED_REFCLK_EN == 1)? 1 : NUM_CHANNELS. 2. Sampling clock for 10G TOD sync is MHz. 3. Sampling clock for 1G TOD sync is MHz. 4. For Intel Arria 10 devices, the design example uses IOPLL. (1) n Channel xgmii_clk[n] MHz PLL 1 (4) MHz pll_ref_clk_10g[n] MHz MHz pll_ref_clk_10g(0) 625 MHz pll_ref_clk_1g(0) (2) (3) (NUM CHANNEL - 1) / ATX PLL fpll (NUM CHANNEL - 1) / PLL 2 pll_ref_clk_1g[n] 125 MHz rx_recovered_clk[n] mm_clk 125 MHz period_clk S Master TOD clk Master Pulse Per Second Figure 20. Note: Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design. altera_eth_multi_channel altera_eth_channel altera_eth_channel TX / RX FIFO Avalon-MM address_decoder_multi_channel 0x02_0000 0x03_0000 N Channels address_decoder_channel Adapters tx/rx_312_5_clk gmii_tx_clk S LL 10GbE MAC csr_clk gmii_rx_clk tx/rx_156_25_clk Adapters 125 MHz tx_serial_clk_10g tx_serial_clk_1g tx_clkout S Arria 10 PHY mgmt_clk xgmii_tx_clk xgmii_rx_clk rx_pma_clkout Transceiver Reset Controller MHz MHz MHz 625 MHz Legend MHz MHz 125 MHz 125 MHz Note: 1. n = (SHARED_REFCLK_EN == 1)? 1: NUM_CHANNELS 2. For Intel Arria 10 devices, the design example uses IOPLL. xgmii_clk[n] n Channel (1) PLL (2) pll_ref_clk_10g[n] MHz (NUM CHANNEL - 1) / ATX PLL pll_ref_clk_10g(0) fpll pll_ref_clk_1g[n] 125 MHz (NUM CHANNEL - 1) / pll_ref_clk_1g(0) rx_recovered_clk[n] dc_fifo_tx_clk MHz dc_fifo_rx_clk MHz 33

34 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices Reset Scheme The reset signals of the design example master_reset_n and channel_reset_n[n:0] are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components. Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example. Figure 21. Master Reset master_reset_n Ethernet Design Example with IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz PLL MHz Ethernet Channel n Master PPS Master TOD Transceiver Reset Controller ATX PLL fpll master_reset_n Ethernet Design Example without IEEE 1588v2 Feature channel_reset_n[n:0] mm_reset[n:0] datapath_reset[n:0] Ethernet Channel 0 PLL MHz Ethernet Channel n Transceiver Reset Controller ATX PLL fpll 34

35 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the transceiver reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together. The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv Figure 22. Channel Reset mm_reset Ethernet Design Example with IEEE 1588v2 Feature datapath_reset LL 10GbE MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller TOD 10G TOD SYN 96B_10G PPS 10G TOD SYN 64B_10G TOD 1G TOD SYN 96B_1G PPS 1G TOD SYN 64B_1G Address Decoder datapath_reset Ethernet Design Example without IEEE 1588v2 Feature mm_reset MAC Reset CSR pcs_mode_rc rx_block_lock led_link PHY Transceiver Reset Controller Address Decoder 3.4. Simulation The simulation test cases demonstrate how the channel speed and the configuration of the PHY are changed. These test cases use circular loopback on the total number of Ethernet channels. The following table describes the steps to change the speed and configuration. 35

36 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices Table 11. Ethernet Operations Operation Configuring the PHY speed. Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. Description Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), or 1G1000Base-X. Write one of the following values to the PHY's register at address offset 0x12C0. 0x01: Turn on the auto-detection mode. In this mode, the PHY automatically detects the speed. 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps. 0x41: Turn off the auto-detection mode and set the speed to 10 Gbps. Example To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11 To set port 0 to auto-detection mode: write_32 0x02_52C0 0x Test Case Design Example with the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the design example with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the design example asserts the channel_ready signal for each channel. 4. Sends the following packets: Non-PTP No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP 5. Repeats steps 2 to 4 for other operating speeds. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 36

37 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices Figure 23. Sample Simulation Output Test Case Design Example without the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for all channels. 3. Waits until the example design asserts the channel_ready signal for each channel. 4. Sends the following packets: Normal data frame, 64Bytes SVLAN data frame, broadcast, 64Bytes VLAN data frame, unicast, 500Bytes 5. Repeats steps 2 to 4 for other operating speeds. 37

38 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. Figure 24. Sample Simulation Output 3.5. Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control application, which is part of the development kit, set the following frequencies: Y MHz Y6 125 MHz Related Information Compiling and Testing the Design in Hardware on page 12 More information on the procedure and hardware setup. 38

39 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices Test Cases Clock Control More information on using the Clock Control application. You can run any of the following tests from the System Console. Table 12. Hardware Test Cases Test Case Command Example PHY internal serial loopback SMA loopback TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_size> For the design with the IEEE 1588v2 feature: TEST_SMA_LB <channel> <speed_test> <burst_size> For the design without the IEEE 1588v2 feature: TEST_SMA_LOOPBACK <channel> <speed_test> <burst_size> TEST_PHYSERIAL_LOOPBACK 0 10G 1000 TEST_SMA_LB 0 10G 1000 Table 13. Command Parameters Parameter Valid Values Description channel 0 to the number of channel specified for the design The number of channels for the test. speed_test 10G, 1G The PHY speed. burst_size The number of packets to generate for the test. When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output. Figure 25. Sample Test Output Packet Monitor 39

40 3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices Figure 26. Sample Test Output Statistics Counters Signal Tap Debug Signals The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below: set_global_assignment -name ENABLE_SIGNALTAP ON Table 14. Signal Tap Debug Signals Component Module Name Signal Top-level design example altera_eth_top mm_clk ref_clk_1g ref_clk_10g channel_ready_n channel_reset_n master_reset_n Multi-channel wrapper Design example without the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel Design example with the IEEE 1588v2 feature: altera_eth_top.altera_eth_mul ti_channel_1588 pll_locked pll_1_locked pll_2_locked (only for the design example with the IEEE 1588v2 feature) pll_locked_10g pll_locked_1g continued... 40