Ethernet - HDSL Gateway

Transcription

1 Ethernet - HDSL Gateway )(5',1$1'.29$A(9,@06F(( Institute of Security Belgrade, Kraljice Ane bb YUGOSLAVIA Abstract: - One pilot solution of Ethernet-HDSL gateway in the form of standalone processor controlled system is considered in this paper. Block diagram of hardware with 80C188 processor, MK5032 Ethernet Controller, MK68592 Ethernet Serial Interface, and with HDSL dedicated chipset Bt8953 Framer, Bt8952 Transceiver and Bt8921 Analog Front End is detailed presented. The software organization through LAN, HDSL and IPC task with their modules, all under the control of Real Time DOS Kernel is also pondered. The main characteristics of the solution and its benefits to the ISDN link transmission alternative are pointed out. Key words: - LAN, Ethernet, HDSL, ETSI ETR-152, Gateway, Intel 80C188 CSCC'99 Proc.pp Introduction The potential of the HDSL [1] technique, w the new techlogy, was the challenge to integrate its particular structure in area of data communication [2]. As the results of the investigation of problem inter working between LANs and the HDSL, we present in this paper our pilot solution of Ethernet - HDSL gateway. The gateway solution is in the form of standalone processor controlled system, that realizes in hardware and software the interface between the IEEE MAC and LLC layer of the Ethernet, and the two pairs ETSI ETR-152 standard [3]. Using only one pair, the gateway operates at 1168Kb/s, covering first two layers of equivalent OSI model. The IP and TCP/IP protocols are assumed at network and transport layer respectively as the standard protocols in data communications. The solution can be used as high-bit rate digital modem in Ethernet campus connections, and as fast Internet access system in Telcos carrier sensing area. Better quality data, voice, and video conferencing services in LAN and WAN connections are enabled by this gateway solution over one copper pair, and to the larger distance, in comparison with the ISDN alternative. 2. Hardware Structure In the design phase of the of the gateway development, some considerations were taken to define the system hardware and software organization. Because the system must be response oriented, the concept of the system with the dedicated hardware components controlled by the processor was selected, to avoid time consuming processes in software. So the decision was to construct pilot standalone system from the components currently on the market. The LSI chipset from Brooktree was selected to provide the interface to HDSL line, while the dedicated SGS- Thompson chips were selected for the Ethernet side interface. Former experiences with Intel 80C188 [4] processor, its software compatibility with PC development platform and the evaluation that it can fulfill demanded communication functions are the factors in selection 80C188 for controlling the programmable dedicated components, through the Mitel MT8020 [5] parallel access circuit. Having 2Mb/s synchrous serial bus, this circuit is selected to provide high-speed communication to the HDSL line components. The hardware schematic of the Ethernet-HDSL gateway is presented in figure 1. Interface to the Ethernet LAN perform the MK68592 Serial Interface Adapter and the MK5032 Variable Bit Rate Network Controller [6], that support IEEE Ethernet standard. The MK68592 circuit contains Manchester encoder and decoder, ise filter and collision detector, enabling MAC layer interface to Ethernet transceiver cable. The MK5032 Controller shares the common multiplexed bus and the memory with 80C188 processor. In master mode it performs DMA data transfer from its RX serial input to the RX buffers in CY7C1009 [7] RAM memory, and the data transfer from the TX buffers in RAM to its serial output, under the control of LAN task in CY7C286 [7] EPROM memory. When the MK5032 is in slave mode, the 80C188 processor has the access to its control and status registers for initialization and testing.

2 Fig. 1 Acquiring the bus control, the 80C188 processor can access the common part of RAM memory, take the data from the RX buffer and send it to D input of MT8020(2) circuit, that is used as parallel to serial converter, providing 2Mb/s PCM stream on its output ST0. The 8020(1) circuit performs serial to parallel conversion of 2Mb/s PCM stream on its input STi. The 80C188 processor reads its rx registers and transfers the data bytes to TX buffers in RAM, for sending to Ethernet network. As bus master, the 80C188 processor controls also the HDSL chips: Bt8953 Channel Unit (Framer) [8] and Bt8952 Transceiver [9]. The Bt8953 circuit performs mapping of incoming PCM string on its TSER input, then HDSL overhead bit allocation, scrambling and HDSL frame synchronization, giving 2B1Q code HDSL frame on its output TDAT. This frame is fed to Bt8952 HDSL transceiver chip, where it is filtered, pulse shaped and converted to analog form on its XMIT, XMITB outputs. Taking this outputs the Analog Front End (AFE) Bt8921 [10] performs filtering and differential line driver function to its TXLINE+, TXLINEoutputs. These outputs drive one twisted copper pair through the hybrid circuit HYB, that performs four wires to two wires conversion in the direction to the HDSL line. In the opposite direction the HYB performs two wires to four wires conversion driving the RXLINE+, RXLINE- inputs of AFE circuit. The AFE circuit performs in that direction the signal amplification, A/D conversion, and filtering, giving 13 bit word on its RXDATA2-RXDATA15 outputs. These outputs are fed to Bt8952 Transceiver circuit, that performs receiving signal echo cancellation, equalization, clock extraction and signal detection, providing HDSL frame data on its output RDAT. Taking this frame the Bt8953 Channel Unit circuit performs 2B1Q decoding, descrambling and HDSL frame to PCM frame mapping under the control of the 80C188 processor, giving 2Mb/s PCM stream on its RSER output, that is fed to MT8020(1) Parallel Access circuit. The GT block on figure 1 provides necessary clock signals: 60MHz for Bt8952, 4.096MHz and 2.048MHz for two MT8020 circuits and 20MHz for MK68592 Ethernet Serial Interface Adapter. Because the MK5032 Controller and the 80C188 processor share the common multiplexed address/data bus, simple logic is provided for bus arbitration, and tree-state latches 74LS373 are used for bus de multiplexing. 3. Gateway Software Considering the indispensability of the system operation in real time, with asynchrous functional events that need to be serviced, a multitasking software architecture is assumed, with Real Time DOS Kernel as operating system executing on Intel 80C188 processor. Extended multitasking functions of RT DOS Kernel enable task control, task synchronization, task communication and task scheduling what was necessary to support application software. The Data Flow Diagram(DFD) of the gateway software is presented in figure 2.

3 Fig. 2 LAN task performs receiving the data from Ethernet frames to RX buffers in RAM, and sending the data from TX buffers in RAM to Ethernet network, supporting the LAN controller circuit. Addresses of buffers, their status's and byte counts are organized in RX descriptor ring and TX descriptor ring, as data structure covered by MK5032 LAN controller's memory management mechanism.flow chart of LAN task program routine is presented in figure 3. Through the testing routine of LAN controller's status register, incidents at Ethernet network are detected, and proper responding routines are engaged, to support LAN controller in receiving or sending data, and in RAM memory data structure management ( RX and TX descriptor rings ). HDSL task supports HDSL dedicated components Bt8953 Framer and Bt8952 Transceiver, enabling the transfer the data from HDSL frame to the HDSL RX ring buffer in RAM memory, and the data from the HDSL TX ring buffer to the HDSL line. It provides start-up and control procedures compliant with ETSI ETR-152 [3] standard. Figure 4 is the flow chart of HDSL task's routines. Through testing IRQ register of the Bt8952 Transceiver the performance monitoring operations of the HDSL loop are executed, including routines of echo filter and equalizer filter coefficients adaptation in an LMS algorithm. If the receiver interrupt is detected the routines for extracting overhead bits from HDSL frame are engaged for control applications, and the data are stored to the HDSL RX ring buffer in RAM. In case of the transmitter interrupt, the data from HDSL TX ring buffer in RAM, and HDSL overhead control bits are fed to HDSL Framer circuit for sending to HDSL line. The IPC task performs communication between two mutual asynchrous tasks, LAN task responding on the events on Ethernet network side, and HDSL task servicing the incidents on the HDSL line, having the common parts of RAM memory with both tasks. The communication with these two tasks is on message level through the RT DOS Kernel. The IPC task routines are given in figure 5. Getting the signal message from HDSL task that the received message is completed in HDSL RX ring buffer, the IPC task moves it to free TX buffer in part of RAM memory shared with LAN task. In case of LAN task signal message, indicating the completing of received message from the Ethernet side in RX buffers in RAM, the IPC task moves the data from RX buffers to the TX ring buffers in part of RAM memory shared with HDSL task.

4 S S Read IRQ register of HDSL transceiver Test status register CSR0 of LAN Controller Init bit? Far end level m eter alarm? Initialization routine Start bit? yes Adaptation of AGC,LEC and NEC echo canceller filter coefficient in LM S algorithm Start LAN controller to send and receive packets Signal/Noise Ratio Alarm? Receiver interupt? Get last baffer address of LAN Receive Descriptor Ring Adaptation of DAGC,FFE and DFE Equilizer filter coefficient in LM S algorithm W rite the packet to LAN Rx buffer Read the Interupt Request Register of HDSL Framer Read Receive M essage Descriptor RM D1 Receive fram e interupt? Error bit? Rx error handling subroutine Read overhead bits EOC,IND,CRC and Z from Status Register of HDSL Framer Transm itter interupt? Write 32 bytes from serial to parallel circuit to HDSL Rx Ring buffer Get last buffer address of LAN Tx Descriptor Ring Transm it fram e interupt? Transm it the packet from LAN Tx baffer Write 32 bytes from HDSL Tx Ring buffer to parallel to serial circuit Read Transmit M essage Descriptor TM D1 Error bit? Write overhead bits SYNC,EOC,IND,CRC and Z to HDSL Framer Status Register Tx error handling subroutine Error bit? ex Error Service Routine ex Fig Conclusion The Ethernet - HDSL gateway is solved with dedicated hardware components controlled by the Intel 80C188 processor with Cypress CY7C Kx8 RAM, CY7C286 64Kx8 EPROM memory and with Mitel MT8020 parallel access circuit. Ethernet dedicated components built in, are SGS-Thompson MK5032 LAN controller and MK68592 Serial Interface Adapter, while the built Fig. 4 in HDSL line interface components are Brooktree Bt8953 Framer, Bt8952 Transceiver and Bt8921 Analog Front End (AFE), enabling the construction of the demanded fast responding system. The software is organized through LAN task supporting MK5032 controller, through HDSL task supporting Bt8953 Framer and Bt8952 Transceiver with implementation of ETSI ETR-152 start-up and control procedures, and through the IPC task. This task

5 6 Message from the LAN task? Read the current buffer address of LAN Rx Descriptor Ring Get the current buffer address of HDSL Tx Ring Buffer M ove the packet from LAN Rx buffer to HDSL Tx Ring Buffer Read the LAN Receive Message Descriptor RMD1 M ore buffers per packet? Point to the next LAN Rx baffer address Increment the pointer to the HDSL next Tx buffer M essage from the HDSL task? Read the current buffer address of HDSL Rx Ring Buffer Get the current buffer address of LAN Tx Descriptor Ring performs inter tasks communications through common buffers in RAM under control of built in real time DOS kernel RT DOS, that supported inevitable multitasking software functions. Covering first two layers of OSI equivalent model, with IP and TCP/IP protocols at next higher levels, the presented solution integrates the new HDSL transmission techlogy with standard data communication methods, giving the higher quality data communications over the wide spread copper pairs. Applying the presented gateway solution in LAN, WAN and Internet connections, high quality data, voice and video conferencing services are enabled. The benefits of this solution in comparison to ISDN alternative are: - the solution is cost-effective - only one copper pair is used - simpler applying the system on the existing copper cable - larger distance reach without the repeater and - fiber optic quality of signal transmission. Through proper design decisions the presented gateway solution is sized to meet full duplex 1168Kb/s data transfer through one pair HDSL line, with minimum hardware and system response time. M ove the packet from HDSL Rx baffer to LAN Tx buffer M ore buffers per packet? Point to the next LAN Tx buffer Point to the next HDSL Rx buffer Fig. 5 ex 5. References [1] Leichleider,J.W., High Bit Rate Digital Subscriber Lines, IEEE Journal of Selected Areas in Communications, Vol.9, No 6, Aug [2].RYDaHYL`)., One Solution of High Bit Rate PC Communication, Proceedings of the 6th Telecommunications Forum TELFOR "98.,Belgrade, YU, Nov [3] Europian Telecommunications Standard Institute, ETSI ETR-152 Technical Report, France, [4] Intel Corp., Intel 16/32bit Embeded Processors, USA,1990. [5] Mitel Corp, Microelectronics Data Book, USA, [6] SGS-Thompson Microelectronics, Datacom Products Databook, USA, dec [7] Cypress Semiconductor Corp., High Performance Databook, USA, [8] Brooktree Corporation, Bt HDSL Channel Unit, USA, [9] Brooktree Corporation, Bt HDSL Transceiver, USA, [10] Brooktree Corporation, Bt HDSL Analog Front End (AFE), USA, 1995.

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