EC 513 Computer Architecture

Transcription

1 EC 513 Computer Architecture Cache Coherence - Snoopy Cache Coherence rof. Michel A. Kinsy

2 Consistency in SMs CU-1 CU-2 A 100 Cache-1 A 100 Cache-2 CU- bus A 100

3 Consistency in SMs CU-1 CU-2 A 200 Cache-1 A 100 Cache-2 CU- bus A 100 Suppose CU-1 updates A to 200 Write-back: memory and cache-2 have stale values Write-through: cache-2 has a stale value

4 Consistency in SMs CU-1 CU-2 A 200 Cache-1 A 100 Cache-2 CU- bus A 100 Suppose CU-1 updates A to 200 Do these stale values matter? What is the view of shared memory for programming?

5 Write-through Caches & SC T1 is executed rog T1 ST X, 1 ST Y,11 Cache-1 writes back Y Cache-1 X= 1 Y=11 X= 1 Y=11 Y =10 Y =11 Cache-2 Y = X = Y = X = rog T2 LD Y, R1 ST Y, R1 LD X, R2 ST X,R2 T2 executed X= 1 Y=11 Y =11 Y = Cache-1 writes back X X= 1 Y=11 X = 1 Y =11 Y =

6 Write-through Caches & SC T1 is executed rog T1 ST X, 1 ST Y,11 Cache-1 X= 1 Y=11 Y =10 Cache-1 writes back Y Cache-2 Y = X = rog T2 LD Y, R1 ST Y, R1 LD X, R2 ST X,R2 T2 executed X= 1 Y=11 Y =11 Y = Cache-1 writes back X X= 1 Y=11 X = 1 Y =11 Y = Cache-2 writes back X & Y X= 1 Y=11 X = 1 Y = Y =

7 Write-through Caches & SC rog T1 ST X, 1 ST Y,11 Cache-1 X=0 Y=10 Y =10 Cache-2 Y = rog T2 LD Y, R1 ST Y, R1 LD X, R2 ST X,R2 T1 is executed X= 1 Y=11 X = 1 Y =11 Y = X =0 T2 executed X= 1 Y=11 X =1 Y = Write-through caches don t preserve sequential consistency either Y =

8 Maintaining Sequential Consistency Motivation: We can do without locks -- SC is sufficient for writing producer-consumer and mutual exclusion codes (e.g., Dekker) roblem: Multiple copies of a location in various caches can cause SC to break down. Hardware support is required such that Only one processor at a time has write permission for a location No processor can load a stale copy of the location after a write Cache coherence protocols

9 A System with Multiple Caches L2 L2 Interconnect Modern systems often have hierarchical caches Each cache has exactly one parent but can have zero or more children Only a parent and its children can communicate directly M

10 A System with Multiple Caches L2 L2 Interconnect M Inclusion property is maintained between a parent and its children, i.e., a in L i implies that a in L i+1

11 Cache Coherence rotocols for SC Write request: The address is invalidated in all other caches before the write is performed, or The address is updated in all other caches after the write is performed Read request: If a dirty copy is found in some cache, a write-back is performed before the memory is read We will focus on Invalidation protocols as opposed to Update protocols

12 Warmup: arallel I/O Address (A) Bus hysical roc. Data (D) Cache R/W age transfers occur while the rocessor is running A Either Cache or DMA can be the Bus Master and effect transfers D R/W DMA DISK DMA stands for Direct Access

13 roblems with arallel I/O Cached portions of page Bus hysical roc. Cache DMA transfers DMA DISK à Disk: hysical memory may be stale if cache copy is dirty Disk à : Cache may have data corresponding to the memory

14 Snoopy Cache Goodman 1983 Idea: have the cache watch (or snoop upon) DMA transfers, and then do the right thing Snoopy cache tags are dual-ported Used to drive Bus when Cache is Bus Master roc. A R/W D Tags and State Data (lines) A R/W Snoopy read port attached to Bus Cache

15 Snoopy Cache Actions Observed Bus Cycle Read Cycle, i.e., à Disk Write Cycle, i.e., Disk à Cache State Address not cached Cached, unmodified Cached, modified Address not cached Cached, unmodified Cache Action No action No action Cache intervenes No action Cache purges its copy Cached, modified???

16 Shared Multiprocessor rocessor Cores Local Memories Bus 1 Snoopy Cache hysical 2 Snoopy Cache 3 Snoopy Cache DMA DISKS Use snoopy mechanism to keep all processors view of memory coherent

17 Cache State Transition Diagram The MSI protocol state bits Each cache line has a tag Address tag Other processor reads 1 writes back M: Modified S: Shared I: Invalid M 1 reads or writes Write miss Read miss Read by any processor S Other processor intends to write I Cache state in processor 1

18 Cache State Transition Diagram The MSI protocol state bits Each cache line has a tag Address tag M: Modified S: Shared I: Invalid M 1 reads or writes Write miss Read miss Read by any processor S Other processor intends to write I Other processor intends to write 1 writes back Cache state in processor 1

19 Cache State Transition Diagram The MSI protocol state bits Each cache line has a tag Address tag Other processor reads 1 writes back M: Modified S: Shared I: Invalid M 1 reads or writes Write miss Read miss Read by any processor S Other processor intends to write I Other processor intends to write 1 writes back Cache state in processor 1

20 2 rocessor Example 1 reads 1 writes 2 reads 2 writes 1 Read miss 2 reads, 1 writes back S 2 intends to write M I 1 reads or writes Write miss 2 intends to write 1 writes back 1 reads 1 writes 2 writes 1 writes 2 Read miss 1 reads, 2 writes back S 1 intends to write M I 2 reads or writes Write miss 1 intends to write 2 writes back

21 2 rocessor Example 1 reads 1 writes 2 reads 2 writes 1 Read miss 2 reads, 1 writes back S 2 intends to write M I 1 reads or writes Write miss 2 intends to write 1 writes back 1 reads 1 writes 2 writes 1 writes 2 Read miss 1 reads, 2 writes back S 1 intends to write M I 2 reads or writes Write miss 1 intends to write 2 writes back

22 Observation Other processor reads 1 writes back M 1 reads or writes Write miss Read miss Read by any processor S Other processor intent to write If a line is in the M state then no other cache can have a copy of the line! stays coherent, multiple differing copies cannot exist I Other processor intent to write 1 writes back

23 Next Class Cache Coherence - Directory Cache Coherence