Wavelength routed shared buffer based feed-forward architectures for optical packet switching

Size: px

Start display at page:

Download "Wavelength routed shared buffer based feed-forward architectures for optical packet switching"

Holly Holland
5 years ago
Views:

1 Wavelength routed shared buffer based feed-forward architectures for optical packet switching R. K. Singh, Student Member, IEEE,R. Srivastava, V. Mangal and Y. N. Singh, Senior Member, IEEE Abstract--Several techniques for optical buffering have been given in past and still a lot of research is being done. Also, the rapid growth of the broadband communication has placed extreme demands upon the telecommunication infrastructure. This has generated an urgent requirement to introduce new technologies. Wavelength division multiplexing (WDM) is one of those techniques, which allows simultaneous propagation of large number of channels at higher data rates in a single fiber. In this paper, we are proposing three architectures for optical packet switching by utilizing wavelength routed shared buffer more efficiently. Buffering technique used in this paper is a new approach towards WDM application in optical domain. These three architectures are made by three different combinations of space switch and Arrayed Waveguide Grating (AWG). The results for the loss probability and average delay are obtained by simulation. Index Terms Arrayed Waveguide Grating (AWG), Loop buffer memory, optical buffering, shared buffer, WDM. T I. INTRODUCTION HE purpose of switching is to route the packet to the destined output port. The important aspects of photonic packet switching [1] are control, packet synchronization, clock recovery, packet routing, contention resolution and packet header replacement, which are used during the successful routing of a packet. Among all the aspects, contention resolution is the major issue for the all-optical networks. The only solution is to store the contending packets in the memory. Since there is no counterpart of electronic RAM in optical domain, several techniques for optical buffering, by using fiber delay lines, have evolved till now [2], [3] and still research is going on to explore better solutions. Optical buffering can be introduced in three ways: input buffering, output buffering and shared buffering [2], [4]. Shared buffer optical switch is more advantageous as compared to the other two, because it also provides switching alongwith buffering. These shared type buffers can be implemented in the optical switches either in the feed-back or in the feed-forward manner [5]-[9]. Both of these configurations have their advantages and disadvantages and are used as per the requirement of the switch architecture. Till now, major focus is on the application of R. K. Singh, R. Srivastava, V. Mangal and Y. N. Singh are with Indian Institute of Technology Kanpur, INDIA ( rajatks@iitk.ac.in, rajivs@iitk.ac.in, ynsingh@iitk.ac.in.) shared buffer by using traveling type fiber delay lines while little attention was given towards utilizing the recirculating type buffer delay lines. In this paper, we are proposing three architectures for optical packet switching by using feed-forward shared buffer. These buffers are constructed using recirculating type loop buffer utilizing WDM technique for storing the packets [10]. The recirculating loop buffers are usually designed for equal length packets. Hence this study pertains to equal length packets. Detailed description about the architecture is given in section II. Comparison of the three architectures is given in section III. Scheduling algorithms for the operation of the switch architectures are explained in section IV. Results are discussed in section V and finally, section VI concludes the paper. II. DESCRIPTION OF THE ARCHITECTURES The advantages of using recirculating type delay lines over traveling type, for same capacity are given in Table I. TABLE I DIFFERENCE BETWEEN DELAY LINE TYPES Traveling type loop buffer Recirculating type loop buffer 1 Provides fixed delay Any number of times same packet can be stored 2 More number of fibers are required for larger time of Only single loop is required to provide any amount of delay storage 3 Can store only one packet at a time More than one packet can be stored using WDM application 4 Tunability is not possible Possible here In this paper, the notation used for all the three architectures are A1, A2 and A3 respectively. Each architecture and its corresponding buffer module are shown in Fig. 1 to Fig. 5. The basic building block of all the architectures has similar structure. These architectures consist of three sections: 1. Scheduling section. 2. Combined section for routing the packet through either M direct path or m buffer modules. 3. Switching section. Scheduling and switching section, of all the architectures, is constructed either by using space switch or by AWG. In the architecture A1, space switch is used for scheduling and

2 switching section and the size of these sections will be N K and K N respectively. In case of A2, size of scheduling stage is same as A1 i.e. of N K while switching is done by AWG of size N N. Finally, in the architecture A3, scheduling & switching stage are made by AWG of size N K and N N respectively. Here, K is defined as, K = M + m D where, M is the number of direct path with no delay, m is the number of loop buffer modules used in the feed-forward manner and D is the number of input/output ports assigned to each buffer module. The capacity of each buffer module is considered equal to B ( D), i.e. it can store up to B number of packets at B different wavelengths. These wavelengths (B) will be different from the incoming wavelengths (N). Also, the same range of B wavelengths can be reused in all the buffer modules since the signals on same wavelengths in different buffer modules are independent and they do not interfere. Scheduling strategy will remain same for all the architectures while there will be slight change in the buffering and routing techniques. Each buffer module consists of D tunable wavelength converters (TWC) at its input, a recirculating loop buffer and either one wavelength demultiplexer (DEMUX in case of A1, Fig. 4) or a Band Pass Filter (BPF in case of A2 and A3, Fig. 5) at the output of the buffer module. Each of these BPF allows any of the wavelengths reserved for tuning out the stored packet. Packets from all these D inputs use WDM to share the recirculating loop buffer. The number of buffer wavelengths (B) inside the loop depends on the switch design, desired traffic throughput, packet loss probability and size of the switch [10]. The allocation of the packets to the loop buffer depends on the routing and priority algorithm for the switch. The path, followed by a packet, in recirculating loop, (Fig. 6) consists of 3dB coupler, DEMUX, TWC, combiner, erbium-doped fiber amplifier (EDFA), isolator, BPF and again the same 3dB coupler during one circulation. Here, number of TWC and the size of DEMUX and combiner inside the loop depend upon the required buffer capacity (B), and hence, these are considered equal to B. The EDFA is placed inside the loop to compensate the power loss in the loop buffer during circulation, and BPF is used to band-limit the noise. Fig. 2. Switch Architecture II (A2). Fig. 3. Switch Architecture III (A3). Fig. 4. Buffer module for A1. Fig. 5. Buffer module for A2 and A3. Fig. 6. Architecture of recirculating loop. Fig. 1. Switch Architecture I (A1). The buffer module in case of A1 (Fig. 4) consists of a DEMUX at the output of recirculating loop. The wavelength range of this DEMUX is chosen different from the buffer wavelength (B) to prevent direct transfer of packets through the buffer module without entering the recirculating loop.

3 III. COMPARISON AMONG THREE ARCHITECTURES A. Link Loss Analysis The maximum physical loss attained by any packet, while passing through different architectures, is defined as: L = L L L L L L L A1 SS TWC Com LB 3dB DEMUX SS L = L L L L L L L A2 SS TWC Com LB 3dB BPF AWG L = L L L L L L L L A3 TWC AWG TWC Com LB 3dB BPF AWG where L LB, loss through the recirculating loop, is defined as follows, LLB L3dB = L L L L L. DEMUX TWC Com ISO BPF The typical values of various loss variables, defined above, are given in Table II. TABLE II VALUE OF DIFFERENT PARAMETERS Symbol Quantity Value L SS Space switch loss 0.5Log 2N db L AWG Arrayed waveguide loss 2 db L TWC Loss of Tunable Wavelength Converter 2 db L Com Combiner loss at the input of loop 10Log 10D db L Com Combiner loss inside loop 10Log 10B db L 3dB Loss of 3dB coupler 3.4 db L DEMUX Loss of DEMUX 1.5(Log 2D-1) db L ISO Isolator Loss 0.15 db L BPF Loss of Band Pass Filter 1.0 db B. Control Complexity The performance of all the architectures, in terms of packet loss probability and average delay, will be same because same scheduling algorithm is used for each case. But their application requires a specific set of components for proper use of that particular architecture, because every component exhibits some advantages and disadvantages. The major distinctions among them are: A1 consists of space switch fabric at both stages i.e. at scheduling as well as at switching stage. Hence their control complexity is high. Whereas A2 uses AWG at switching stage and A3 uses AWG at both ends in place of space switch fabrics. There is no controlling in AWG due to its wavelength specific self routing nature. But this advantage will be countered by the presence of TWC at each input port of AWG and the controlling is transferred from switch to TWC. IV. SCHEDULING ALGORITHM The buffering module used in these proposed architectures is of feed-forward type and recirculating in nature. The incoming packets, after passing through the scheduling section for once only, follow the scheduling algorithm and choose the appropriate path either the direct one or through the buffer modules. If any packet is directed towards buffer due to contention, then it will remain in recirculating loop till the contentions get resolved. We had simulated all the architectures to estimate the performance in terms of packet loss probability and average delay. The arriving traffic is chosen random in nature and scanning of input is done sequentially during simulation. The arriving packet may contend for any output in two ways, i) contention among themselves or ii) contention with already stored packets in the buffer. During contention of any type, priority will be given to the already stored packets in the buffer modules and then, if possible, rest of the contending packets will be buffered. Routing is done in such a way so that no packet gets indefinite delay. Direct path will only be used when there is no packet, destined for same output port, is stored in any of the buffer module. The buffer module for A1 uses (B + D) wavelengths and that for A2 and A3 uses (B + N) wavelengths. Here, B is the number of buffer wavelengths used to store a packet in the buffer, and D or N is the number of wavelengths used for reading out the packets from the loop buffer. The packets to be buffered are converted to the wavelengths available in the buffer; if buffer is full then packets are dropped. When a packet is forwarded for buffering, the respective TWC at the input of the available buffer module is tuned to any one of the free wavelengths of loop buffer. The packets buffered in different modules will circulate in the loop as long as the respective destined output port is busy. Also, the TWC inside that recirculating loop, corresponding to the wavelength assigned to the packets will remain transparent till it is desired to read out the packet or to have dynamic wavelength re-allocation. For reading out a packet when output contention is resolved, corresponding TWC inside that loop is tuned to the appropriate wavelength and the packet is directed towards switching section through DEMUX/BPF (depending upon the architecture). In case of A1, the TWC inside the loop is tuned to the free wavelength at DEMUX output port, while in case of A2 and A3, since the switching section is made of AWG, so the TWCs are tuned accordingly. As explained already in the literature that an AWG of size P P on Q wavelength has a fixed routing pattern. This routing is defined in such away that, if the inputs of AWG are numbered from 1 to P, and its wavelengths range from 1 to Q, then an input signal on wavelength i at input fiber j will be get routed at the same wavelength on the output fiber numbered as k, where k = (( i j) mod P) + 1. Thus, according to the routing logic of AWG, the TWC inside that loop is tuned to the wavelength appropriate for that packet to reach the destined output port in case of A2 and A3. Finally, these scheduled packets, on reaching at the switching section, can be switched to the destined output port through the space switch fabric or AWG. Due to the above routing pattern at AWG, TWC is also placed in the direct path for the A2 as well as in direct path and at the input of scheduling section in case of A3. After applying the algorithm, all those arriving packets are dropped which cannot be passed directly as well as cannot be stored in the buffer modules. The ratio of dropped packets to total transmitted packets will give the packet loss probability estimate. Average delay performance for the packet, while passing through the buffer module, has also been obtained.

4 V. RESULTS AND DISCUSSION Simulations are done for various combinations of the values of B, M and m for a particular value of N = 16 at different loading conditions and results are plotted in Fig. 7. Here, we observe that three combinations perform better and give comparable and efficient result. We have analyzed the results to get optimize value. For convenience, we had given the name C1, C2 and C3 to these three combinations. These are defined, in terms of values of different parameters as follows: C1: B = D, M = N / 2, m = 3 N / 2D C2: B = 2 D, M = N /4, m = N / D C3: B = 3 D, M = N /4, m = 3 N /4D These combinations are used here for D = 4, N = 16. DEMUX and this indicates that C2 will be the better choice in terms of DEMUX usage. Another important parameter is gain of the EDFA placed inside the recirculating loop. Since in case of C3, maximum numbers of wavelength channels are used for buffering, thus the EDFA used in case of C3 will be of highest gain to compensate the higher loss of 1 12 DEMUX used there. These EDFAs will also produce maximum amplified spontaneous emission (ASE) noise which is a degrading factor and should be as low as possible, because ASE noise increases alongwith gain of EDFA. Due to this reason, gain of EDFA used in C1 will be lowest (Table III). Here, again C2 will be better choice in term of using EDFA because its gain lies between the gains of EDFA used for C1 and C3. Sizes of scheduling and switching stages used in the architecture are nearly equal, so they will not be as much effective in selecting the optimal choice. Hence, the optimal choice among the three combinations of parametric values is C2, i.e. B = 2D, M = N/4, m = N/D with D = 4 and N = 16. Fig. 7. Loss probability for N = 16 with various combination of B, M and m. A. Optimal combination selection by simulation Fig. 8 and Fig. 9 deal with the loss probability and average delay respectively, for the switch of size N = 16 and combinations C1, C2 and C3. We observe that under lower loading condition delay performance is same for all while at higher loads, loss probability remains same and worst for all combinations. We are getting lowest loss probability for C2 as compared to C1 and C3 whereas least average delay is obtained for C1. But, this advantage in delay for C1 will be overcome by better loss probability for C2. This can be proved by comparing the results at ρ = 0.7, where loss probability for C2 is 3 times better than C2 while average delay increment for C2 is only 0.3 slots. B. Optimal combination selection in terms of component complexity The major components and their quantity used in the A1, for the above three combinations, are compared in Table III. The number of TWCs (= D m + B m) remains same in all cases while that of DEMUX is highest for C1 and lowest for C3. On the other hand, size of DEMUX used inside the recirculating loop will be smallest for C1 (i.e. 1 4) while largest for C3 (i.e. 1 12) and so is the insertion loss for each case. Hence, there will be a trade-off between number and size of Fig. 8. Comparison of Loss Probability for C1, C2, C3 at D = 4 and N = 16. Fig. 9. Comparison of Average Delay for C1, C2, C3 at D = 4 and N = 16.

5 TABLE III COMPLEXITY ANALYSIS OF MAJOR COMPONENT USED IN ARCHITECTURE I (A1) FOR THREE EFFICIENT COMBINATIONS AT D = 4 AND N = 16 COMBINATION SIZE OF SCHEDULING SECTION SIZE OF SWITCHING SECTION TOTAL NUMBER OF TWC TOTAL NUMBER OF DEMUX (INSIDE + OUTSIDE) OF LOOP GAIN OF EDFA C = 12 LOWEST C = 8 MEDIUM C = 6 HIGHEST The effect of increasing switch size alongwith the other parameters is also examined. The simulation results for packet loss probability and average delay for this optimal combinations (C2), applied on all the architectures, are shown in Fig. 10 to Fig. 12. Here, Fig. 10 explains the variation of loss probability with increasing load at various sizes of switch while Fig. 11 explains the same with increasing switch size under various loading condition. The results show that loss probability increases with higher loading condition for a particular switch size, but if we compare it with increasing switch size at a given load, loss probability decreases for larger switches. The result for average delay is shown in Fig. 12. The delay is more at higher load and it was obvious but there is no major effect of increasing the switch size. The path loss for any packet, passing through the whole switch alongwith the loop buffer module, is calculated for all the three architectures under the optimized combination C2. These values are obtained by using the parametric values given in Table II. LA1 = db LA2 = db L = db A3 In the above calculation, we have considered only single revolution of any packet in the recirculating loop, i.e. if any packet performs more number of circulations then its loss will be more. These results indicate that physical loss remains same for any packet passing through any of the three architectures. Thus, selection of the architecture depends upon the controlling ability of the system as well as on the system requirements. Fig. 10. Loss probability for various switch size using C2 at D = 4. Fig. 12. Average Delay for various switch size using C2 at D = 4. VI. CONCLUSION In this paper, we have presented three architectures with different scheduling and switching section. We had compared the three architectures in term of physical parameter such as link loss and gain of the EDFA. We had also optimized the buffer parameters for better loss probability and average delay. Also, the final three combinations of parameters are comparable among each other and can be used accordingly, but C2 will be the optimal choice. Fig. 11. Loss probability under various load on system using C2 at D = 4.

VII. REFERENCES [1] R. S. Tucker and W. D. Zhong, Photonic packet switching: an overview, IEICE Trans. Commun., vol. E82 B, pp. 254-264, Feb. 1999. [2] D. K. Hunter, M. C. Chia and I.

Fumagalli, An optical switch architecture for manhattan network, IEEE J. Select. Areas Commun., vol. 6, pp. 550-559, May 1993. [4] M. G. Hluchyj and M. J. Karol, Queueing in high-performance packet switching, IEEE J.

Tetali, A Markov chain model for an optical shared memory packet switch, IEEE Trans. Commun., vol. 47, pp. 1593-1603, Oct. 1999. [6] M. C. Chia, D. K. Hunter, I. Andonovic, P. Ball, I. Wright, S. P. Ferguson, K.

, vol. 19, pp. 1241-1254, Sep. 2001. [7] W. D. Zhong and R. S. Tucker, A new wavelength-routed photonic packet buffer combining travelling delay lines with delay-line loops, IEEE J. Lightwave Technol.

6 VII. REFERENCES [1] R. S. Tucker and W. D. Zhong, Photonic packet switching: an overview, IEICE Trans. Commun., vol. E82 B, pp , Feb [2] D. K. Hunter, M. C. Chia and I. Andonovic, Buffering in optical packet switches, IEEE J. Lightwave Technol., vol. 16, pp , Dec [3] I. Chlamtac and A. Fumagalli, An optical switch architecture for manhattan network, IEEE J. Select. Areas Commun., vol. 6, pp , May [4] M. G. Hluchyj and M. J. Karol, Queueing in high-performance packet switching, IEEE J. Select. Areas Commun., vol. 6, pp , Dec [5] P. D. Bergstrom, Jr., M. A. Ingram, A. J. Vernon, J. L. A. Hughes and P. Tetali, A Markov chain model for an optical shared memory packet switch, IEEE Trans. Commun., vol. 47, pp , Oct [6] M. C. Chia, D. K. Hunter, I. Andonovic, P. Ball, I. Wright, S. P. Ferguson, K. M. guild and M. J. O Mahony, Packet loss and delay performance of feedback and feed-forward arrayed-waveguide gratings-based optical packet switches with WDM inputs-outputs, IEEE J. Lightwave Technol., vol. 19, pp , Sep [7] W. D. Zhong and R. S. Tucker, A new wavelength-routed photonic packet buffer combining travelling delay lines with delay-line loops, IEEE J. Lightwave Technol., vol. 19, pp , Aug [8] L. Li, S. D. Scott and J. S. Deogun, A novel fiber delay line buffering architecture for optical packet switching, in Proc IEEE Globecom Conf., pp [9] J. F. Huang, C. C. Yang and C. H. Chou, Evaluations on a buffering WDM optical packet switch equipped with shared wavelength converters, J. Opt. Commun., vol. 25, pp , Jan [10] S. Shukla, R. Srivastava and Y. N. Singh, Modelling of fiber loop buffer based switch, in Proc Photonics Conf., p-248. Yatindra Nath Singh (M 98) was born in Delhi in India, on Aug 26, He obtained B.Tech. in Electrical Engineering with honors from Regional Engineering College, Hamirpur, Himachal Pradesh in July 1991, M.Tech. in Optoelectronics & Optical Communications from Indian Institute of Technology, Delhi in December 1992 and Ph.D. from Department of Electrical Engineering, Indian Institute of Technology, Delhi in He was with the Department of Electronics and Computer Engineering, IIT Roorkee, India as faculty from Feb'97 to July'97. He is currently working as faculty in the department of electrical engineering, Indian Institute of Technology, Kanpur. He has been given AICTE young teacher award in He is a fellow of Institution of Electronics and Telecommunication Engineers (IETE), India and senior member of The Institution of Electrical and Electronics Engineers, Inc., (IEEE) USA. His academic interests include Optical Networks, Photonic packet Switching, Optical Communications, telecom networks, Network managements, E-learning systems, Open-source software development. He is actively involved in development of Open Source E-learning platform tools codenamed Brihaspati. VIII. BIOGRAPHIES Rajat Kumar Singh (M 2005) was born in Jaunpur, (UP) in India, on Dec 18, He received B.Tech. degree in Electronics & Instrumentation Engineering from Bundelkhand Institute of Engineering & Technology, Jhansi (UP) in 1999 and M.E. degree in Communication Engineering from Birla Institute of Technology & Science, Pilani (Raj.) in Dec Currently, he is pursuing his PhD from Indian Institute of Technology, Kanpur. His research interests are in the field of photonic packet switching, telecom networking and optical networks. Rajiv Srivastava was born in Kanpur, (UP) in India, on Feb 18, He received M.Sc. degree in Physics (Solid State) from CSJM University, Kanpur (UP) in 1997 and M.Tech. degree in Laser Technology from Indian Institute of Technology, Kanpur in Dec Currently, he is pursuing his PhD from Indian Institute of Technology, Kanpur. His research interests are in the field of photonic packet switching and Solitons based optical networks. Vipin Mangal was born in Gwalior (MP) in India, on Oct 8, He received B.E. degree in Electronics & Telecommunication Engineering from Institute of Technology & Management, Gwalior (MP) in 2002 and M.Tech. degree in Information System from Indian Institute of Technology, Kanpur in May His research interests are in the field of photonic packet switching, optical networks and signal processing.

Exact and Approximate Analytical Modeling of an FLBM-Based All-Optical Packet Switch

JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 21, NO. 3, MARCH 2003 719 Exact and Approximate Analytical Modeling of an FLBM-Based All-Optical Packet Switch Yatindra Nath Singh, Member, IEEE, Amit Kushwaha, and