PHOTONIC ATM FRONT-END PROCESSOR

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Justina Eugenia Hudson
5 years ago
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1 PHOTONIC ATM FRONT-END PROCESSOR OBJECTIVES: To build a photonic ATM front-end processor including the functions of virtual channel identifier (VCI) over-write and cell synchronization for future photonic ATM. APPROACHES: STARTING DATE: July 1, DURATION: 3 years. Taking the advantages of both electronics and photonics (intelligence and bandwidth), signals will be kept in the optical domain through the processor. The header information will be tapered down to the electronic domain for processing and control. MILESTONES: 1. Electronic Control Unit: including cell delineation, synchronization, and interface, VCI table read/write, and control unit. (end of the 2nd year) 2. Y-junction SOA gate switches and 3-stage cell synchronizers. (3rd year) 3. VCI over-write Unit: with LiNbO 3 switches and with SOA gate switches. (end of the 3rd year)

2 PHOTONIC ATM FRONT-END PROCESSOR TECHNICAL ACCOMPLISHMENTS LAST YEAR 1. Complete the fabrication of the BH/BR Y-junction semiconductor optical amplifier (SOA) gate switch. The device is designed for easier fiber coupling and packaging. Subnanosecond switching time is achieved. Switching of multiwavelength signals is demonstrated. 2. Demonstrated 2.5 Gb/s VCI over-writing operations using LiNbO3 switches. There is no bit lost during the switching even without guard time between cells. 3. Start to build cell synchronizer using SOA gates. Optical delays of 0, 1/8, 1/4, and 1/2 cell lengths were demonstrated. 4. Complete the design and printed circuit boards (PCBs) implementation for cell delineation and VCI overwrite. The PCBs of cell delineation and VCI overwrite work at near 2.5 Gbit/s. The intergration of optical and electronic subsystems for VCI overwrite is currently working at 1.68 Gbit/s and is being tunedto2.5gbit/s.

3 PHOTONIC ATM FRONT-END PROCESSOR KEY MILESTONE NEXT YEAR 1. Improve the gain of the SOA gate switch to achieve fiber to fiber insertion gain (-5 db for current devices). 2. Demonstrate the VCI over-write function with Y-junction SOA gate switches. 3. Complete the design and PCB implementation of cell synchronizer control electronics, which include electrical-controlled optical delay lines. 4. Demonstrate the complete system of header extraction, cell delineation, circuit board controlled VCI overwrite, and cell synchronization at 2.5 Gb/s.

4 PHOTONIC ATM FRONT-END PROCESSOR TECHNOLOGY TRANSITION/INSERTION AND COMMERCIALIZATION PLAN 1. Continuously cooperate with Lucent Technology to fabricate all the optoelectronic devices. 2. The SOA gate switches can switch a full 64-wavelength (bit) parallel words with one photonic switch and in one single switch operation. When the microprocessor speed entering into the ~GHz (Intel Merced chip set) range with 64-bit data bus, this technology may have significant impact to implement the next generation gigabit interconnect. 3. The circuit design of cell delineation at 2.5 Gb/s can be transferred to chip vendors.

5 FABRICATION & DEMONSTRATION OF A WDM, ATM, MULTICAST SWITCH OBJECTIVES: To build electronic control circuits and photonic devices required to implement an optically transparent WDM, ATM, multicast switches. APPROACHES: STARTING DATE: May 15, DURATION: 3 years. The first 3 years will be focused on the design of an optical ATM switch structure and the fabrication of all the required basic electronic control circuits and optoelectronic devices. The extended 2 years will be used for the whole switch system implementation. MILESTONES: Totally 4 tasks need to be finished near or at the end of the 3rd year: 1. all optical wavelength converters. 2. fast tunable actives filters. 3. WDM optical memories. 4. electronic central processor and interface circuits.

6 FABRICATION & DEMONSTRATION OF A WDM, ATM, MULTICAST SWITCH TECHNICAL ACCOMPLISHMENTS LAST YEAR 1. Complete the device and system testing of tunable active filters. Experiments of using the tunable DBR active filter as a WDM demultiplexer, channel power monitor, channel power controller, and equalizer in an 8-channel WDM system were demonstrated. 2. Utilizing the recently discovered ôgain Decompression effectöto build very fast wavelength converters. Conversion at 5 Gb/s (speed limit of our BER tester) is demonstrated. We are working on obtaining 100 Gb/s TDM demultiplexing using these devices. 3. Build an 8-wavelength WDM buffer memory and experimentally demonstrate the memory operation over 25 circulation at 1 Gb/s (limited by digitizer display word length) with very little noise accumulation. 4. Complete a 4x4 optical ATM switch design with shared-memory structure. 5. Extend the integrated coherent receiver works to transceiver, full duplex, counter-mixing, and a new secure and BW-on-demand networking operations.

7 FABRICATION & DEMONSTRATION OF A WDM, ATM, MULTICAST SWITCH KEY MILESTONES NEXT YEAR 1. Demonstrate high speed operation of dynamic wavelength-channel selection using active filter banks. 2. Finalize the wavelength converter structure. Demonstrate very high speed wavelength conversion and possibly all optical logic operations. 3. Complete the design and implementation of channel selection and memory control circuits. 4. Complete the circuit implementation of the control logic that deals with cell routing, contention resolution, and multicasting.

8 FABRICATION & DEMONSTRATION OF A WDM, ATM, MULTICAST SWITCH TECHNOLOGY TRANSITION/INSERTION AND COMMERCIALIZATION PLAN 1. Continuously cooperate with Lucent Technology to fabricate all the optoelectronic devices. 2. Concept of using the low cost integrated coherent transceivers for a secure and bandwidth-on-demand full service broadband network have been proposed. We will continuously push it for commercialization. 3. Based on the structure of all active wavelength converters, we have developed integrated device structure of TDM demultiplexer, all optical modulator, and all optical XOR gate for ~100 Gb/s optical networks. NRL researchers are interested in the work and working together with us.

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