Using the Current Control for Dynamic Voltage Scaling to Reduce the Power Consumption of PC Systems

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1 Using the Current Control for Dynamic Voltage Scaling to Reduce the Power Consumption of PC Systems Ying-Wen Bai and Feng-Hua Chang Abstract In this paper we use the load current of the CPU as decision of the working state of the PC is either a heavy load or a light load. Based on the voltage specification of each device on the PC motherboard, we use the current control for dynamic voltage scaling (IREF-DVS) regulator to provide different voltages for each device. When the PC has a light load we can decrease the operating voltage of each device to the minimum voltage, and with a heavy load this design can increase it to the maximum voltage to improve the performance. T I. INTRODUCTION here are a lot of devices on the PC motherboard, and they all need power to work properly. The CPU is the most power-hungry component. With an Intel i7-870 CPU the maximum current of the core voltage is 110A, and the maximum power consumption is 95W. So there are many studies currently being made to find a way reduce the PC power consumption. These studies focus on reducing the core voltage to reduce power consumption of the CPU. In the ACPI specifications the CPU power-saving technology is called C-State [1]. The C-State is defined as the S0 state, the CPU idle state, and thus it is defined as one of the PC working states. Table I shows all definitions of the C-State. When the CPU enters into the C-State, the C1-State and the C3-State both stop the internal CPU clock. The difference is that the CPU can also control the internal cache memory in the C1-State but not in the C3-State because the internal PLL circuits and the cache memory are all shut down in the C3-State. When these units are stopped, it means that the CPU is in the sleep mode. But merely only cutting off the internal clock signals is not enough to further reduce CPU power consumption. Therefore the next step is to reduce the processor voltage. We know that power consumption is proportional to voltage. If we can reduce the CPU operating voltage, this will reduce the CPU power consumption. The C6-State is a deep sleep mode which reduces the CPU operating voltage for lower power consumption. When the CPU goes into the C6-State, this state allows the reduction of power consumption by reducing the CPU core voltage, even to as low as 0V. At this time, the CPU is in a complete sleep state because the CPU has a special internal static memory cell. The CPU writes all information into the static memory cell when it enters into the C6-State. The CPU resumes all the information from the static memory cell when Ying-Wen Bai is with the Department of Electrical Engineering, Fu Jen Catholic University, Taipei, Taiwan. ( bai@ee.fju.edu.tw). Feng-Hua Chang is currently working toward the M.S. degree in Electrical Engineering at Fu Jen Catholic University, Taipei, Taiwan. ( @mail.fju.edu.tw). it exits from the C6-State, thus ensuring that the previous work is not lost. TABLE I CPU C-STATES Mode Status Description a Normal Operating State The normal operating state of a core where code is being executed. C1 Halt State No instructions are being executed. The CPU controller turns off the clocks. C3 Sleep The core PLLs are turned off and all the core caches are flushed. A core in C3 is considered an inactive core. The wakeup time for idle state C3 is significantly longer than in state C1. C6 Deep Power Down The core PLLs are turned off, the core caches are flushed and the core state is saved to the Last Level Cache (LLC). The power gate transistors activated to reduce power consumption to a particular core to approximately zero Watts. Below is the comparison of the power consumption in different CPU C-States: P > PC1 > PC3 > PC6 (1) Below is the comparison of the resumption time from each C-State to the -State: T C6 > > TC3 > > TC1 > (2) Fig. 1 is the transition of the CPU C-States. The CPU can go into any C-State for the best performance and power saving. The C6-State can only adjust the core voltage of the CPU but not the operating voltage of the other devices in the PC system. Dynamic Voltage and Frequency Scaling (DVFS) are currently most commonly used to enhance the CPU performance, and the power saving technologies C-State and Intel Turbo Boost [2] both use DVFS. DVFS dynamically adjusts both the CPU clock frequency and the operating voltage. The frequency and voltage can be adjusted upward to enhance performance and adjusted downward to save power. The Turbo Boost function adjusts the voltage upward with the CPU frequency to improve performance. The C-State reduces the CPU operating frequency and voltage to reduce power. There are many technologies related to Dynamic Voltage Scaling (DVS), such as Process-Driven DVS [3], Application-Driven DVS [4], Temperature-Aware DVS [5][6] and Energy-Aware DVS [7]. These methods determine the voltage operating point, which usually depends on the CPU operating frequency or the operating temperature /11/$ IEEE SI International 2011

2 Battery-Aware DVS [8][9] is used in portable products for longer use. Fig. 1. State transition of CPU C-States in ACPI S0. Every PC motherboard device needs a power supply to provide power to work correctly, and each device has its own specifications for voltage. For example, the standard DDRIII-VDD voltage is 1.5V, but there is an acceptable voltage margin. In the DDRIII specifications the operational voltage range of DDRIII-VDD is defined at 1.425V V. In other words, DDRIII devices can work well as long as the voltage source is maintained at 1.425V or above. Before designing the voltage regulation system we must first understand each voltage range of the device to make sure it can work well. Table II is the power deliver list of the motherboard [10]. It defines the working current and operating voltage range of all on-board devices. If the motherboard can lower the voltage in a high-consumption device, it saves more power. Equation (3) is a known formula for power consumption. Power consumption is proportional to voltage and operating current. Assuming the current is a constant, decreasing the voltage is the easiest method for power saving. P = I V (3) In PC motherboard design specifications the operating voltage of all devices has a design margin. We can adjust the voltage down to the minimum of the margin to save power, and the operating voltage lets the PC work well even in the worst possible scenario. For example, the standard working voltage of CPU-VTT is 1.1V, assuming the operating current is 30A. If the PC motherboard lowers the voltage to 1.045V, it saves power as below. P = P P (4) SAVE V_type V_min PSAVE = P1.1V P1.045 P = [1.1V 30A] [1.045V 30A] = 1.65W If P SAVE is used in portable products, a device saving 1.65W means that its use can be extended by up to 5% with the same battery capacity. Device TABLE II PLATFORM POWER DELIVERY Load Current(max) Typical Voltage Operational Range CPU A CPU control 0.65V - 1.3V VCC_CORE CPU -- 25A CPU control 0.65V - 1.3V VCC_AXG CPU -- VTT 30A 1.1V 1.045V V VCCPLL 16A 1.8V 1.854V V PCH -- VCC 6.5A 1.05V V V PCH A 1.05V V V VCCME DDR A 1.5V 1.425V V VDD/VDDQ DDR mA 0.75V V V VTT Realtek 40mA 3.3V 3.135V V ALC888S -- DVDD Realtek 51mA 5V 4.75V V ALC888S -- AVDD PCI Express 3A 3.3V 3.003V V x V PCI Express 5.5A 12V 10.92V V x V PCI Express 3A 3.3V 3.003V V x V PCI Express 0.5A 12V 10.92V V x V USB A/port 5V 4.75V V USB A/port 5V 4.75V V As a PC is usually seldom under heavy loading operating conditions, even the operating time of light loading will be much larger than the operating time of heavy loading. In [11][12] it is pointed out that both workload and load current have a very strong correlation. When the PC runs high-performance requirement software, for example, a 3D game, the CPU has to carry out a high speed floating operation which requires a relatively large source current. When the PC is running under low performance conditions, for example, MSN or idling, the CPU is in the idle state. The current requirement of the CPU is now relatively low, and we can therefore use the Accurate Current Monitor (IMON) function of the DC-DC buck converter [13]. It is easy to get the CPU operating current and then estimate the current system running state. IMON is an analog signal proportional to the load current of the CPU V CORE ; it is a voltage output representation (V IMON ). When the load current of the V CORE changes, then the V IMON changes. The V IMON is relatively lower when the load current of the V CORE decreases relatively higher when the load current of V CORE increases. The V IMON change curve is close to linear; it shows a voltage between 0V-1.1V. Fig. 2 shows that load current and V IMON both are proportional to changes in real-time and are synchronized SI International 2011

3 IREF-Generator in the IREF-DVS, so we can sink or source the I REF current in the V FB pin to change the V OUT. If we want the V OUT to be higher, we let the IREF-Generator sinks the I REF in the V FB pin. The V FB then decreases with the I REF current, and the V OUT increases. If we need a lower V OUT, we let the IREF-Generator source the I REF in the V FB pin. The V FB then increases with the I REF current, and the V OUT decreases. Fig. 2. CPU workload current and V IMON. The devices on the PC motherboard mostly use a DC-DC buck converter to provide a voltage source. The DC-DC buck converter output voltage value (V OUT ) is determined by the feedback voltage (V FB ). Fig. 3 shows how the DC-DC buck converter adjusts the output voltage. Assuming that the required device operating voltage is 1.2V, we should make sure that the V OUT is fixed at 1.2V. There is an internal reference voltage (V REF ) in the controller of the DC-DC buck converter which is a fixed voltage of 0.8V. We match the V OUT by R2 / (R1 + R2) and get the V FB = 0.8V. If we want to change the V OUT, we just change the V FB. Fig. 3. Feedback voltage circuit of buck converter. We propose a new method to reduce the system level power consumption of a PC by which we lower the operating voltage of devices. We can easily obtain the necessary CPU load current by V IMON and then ascertain the CPU working state. For all devices we can increase the operating voltage if the CPU works in high-performance status, thus making the PC system more stable, and we can decrease it if the PC works in a low-performance status, thus reducing the PC system power consumption. We have designed a circuit that dynamically changes the input reference voltage V FB according to the V IMON. This circuit easily changes the DC-DC Buck Converter output voltage V OUT. Based on the voltage characteristics of the different devices the control circuit makes adjustments, because their voltage operation ranges are not identical. Fig. 4 is the circuit of the IREF-DVS Regulator circuit. There is an Fig. 4. Circuit of IREF-DVS regulator. II. DESIGN OF THE IREF-DVS REGULATOR Fig. 5 shows the schematics of the IREF-Generator. There is a group of 8-bit target-voltage setting inputs, a decoder and a set of internal current generators. We set the V OUT through the 8-bit input value. The 8-bit V OUT is decoded by the decoder. The V OUT is converted to I REF into a current generator. The current generator is an adjustable current sink/source which can adjust the I REF current upward or downward. Through the SMBus of the motherboard we control the IREF-Generator. We depend on the V IMON, set 3 trigger-points and 4 steps of the V OUT, and let the V OUT change in steps. Fig. 6 is the flow chart of the IREF-DVS. We use the SMBus interface of the PC motherboard to control the IREF-DVS. With the SMBus it is easy to control both the size and the direction of the I REF. When we need to decrease the output voltage, the motherboard BIOS reads the trigger-points of the V IMON and the voltage step values through the SMBus. Nest the decoder of the IREF-Generator turns on the top of the current source array. Its source current increases the V FB, and the V OUT decreases. To increase the output voltage, the motherboard BIOS reads both the trigger-points of the V IMON and the voltage step values through the SMBus. Next the decoder of the IREF-Generator turns on the bottom of the current sink array. The IREF-Generator sinks the current to decrease the V FB, and the V OUT increases. In addition, when the V IMON changes up and down in real-time, according to its three trigger-points, the V OUT changes synchronously SI International 2011

4 Fig. 5. Schematics of IREF-Generator. Fig. 7. V IMON and V OUT with IREF-DVS regulator. III. EXPERIMENTATIONS In this experiment we have used two independent groups of IREF-DVS Regulators and have selected two different operating voltages of the Devices on a PC motherboard {CPU-VTT, DDRIII-VDD}. Now we can verify the power saving improvements in this test PC. Fig. 6. Flowchart for IREF-DVS regulator. Fig. 7 shows the relationship between V IMON and V OUT after using the IREF-DVS. When the PC runs a program, the CPU load current increases and changes dynamically, and the voltage of the V IMON also increases and changes with the CPU load current. When the IREF-DVS senses that the V IMON should change upwards, it means that as the PC is currently running on a high-performance program, a higher operating voltage is needed to improve the working performance. Therefore the sinking of the current in the V FB by the IREF-DVS causes the V OUT to increase. When the program is finished, the CPU operating current drops, the V IMON also decreases, and when the IREF-DVS senses that the V IMON should change downward, it means that the PC currently does not require an operating voltage for a high-performance program. Therefore the sourcing of the current in the V FB by the IREF-DVS causes the V OUT to decrease, thus saving power. Fig. 8. Test devices with IREF-DVS regulator. TABLE III RELATIONSHIP BETWEEN CPU LOADING AND V IMON Test Condition Win XP only (CPU Loading 2%) CPU Loading 25% CPU Loading 50% CPU Loading 75% V IMON 59.9mV 509mV 710mV 910mV CPU Loading 100% 1.05V Fig. 8 is the block diagram of our test PC motherboard and the two devices with independent IREF-DVS regulators. We use Windows XP with Prime95 to find the relationship between CPU loading and V IMON. The five test conditions of the CPU loading are 2% (Windows XP only), 25%, 50%, SI International 2011

5 75%, 100%. Before using the IREF-DVS regulators we have measured the V IMON and the operational currents of the devices under the five test conditions. As shown in Table III, when the CPU loading changes from 2% to 25%, the V IMON shows a great change. The proposed design can save on the power consumption of CPU-VTT and DDRIII-VDD with IREF-DVS regulators when the CPU loading is less than 75%. We have first measured the relationship between the V IMON and the operating voltages of the two devices. In Fig. 9, we observe the operational voltage without IREF-DVS regulators, where the two voltages are maintained at the original level {CPU-VTT, DDRIII-VDD} = {1.1V, 1.5V}, not changing with the V IMON. When using the IREF-DVS regulators, the two operational voltages change with the V IMON, in real-time, as shown in Fig. 10. Table IV shows the settings of the three V IMON trigger-points {244mV, 488mV, 976mV} and the four-step supply voltages of the two devices on our test motherboard. V IMON TABLE IV SETTINGS OF FOUR-STEP VOLTAGES REFER TO V IMON CPU-VTT Voltage DDRIII-VDD Voltage 0-244mV 1.045V 1.425V mV 1.065V 1.450V mV 1.080V 1.475V mV 1.100V 1.500V IV. TEST RESULT Normally, when a PC is operating the CPU loading always changes with the program action. To understand the performance and the power consumption with IREF-DVS regulators we have measured the total power consumption on a test PC under the four conditions below. 1. Idle in Win XP (Not running any program) 2. Play DVD (Windows Media Player) 3. 3DMark06 4. Restaurant Facebook We have measured the power consumption on a 12V power rail which is the input power for the CPU and the DDR. Fig. 11 is the comparison of the average power consumption of devices without IREF-DVS regulators and with IREF-DVS regulators under the four test conditions. Fig. 11 shows how the IREF-DVS regulators improve the power consumption under all conditions. Fig. 9. V IMON and device operational voltages without regulator. IREF-DVS Fig. 11. Comparison of average power consumption with and without IREF-DVS regulator. Fig. 10. V IMON and device operational voltages with IREF-DVS regulator. Fig. 12 is the performance score of 3Dmark06. We observe that the performance score is not markedly different between devices that here and do not have IREF-DVS regulators SI International 2011

6 (a) Devices without IREF-DVS regulator. (Score=1451) (b) Devices with IREF-DVS regulator. (Score=1448) Fig. 12. Performance score of 3DMark06. V. CONCLUSION In our design the working current of the actual monitoring CPU changes the device voltage. The device voltage changes in real-time and according to the real CPU working state. Power saving is at the system level. Through the SMBus control the proposed design sets the voltage steps and trigger-points. When the operating voltage in the device follows the specifications, it sets a dynamically change the voltage to the most power-saving mode. The test results show that through the IREF-DVS regulator this design reduce power consumption by more than 2W, an improvement of about 5%. In the future we will try to change the device voltage to less than operating voltage specifications to achieve even greater power saving. REFERENCES [1] Intel Corporation, Intel Core i7-800 and i5-700 Desktop Processor Series, and Intel Xeon Processor 3400 Series External Design Specification-Volume 1 Revision 2.1, _Lynnfield_EDS_Rev2_1_Vol_1.pdf?HashKey= _d32ce138654be9f4c74312f230f7b8b0, June, [2] J. Charles, P. Jassi, N. S. Ananth, A. Sadat, and A. Fedorova, Evaluation of the Intel Core i7 Turbo Boost feature, IEEE International Symposium on Workload Characterization, pp , Oct [3] Bin Lin, A. Mallik, P. Dinda, G. Memik, and R. Dick, User- and Process-Driven Dynamic Voltage and Frequency Scaling, IEEE International Symposium on Performance Analysis of Systems and Software, pp , April, [4] Taewhan Kim, Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling, 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pp , [5] Longhao Shu, and Xi Lin, Temperature-Aware Energy Minimization Technique through Dynamic Voltage Frequency Scaling for Embedded systems 2nd International Conference on Education Technology and Computer, pp , June, [6] Yu-Wei Yang, K. and Shu-Min Li, Temperature-Aware Dynamic Frequency and Voltage Scaling for Reliability and Yield Enhancement, Design Automation Conference, pp.49-54, Jan [7] Xiliang Zhong, and Cheng-Zhong Xu, Energy-Aware Modeling and Scheduling for Dynamic Voltage Scaling with Statistical Real-Time Guarantee, IEEE Transactions on Computers, pp , March [8] Cai Yuan, S. M. Reddy, I. Pomeranz, and B. M. Al-Hashimi, Battery-aware Dynamic Voltage Scaling in Multiprocessor Embedded System, IEEE International Symposium on Circuit and Systems, pp , May, [9] Younglin Cho, Younghyun Kim, Yongsoo Joo, Hyungsoo Lee, and Naehyuck Chang, Simultaneous Optimization of Battery-Aware Voltage Regulator Scheduling with Dynamic Voltage and Frequency Scaling, 2008 ACM/IEEE International Symposium on Low Power Electronics and Design, pp , Aug [10] Intel Corporation, Piketon / Kings Creek and Foxhollow Platform Design Guide Rev 1.5, _Lynnfield_EDS_Rev2_1_Vol_1.pdf?HashKey= _d32ce138654be9f4c74312f230f7b8b0, July, [11] G. A. Paleologo, L. Benini, A. Bogliolo, and G. De Micheli, Policy Optimization for Dynamic Power Management, Design Automation Conference, pp , June, [12] H. R. Pourshaghaghi, and J. P. de Gyvez, Dynamic Voltage Scaling Based on Supply Current Tracking Using Fuzzy Logic Controller, 16th IEEE International Conference on Electronics, Circuits, and Systems, pp , Dec [13] ON Semiconductor, NCP5395T 2/3/4-Phase Controller with On Board Gate Drivers for CPU Applications, D.PDF, Nov SI International 2011