LOWERING POWER CONSUMPTION OF HEVC DECODING. Chi Ching Chi Techinische Universität Berlin - AES PEGPUM 2014

Transcription

1 LOWERING POWER CONSUMPTION OF HEVC DECODING Chi Ching Chi Techinische Universität Berlin - AES PEGPUM 2014

2 Introduction How to achieve low power HEVC video decoding? Modern processors expose many low power techniques Clock gating, power gating, DVFS, asymmetric cores Increase application performance SIMD, multithreading Two (contradicting) general approaches: Exploit slack Race to idle What combination is best for video decoding? Slide 2

3 Outline Introduction Architectural Low Power Modes Power Optimization HEVC Decoder Platforms and Methodology Results Offline Decoding Real-time Decoding Efficiency Out-of-the-box Conclusions Slide 3

4 Architectural Techniques Power consumption processor: P cpu = αnkv dd I leak }{{} P static + (1 α)ncfv 2 dd }{{} P dynamic (1) Modern architecture incorporate various low power techniques to reduce the active and idle power Active power Dynamic Voltage Frequency Scaling (DVFS) Asymmetric cores Idle power Clock gating Power gating Slide 4

5 Low Power Active DVFS lowers V dd, I leak, f P static P dynamic Asymmetric ARM big.little extend DVFS in lower performance regions In Linux cpufreq subsystem controls both DVFS and asymmetric core switching Governors change frequency depending on load exynos_cpufreq driver maps Little cores to lower frequencies In general responds to load quickly to avoid performance regression Slide 5

6 Low Power Idle I Clock gating and power gating used to implement idle states (C-states) ACPI defines C0 - C3, Intel extends up to C10 Intel core C-states C0 Core is execution code C1 C1E C3 Core is halted most clocks are stopped Voltage reduced to Pn Core L1/L2 flushed to L3, PLL stopped C6-C10 Core state saved and power gated Slide 6

7 Low Power Idle II Intel package C-states C3 Mem self-refresh, some uncore clocks C6 C7 C8 stopped, some voltages reduced All uncore clocks stopped L3 power gated, more voltages reduced Most uncore power gated C9-C10 FIVR in low power/off state In Linux cpuidle subsystem controls C-states Trade off power saving in lower C-state vs. transition cost Predicts duration of next idle period to select C-state C-state, transition time, transition energy model specific Vendor supplies this in model/series specific drivers Slide 7

8 Outline Introduction Architectural Low Power Modes Power Optimization HEVC Decoder Platforms and Methodology Results Offline Decoding Real-time Decoding Efficiency Out-of-the-box Conclusions Slide 8

9 Power Optimization HEVC Decoder Two usage models HEVC decoding : offline and real-time Offline decoding Improve application performance General optimization ISA/Architecture specific (e.g. SIMD) Multithreading Additionally for real-time decoding Decrease worst-case complexity Coalesce computation Slide 9

10 Real-time Video Decoding I Decrease worst-case complexity using playback buffers Frametime (ms) 50 T buf Frame Lower peaks allow for execution on lower frequency/slower cores Improves possibilities for exploiting slack Slide 10

11 Real-time Video Decoding I Decrease worst-case complexity using playback buffers Frametime (ms) 50 T buf Frame Lower peaks allow for execution on lower frequency/slower cores Improves possibilities for exploiting slack Slide 10

12 Real-time Video Decoding I Decrease worst-case complexity using playback buffers Frametime (ms) 50 T buf Frame Lower peaks allow for execution on lower frequency/slower cores Improves possibilities for exploiting slack Slide 10

13 Real-time Video Decoding II Improve C-state residency with burst decoding 60 Ready buffer Frame Perform decoding bursts to improve deeper C-state residency Improves effectiveness of race to idle in theory In practice has no significant benefit except rare configurations Slide 11

14 Real-time Video Decoding II Improve C-state residency with burst decoding 60 Ready buffer s Frame Perform decoding bursts to improve deeper C-state residency Improves effectiveness of race to idle in theory In practice has no significant benefit except rare configurations Slide 11

15 Outline Introduction Architectural Low Power Modes Power Optimization HEVC Decoder Platforms and Methodology Results Offline Decoding Real-time Decoding Efficiency Out-of-the-box Conclusions Slide 12

16 Platforms I Used 4 platform representative of modern PC and consumer electronics processors Power measurable but not completely comparable Series Model Process Die size Measurable power Cores Uncore DRAM Haswell i5-4670t 22nm 177mm 2 Haswell ULT i5-4200u 22nm 134mm 2 Baytrail-T Z nm 102mm 2 Exynos nm 122mm 2 (GPU) Slide 13

17 Platforms II Vdd Haswell 4670T Haswell 4200U BayTrail Z3740* Exynos A15 Exynos A MHz 500 Slide 14

18 Haswell i5-4670t Haswell 4 cores TDP 45 W Low power desktop/ all-in-one Source: Intel Uncore Dram Cores 20 C1E Slide 15 C tu 00 rb o tu 00 rb o C tu 00 rb o tu 00 rb o C tu 00 rb o tu 00 rb o tu 00 rb o tu 00 rb o Watt 30 1-core 2-core 3-core 4-core

19 Haswell ULT i5-4200u Haswell 2 cores ( SMT ) TDP 15 W Ulltrabook/convertibles Source: Intel Uncore Cores Dram Watt turbo turbo turbo turbo turbo turbo turbo C7 C3 C1E C1 1-core 2-core 2c4t Slide 16

20 Baytrail-T Z3740 Silvermont 4 cores SDP 2 W/ TDP 5 W? Tablets 6 Uncore Source: Intel, tweakers.net Cores Watt C6 C1 1-core 2-core 3-core 4-core Slide 17

21 Exynos 5410 A15 + A7 big.little cores TDP 6 W? Smartphones/Tablets 6 Cores Dram Watt L-500 L-800 L-1200 b-800 b-1200 b-1600 L-500 L-800 L-1200 b-800 b-1200 b-1600 L-500 L-800 L-1200 b-800 b-1200 b-1600 L-500 L-800 L-1200 b-800 b-1200 b-1600 L-500 L-800 L-1200 b-800 b-1200 b-1600 L-500 L-800 L-1200 b-800 b-1200 b-1600 C2 C1 1-core 2-core 3-core 4-core Slide 18

22 Methodology Use highly optimized HEVC Decoder developed by AES TUB All experiments executed under Linux (3.12+ for x86, 3.4 arm) GCC In total 100 FHD and UHD short 10 sec test sequences 1 second intra period, GOP size 8 FHD 24, 50, 60 fps with 40 to 200 kb/frame UHD 50 fps with 100 to 500 kb/frame Multithreading using wavefronts (WPP) Real-time execution simulated with 8 output picture buffer Slide 19

23 Outline Introduction Architectural Low Power Modes Power Optimization HEVC Decoder Platforms and Methodology Results Offline Decoding Real-time Decoding Efficiency Out-of-the-box Conclusions Slide 20

24 SIMD and Multithreading (1080p) Scalar SIMD mj/frame mj/frame Kb/frame Kb/frame SIMD+MT mj/frame Haswell 4670T Haswell 4200U BayTrail Z3740 Exynos A15 Exynos A Kb/frame Slide 21

25 SIMD and Multithreading (1080p) Scalar SIMD mj/frame mj/frame Kb/frame Kb/frame SIMD+MT mj/frame Haswell 4670T Haswell 4200U BayTrail Z3740 Exynos A15 Exynos A Kb/frame Slide 21

26 DVFS in Offline Decoding (1080p) Haswell 4670T Haswell 4200U Baytrail mj/frame MHz MHz MHz Cortex A15 Cortex A7 mj/frame T1 E tot T2 E tot T4 E tot MHz MHz Slide 22

27 DVFS in Offline Decoding (1080p) Haswell 4670T Haswell 4200U Baytrail mj/frame MHz MHz MHz Cortex A15 Cortex A7 mj/frame T1 E tot T2 E tot T4 E tot T1 E core T2 E core T4 E core MHz MHz Slide 22

28 DVFS in Real-time Decoding (1080p50 4.5Mbps) Haswell 4670T Haswell 4200U Watt T1 P tot T2 P tot T4 P tot T1 P core T2 P core T4 P core Baytrail Exynos T4 P tot T4 P core Watt MHz MHz Slide 23

29 DVFS in Real-time Decoding (1080p50 4.5Mbps) Haswell 4670T Haswell 4200U Watt T1 P tot T2 P tot T4 P tot T1 P core T2 P core T4 P core Ondemand Baytrail Exynos 5410 Watt T4 P tot T4 P core Ondemand MHz MHz Slide 23

30 Efficiency Out-of-the-box Haswell 4670T Haswell 4200U (no SMT) Watt p ondem. 2160p ondem Baytrail Z Exynos p ondem. Watt Activity (MCycles/s) Activity (MCycles/s) Slide 24

31 Efficiency Out-of-the-box Haswell 4670T Haswell 4200U (no SMT) Watt p ondem. 2160p ondem. 1080p manual 2160p manual Baytrail Z Exynos 5410 Watt p ondem. 1080p manual 1080p man. A Activity (MCycles/s) Activity (MCycles/s) Slide 24

32 Outline Introduction Architectural Low Power Modes Power Optimization HEVC Decoder Platforms and Methodology Results Offline Decoding Real-time Decoding Efficiency Out-of-the-box Conclusions Slide 25

33 Conclusions I How to achieve low power HEVC decoding: Offline decoding Application optimization (SIMD+MT) DVFS only when cores are consuming most of energy Real-time decoding Exploiting slack preferred over race to idle Multithreading only helpful when lowering clock < 2W for 1080p50 in software Limitations low power modes: OS not selecting lower frequencies Not able to determine when exploiting slack is desired Slide 26

34 Conclusions II Around 30%! power savings possible Architectures not efficient at low activity DVFS targets mainly cores, but cores consume little power at low frequency big.little solves reduced effectiveness DVFS closer to V th, but not main problem (for Intel) Deeper idle states + race to idle not a replacement Slide 27

35 Future Work Include rendering power in analysis Extend towards more OS (Windows, Android, IOS, etc..) Investigate towards application driven DFVS control Slide 28