AN1775 APPLICATION NOTE

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1 N77 PPLITION NOTE STR7x Hardware evelopment Getting Started Introduction This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the STR7x product family and describes the minimum hardware resources required to develop an STR7x application. etailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. Rev October 00 /7 7

2 N77 ontents Power management Overview Power management block lock management lock control unit Real Time lock US clock Hardware implementation Reset management oot management ebug management IE debug tool JTG / IE connector Reference esign Main lock Reset oot mode Wake-Up Power supplies US full speed interface N interface RS serial interface Serial ROM SPI Flash I EEPROM: JTG interface SRM /7

3 N77.9 Flash L interface onclusions and recommendations Schematics /7

4 Power management N77 Power management. Overview The chip is powered by an external V supply(v :.7 to. V, V :.0 to. V). ll I/Os are V-capable. n internal Voltage Regulator generates the supply voltage for core logic (~=.8V). The two V 8 pins must be connected to external stabilization capacitors. The following figure indicates the recommended configuration for the power supply pins: Figure. STR7x power supply pins V V STR7x V IO-PLL nf 0µF V 8 V SSIO-PLL V SS V SSKP µf V 8KP. Power management block The following figure describes the power management block implemented on the STR7x devices. Figure. Power Management lock V. V V Main Voltage Regulator (MVR) Low Power Voltage Regulator (LPVR) I/O circuitry V 8.8 V ORE nf 0µF V 8KP µf switch see note ackup block The STR7x power management block has two regulators: The Main Voltage Regulator MVR. The Low Power Voltage Regulator LPVR. Note the following remarks about the two regulators: oth regulators can be switched-off by software /7

5 N77 Power management V8 can be used to supply an externally regulated.8v, but V must supply the IOs V8KP pin can be used to externally supply the backup logic, but V must supply the IOs The switch in Figure, opened only during STNY mode, disconnects the V 8 domain from the V 8KP domain It is possible to switch-off the MVR and keep LPVR on when the device is in low-power mode (SLOW, WFI, LPWFI, STOP or STNY). The LPVR has a different design from the main VR and generates a non-stabilized and non-thermally-compensated voltage of approximately.v. In STNY mode the Low Power VR can be switched off when an external regulator provides a.8v supply to the chip through the V8KP pin for use by RT and Wake-Up block. In this case we must to keep the.v on pin V even if the two regulators are switch off to keep stable state on the I/Os. Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the maximum allowed operating frequency is MHz. This is due to the limitation imposed by the LPVR which is not able to generate sufficient current to operate in run mode. The MIN EVIE ORE is powered from an external V power supply pin (V ) through the main regulator. For more details on the power regulators, refer to the STR7x Reference Manual. /7

6 lock management N77 lock management The STR7x offers a flexible way for selecting core and peripherals clocks, the devices have up to external clock sources: The PRU generates the internal clocks for the PU and for the on-chip peripherals. The PRU may be driven by an external pulse generator, connected to the K pin. The Real time lock khz oscillator is connected to the internal K_F signal (if present on the application), and this clock source may be selected when low power operation is required. US clock source available only with devices with US feature.. lock control unit The STR7x clock control unit must be driven by an external oscillator, connected to the K pin, at a frequency of up to MHz. It generates the clocks for the PU and for the on-chip peripherals. range of available multiplication and division factors allows for a large number of operating clock frequencies to be driven from the input frequency. However, great care must be taken to respect the recommendations for allowed frequency limits. For more details on allowed operating frequencies for each clock, refer to the Reference Manual. The following diagram shows the basic implementation of the main external clock. Figure. Main clock oscillator OSILLTOR STR7x K V VSS The following table gives frequency range examples of the Main clock for some input clock values: Input lock MLK (Main lock) Range MHz [ Hz, 0 MHz] 8 MHz [0 Hz, 0 MHz] MHz [00 Hz, 0MHz]. Real Time lock The Real Time lock operates at a speed of khz. This clock must be provided by an external resonator circuitry. The RT is used to generate a time base, and can be selected when low power operation is needed. Refer to the Reference Manual for more details. /7

7 N77 lock management Figure. RT oscillator khz RYSTL pf* pf* STR7x RTXTI RTXTO V SS * these values are given only as examples, refer to the crystal manufacturer for more details. US clock STR70 and STR7 series microcontrollers contain a US.0 Full Speed device module interface that operates at a precise frequency of 8 MHz. This clock is usually provided by an external oscillator connected to the US clock pin USLK. However, to save the board s space and cost, the 8MHz US clock can also be generated by the internal PLL using one single external oscillator for both system and US module. This part of the application note describes the hardware and software reference implementation. US Full Speed signal quality and jitter results can be measured using a single external oscillator to generate not only the System PLL clock and Peripheral s clocks, but also the 8MHz US clock... Hardware implementation The hardware implementation guidelines are described in the figure below. 7/7

8 lock management N77 Figure. US clock and pins implementation V 7K US Indicate K 7E STR70/STR7 K GPIO GPIO P K 0 Ohm pf Vbus + US connector M 0 Ohm - pf V SS K V US LK 8MHz Oscillator US full speed interface device supported via type connector. The US clock uses a separate 8 MHz oscillator. Transistor circuit used to indicate the cable status (able connected US/IN pin = 0 logic, able deconnected = US/IN pin = logic). 8/7

9 N77 Reset management Reset management oth the Main Voltage Regulator and the Low Power Voltage Regulator contain an LV. They keep the device under reset when the corresponding controlled voltage value (V 8 or V 8KP falls below.v±0%). The LVs do not monitor V which supplies the I/O and analog parts of the device. Note: uring power-on, a reset must be provided externally. t power on, the nrstin pin must be held low by an external reset circuit until V. Figure gives an example of the hardware implementation of the RESET circuit for STR7x devices. The STM00 low-power MOS microprocessor supervisory circuit is used to assert a reset signal whenever the V voltage falls below a preset threshold or a manual reset is asserted. Figure. Hardware reset implementation STR7x V nrstin V SS Reset_P K +V08 STM00T not Reset V nf * these values are given only as typical example 9/7

10 oot management N77 oot management Three different boot modes are available and can be enabled by means of three input pins: OOTEN, OOT0 and OOT. The following table describes the different boot mode configurations. OOTEN OOT0 OOT OOT Mode 0 x x Reserved USER: boot from internal FLSH memory 0 RM: boot from internal RM memory EXTMEM: boot from external memory mapped on the EMI interface at h address. The following figure gives an implementation example of boot management for STR7x devices. OOT0 and OOT are alternate function pins used for boot configuration during the RESET phase (floating-input configuration), so they can be used afterwards in the application as standard I/Os. For more details concerning boot configuration, refer to the device reference manual. Figure 7. oot mode selection implementation example V * V * V * these values are given only as typical example * STR7x OOTEN nsty OOT0 OOT TEST * V Note: s the nsty pin has a floating input configuration, an external pull-up has to be provided to avoid remaining in stand-by mode. The TEST pin of the STR7x must always be forced to ground (ST reserved test pin) 0/7

11 N77 ebug management ebug management The Host/Target interface is the hardware equipment that connects the Host to the application board. This interface is made of three components: a hardware debug tool, such as Micro-IE from RM, a JTG connector and a cable connecting the host to the debug tool. Figure 8 shows the connection of the host to the STR7x board. Figure 8. Host to board connection IE ebug tool IE connector HOST P STR7x OR Power Supply. IE debug tool IE ebug tool is a host interface that connects a P to an STR7x development board featuring a debug interface as shown in Figure 8. The Embedded IE is an intelligent host interface that provides fast access to host services, access to on-chip emulation and debug facilities. When you are using the ST7R7x board as stand-alone system, the IE ebug tool can be used to download programs. The STR7x development kit supports the RM RealView IE Micro Edition. The Micro-IE is plugged in to the host via a US cable.. JTG / IE connector The IE connector enables JTG hardware debugging equipment, such as RealView-IE, to be connected to the ST7R7x board. It is possible to both drive and sense the system-reset line, and to drive JTG reset to the core from the IE connector. The Figure 9 shows the RM IE connector pin-out. The STR7x has a user debug interface. This interface contains a five-pin serial interface conforming to JTG, IEEE standard 9.-99, Standard Test ccess Port-Scan oundary rchitecture. JTG allows the IE device to be plugged to the board and used to debug the software running on the STR7x. JTG emulation allows the core to be started and stopped under control of the connected debugger software. The user can then display and modify registers and memory contents, and set break and watch points. /7

12 ebug management N77 Figure 9. Ice connector implementation STR7x njtrst JTI JTMS JTK JTO nrstin GRQS * * K V V See Note V J J * JTG onnector N9 ONN_*0 R_I () VTref () ntrst () TI (7) TMS (9) TK () RTK () TO () nsrst (7) GRQ (9) GK** () () () (8) (0) () () () (8) (0) V 7K TR 8 TR 8 0v 0nF * these values are given only as typical example ** The ebug acknowledge to JTG equipment (GK pin) is not used. Note: In order for JTG and hip Reset to be synchronized the J jumper must be fitted. STR7x has a ebug Request (GRQS) pin, on -pin packages only. This active high signal can be used to force the core to enter ebug Mode, giving the Emulation system access to internal resources (code, registers, memory, etc). This pin must be kept LOW when emulation is not being used. The following table describes the JTG connector pins: Std Name STR7x escription Function ntrst JTRST Test Reset (from JTG equipment) This active LOW open-collector is used to reset the JTG port and the associated debug circuitry. It is asserted at power-up by each module, and can be driven by the JTG equipment. TI JTI Test data in (from JTG equipment) TI goes down the stack of modules to the motherboard and then back up the stack, labelled TO, connecting to each component in the scan chain. TMS JTMS Test mode select (from JTG equipment) TMS controls transitions in the tap controller state machine. TMS connects to all JTG components in the scan chain as the signal flows down the module stack. TK JTK Test clock (from JTG equipment) TK synchronizes all JTG transactions. TK connects to all JTG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good signal integrity. TK flows down the stack of modules and connects to each JTG component. However, if there is a device in the scan chain that synchronizes TK to some other clock, then all down-stream devices are connected to the RTK signal on that component. /7

13 N77 ebug management Std Name STR7x escription Function RTK (not used) Return TK (to JTG equipment) Some devices sample TK (for example a synthesizable core with only one clock), and this has the effect of delaying the time that a component actually captures data. Using a mechanism called adaptive clocking, the RTK signal is returned by the core to the JTG equipment, and the clock is not advanced until the core had captured the data. In adaptive clocking mode, the debugging equipment waits for an edge on RTK before changing TK. TO JTO Test data out (to JTG equipment) TO is the return path of the data input signal TI. nsrst nrstin System reset (bidirectional) nsrst is an active LOW open-collector signal that can be driven by the JTG equipment to reset the target board. Some JTG equipment senses this line to determine when a board has been reset by the user. When the signal is driven LOW by the reset controller on the core module, the motherboard resets the whole system by driving nsysrst low. GRQ GK GRQS (not used w/ pin) (not used) ebug request (from JTG equipment) ebug acknowledge (to JTG equipment) GRQ is a request for the processor core to enter debug state. GK indicates to the debugger that the processor core has entered debug mode. For more details on the JTG port refer to the IEEE standard 9.-99, Standard Test ccess Port-Scan oundary rchitecture specification. /7

14 Reference esign N77 Reference esign. Main.. lock.. Reset This reference design is based on the STR70FZT, a highly integrated microcontroller, running at 8 MHz that combines the popular RM7TMI TM -bit RIS PU with Kbytes of embedded flash, Kbytes of high speed SRM, and numerous on-chip peripherals. +. V surface mounted MHz oscillator provides the main clock source: S, please refer to Section. on page for more details. RT real-time clock for wakeup from standby mode with KHz crystal: Y0, please refer to Section. on page for more details. One push button S is used to generate a hardware reset, please refer to Section on page 9 for more details... oot mode Three switches S08, S09 and S0 are used to select the boot Mode, please refer to Section on page 0 for more details... Wake-Up S push button is used to exit from STNY mode (power supply voltage removed except Real time lock). For more details, please refer to the STR7x reference manual.. Power supplies Power to the board is supplied using a power supply providing V to the board. ll other required voltages are provided by the on-board voltage regulator V L08V and Zener iode LM00 for input voltage. For more details, refer to L08V, LM00 datasheets and Section on page.. US full speed interface US full speed interface device supported via type connector. The US clock uses a separate 8 MHz oscillator. transistor circuit is used to indicate the cable status (able connected US/IN pin = 0 logic, able deconnected = US/IN pin = logic). /7

15 N77 Reference esign. N interface general purpose, asynchronous serial I/O data port connected through a 9-pin -type male connector with micro switches selectable between High or Low bus output S70, and between Standby or Slope control S700. For more details, refer to N transceiver SNHV0 datasheet.. RS serial interface general purpose, asynchronous serial I/O data ports is connected through 9-pin -type male connectors. RS connects directly to URT0, transmit and receive only (null modem). RTS is shorted to TS and TR is shorted to SR at the connector. For more details, refer to RS transceiver ST datasheet.. Serial ROM.. SPI Flash -Mbit SPI serial flash connected to the buffered serial peripheral interface (SPI). Switch S0 is used to enable or disable write protect (pull down = Write protect, pull up = Write enabled). For more details, refer to SPI Flash MP0- datasheet... I EEPROM: 8-kbit EEPROM connected to the I0 interface, Switch S00 is used to enable or disable write protect (pull down = Write protect, pull up = Write enabled). For more details, refer to I Eeprom M08 datasheet. The values R and R are dependent on the I communication speed. For more details on theses values, please refer to the STR7x reference manual..7 JTG interface Refer to the section Section on page..8 SRM Two SRM M byte are connected to External Interface Memoy EMI and mapped from 0x to 0xF FFFF. For more details, refer to the SRM memory TV800FT- datasheet. /7

16 Reference esign N77.9 Flash One Flash M word is connect to External Interface Memoy EMI and mapped from 0x to 0x0F FFFF (boot bank). For more details, refer toflash memory M8W0E datasheet..0 L interface Ld * is connected to external interface memory EMI. ddress is used as the L register address signal. Region space available from 0x to 0xFF FFFF. onclusions and recommendations System clock jitter values decrease when the system clock is delivered by STR7x internal PLL (comparing to the jitter values on the external oscillator inputs), because the noise injected in the LK pin input was filtered by the internal PLL. It is possible to use one single external MHz oscillator to generate both core, peripheral s clocks and 8MHz US clock to minimize and save board cost and space. With this single external oscillator generating both the system clock using PLL and the 8Mhz US clock using PLL, the STR70/STR7 has all the characteristics to pass the requirements for US revision.0 full speed device test and get the US certification. Particular care must be taken to decrease external oscillator noise while routing its clock on board. /7

17 N77 7 Schematics 7 Schematics Figure 0. Reference design top level schematics OOT_EN OOT.0 SRM.Sch L.Sch page (:0) T (:0) not S_SRM not OE not WR0 not WR page T (7:0) RS note R/W FLSH.Sch (:0) T (:0) not S_FLSH not OE not WR vpp not RESET page P.0_not S.0 P._not S. P._not S. P._not S P._.0 P._. P._. P.7_ not R not WE.0 not WE. P.8 TEST TEST NU GRQS JTI JTO JTK JTMS not JTRST not RSTIN K KOUT RTXTO RTXTI OOT_EN P0.9_U0.TX_OOT.0 P0._U.TX_OOT. P._NRX P._NTX USP USN P.0_USLK P. P. P._HRX_I0.S P._HLK_I0.SL P0._S.MISO P0._S.MOSI P0._S.SLK P0.7_S.SSN P.8 P0._U.RX_T.OMP P0._U.TX_T.IP P.0_T.OMP_IN.0 P0.0_S0.MISO_U.TX P0._S0.MOSI_U.RX P0._S0.SLK_I.SL P0._S0.SSN_I.S P.9 P.0 P._T.OMP_IN. P._T.IP_IN. P._T.IP_IN. P._T.IP P._T.IP P._T.OMP P.7_T.OMP P.9 P._HTX P0.8_U0.RX_U0.TX P0.0_U.RX_U.TX_ST P0._SLK P. P. P Title STR70 MU * For not used pins set to logic level by software Size Number Revision ate: -Jun-00 Sheet of File: rawn y: VSS VSS VSS VSS VSS VSS VSS7 VSS P0._WKEUP not STY V_ V_ V_ V_ V_ V_ V_7 V V8_ VSS8_ V8_ VSS8_ V8KP VSSKP OOT. U0 7LX V R R0 R0 R R T0 T T T T T T T7 T8 T9 T0 T T T T T R8 STR70 Serial_ROM.Sch page S SL MISO MOSI SLK SSN not S JTG.Sch JTI JTO JTK JTMS not JTRST not Reset GRQS page 8 N.Sch N_RX N_TX page 7 RS.Sch page RX TX not Reset R00 R0 R GRQS IN LE_P0.0 LE_P0. LE_P0. LE_P0. utton_ utton_ LE_P0.0 LE_P0. LE_P0. LE_P0. R 0 R 0 R 0 R LE LE LE LE K 0 STM00T (.08V) not RESET V VSS R0 SW SPT S08 SW SPT S09 SW SPT S0 S SW-P 00 0nF R7 K R9 0uF 0 N 0 nf 0.0uF not RESET K KOUT RTXTO RTXTI OOT_EN OOT.0 OOT. RX TX GRQS US.Sch page 9 RX TX USP USN USLK USV_IN US_PULL_UP not RESET S SW-P K IN 0 nf R SW SPT S R7 S SW-P R0 RTXTI RTXTO 0.uF S MHz OS OUT V EN Y0 KHz 0 pf 0V *Switch used for calibration S utton_ utton_ R8 S7 SW-P +VN R R9 K7 pf 0V 0.uF.0 0 7/7

18 7 Schematics N77 Figure. L interface + R00 K7 R0 R0 T (7:0) T0 8 T 7 T T T T T T7 0 0 K VV IR R/W 9 G E 0 RS VO 7LX 0uF V V L LWM 0 -G/SYN 0 0.uF RnotW R0 U00 note 7LX V RS R09 K 0 00pF Title L Size Number Revision ate: -Jun-00 Sheet of File: rawn y: /7

19 N77 7 Schematics Figure. EMI Flash T (:0) (:0) R0 R0 R Q0 Q Q Q Q Q Q Q7 Q8 Q9 Q0 Q Q Q Q Q T0 T T T T T T T7 T8 T9 T0 T T T T T R08 not S_FLSH not E not WR not WE VPP vpp 8 not OE not OE not WP not RESET not RP FLSH M8W0E V Title FLSH Size Number Revision Text ate: -Jun-00 Sheet of File: rawn y: /7

20 7 Schematics N77 Figure. EMI SRM T (:0) (:0) R0 R0 R0 R IO_ IO_ IO_ IO_ IO_ IO_ IO_7 IO_8 9 T0 T T T T T T T7 R IO_ IO_ IO_ IO_ IO_ IO_ IO_7 IO_8 9 T8 T9 T0 T T T T T not WR0 not WE not WR not WE not S_SRM not E not E N_E N_E not OE not OE not OE SRM TV800FT- SRM TV800FT- V V Title SRM Size Number Revision.0 ate: -Jun-00 0 Sheet of 0 File: rawn y: 0/7

21 N77 7 Schematics Figure. RS interface 0 0.uF V 0 0.uF V TX RX 00 0.uF V TIN TIN ROUT ROUT TOUT TOUT RIN RIN 7 8 Title Size Number Revision ate: -Jun-00 Sheet of File: rawn y: V- V+ 0 0.uF V J00 R0 9 male ST V RS 0.0 /7

22 7 Schematics N77 Figure. Serial ROM interface R00 R0 R0 R S00 SW SPT SL R K7 7 R0 E E E SL not W S R K7 S * connect to pull-up by default I_EEPROM M08 V R7 R8 MOSI R9 Q MISO SLK S0 not S SW SPT 7 not S not W not HOL * connect to pull-up by default SPI_FLSH MP0- V R0 SSN Title SERIL MEMORY Number Revision Size ate: -Jun-00 Sheet of File: rawn y: 0.0 /7

23 N77 7 Schematics Figure. N interface SW SPT S700 R70 R70 N_TX N_RX R700 R V RS NH NL Vref SNHV0 V 8 7 R70 0 R J70 9 S70 SW-SPST Title N Number 7 Revision.0 Size ate: -Jun-00 Sheet 7 of File: rawn y: 0 /7

24 7 Schematics N77 Figure 7. JTG interface R800 R80 R80 JP80 not JTRst JTI JTMS 7 8 JTK 9 0 JTO GRQS R80 R80 R80 HEER 0X not Reset *Switch closed by default S80 SW SPST R87 K R uF R807 Q80 Q K 8 Title JTG Size Number 8 Revision.0 ate: -Sep-00 Sheet 8 of File: rawn y: 0 /7

25 N77 7 Schematics Figure 8. US interface R900 7K USV_IN R90 K R90 K Q900 7E US_PULL_UP R90 K USN USP R90 0 R90 0 VUS N P R90 US_ON 900 pf 90 pf USLK J900 8MHz OS OUT EN V R907 Title Size US Number 9 Revision.0 ate: -Jun-00 Sheet 9 of File: rawn y: 0 /7

26 7 Schematics N77 Figure 9. Power schematics J000 JK +V +V R000 SV SG NX00 V G G G +V uF V 00nF 00 V 00nF 00 V 00nF 00 V 00nF 00 V L00 FE N 0 0uF V 0.uF 0 V 0nF 07 0v R00 K +VN 00 LM00 +V U00 VOLT_REG_V Vin Vout Title Number 0 Revision.0 File: rawn y: Size ate: -Jun-00 Sheet 0 of 0 0uF 0V 0 0nF 0V 08 0uF 0V 00 0nF 0V +V uF 0V 0uF 0 0V 00uF 0 0V 00uF 0 0V 0nF 07 0V 0nF 09 0V 0 00nF v nF V 00nF 0 v R00 K R LE 00 LE nF V 00nF 0 V nF V 00nF 00 V 00nF 0 V 00nF 0 V 0 00nF V 08 00nF V 00nF 00 00nF 0 V 00nF 0 V V nF V 00nF 07 V nF V 00nF 0 V 00nF 0 V 00nF 0 V 07 00nF V 09 00nF V 00nF 0 00nF 0 V V POWER 0 /7

27 N77 7 Schematics THE PRESENT NOTE WHIH IS FOR GUINE ONLY IMS T PROVIING USTOMERS WITH INFORMTION REGRING THEIR PROUTS IN ORER FOR THEM TO SVE TIME. S RESULT, STMIROELETRONIS SHLL NOT E HEL LILE FOR NY IRET, INIRET OR ONSEQUENTIL MGES WITH RESPET TO NY LIMS RISING FROM THE ONTENT OF SUH NOTE N/OR THE USE ME Y USTOMERS OF THE INFORMTION ONTINE HEREIN IN ONNETION WITH THEIR PROUTS. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ll other names are the property of their respective owners 00 STMicroelectronics - ll rights reserved STMicroelectronics group of companies ustralia - elgium - razil - anada - hina - zech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of merica 7/7

STR710-EVAL. Evaluation Board for STR71xF. Main components. Description. Features. STR710-EVAL board

STR710-EVAL. Evaluation Board for STR71xF. Main components. Description. Features. STR710-EVAL board Evaluation Board for STR71xF STR710-EVAL board Host to JTAG interface High speed JTAG debug port connection Main components STR710F processor running at 48 MHz EMI SRAM 4 Mbytes (2M x 16) EMI flash 4 Mbytes