2 Mbit / 4 Mbit MPF with Block-Protection SST39SF020P / SST39SF040P / SST39VF020P / SST39VF040P

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1 FEATURES: Organized as K x / K x Single Voltage Read and Write Operations.-.V for SSTSF00P/00P.-.V for SSTVF00P/00P Superior Reliability Endurance: 00,000 Cycles (typical) Greater than 00 years Data Retention Low Power Consumption: Active Current: 0 ma (typical) Standby Current: 0 µa (typical) for SSTSF00P/00P µa (typical) for SSTVF00P/00P Sector-Erase Capability Uniform KByte sectors User-Selectable Top or Bottom KByte Block -Protection Feature Fast Read Access Time: and ns for SSTSF00P/00P 0 and 0 ns for SSTVF00P/00P Latched Address and Data PRODUCT DESCRIPTION The SSTSF00P/00P and SSTVF00P/00P are K x / K x CMOS Multi-Purpose Flash (MPF) with Block-Protection manufactured with SST s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SSTSF00P/00P devices write (Program or Erase) with a.-.v power supply. The SSTVF00P/ 00P devices write (Program or Erase) with a.-.v power supply. These devices conform to JEDEC standard pinouts for x memories. Featuring high performance Byte-Program, the SSTSF00P/00P and SSTVF00P/00P devices provide a maximum Byte-Program time of 0 µsec. To protect against inadvertent write, they have onchip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of at least 0,000 cycles. Data retention is rated at greater than 00 years. The SSTSF00P/00P and SSTVF00P/00P devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of Fast Erase and Byte-Program: Sector-Erase Time: ms typical Chip-Erase Time: 0 ms typical Byte-Program Time: µs typical Chip Rewrite Time: seconds (typical) for SSTSF/VF00P seconds (typical) for SSTSF/VF00P Automatic Write Timing Internal V PP Generation End-of-Write Detection Toggle Bit Data# Polling TTL I/O Compatibility for SSTSF00P/00P CMOS I/O Compatibility for SSTVF00P/00P JEDEC Standard Flash EEPROM Pinouts and command sets Packages Available -Pin PDIP -Pin PLCC -Pin TSOP (mm x mm) the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SSTSF00P/00P and SSTVF00P/00P devices are offered in -pin TSOP and -pin PLCC packages. A 00 mil, -pin PDIP is also offered for SSTSF00P/ 00P devices. See Figures, and for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting low while keeping low. The address bus is latched on the falling edge of or, whichever occurs last. The data bus is latched on the rising edge of or, whichever occurs first. 000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. 0-0 /00 These specifications are subject to change without notice. 0

2 Read The Read operation of the SSTSF00P/00P and SSTVF00P/00P devices are controlled by and, both have to be low for the system to obtain data from the outputs. is used for device selection. When is high, the chip is deselected and only standby power is consumed. is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either or is high. Refer to the Read cycle timing diagram for further details (Figure ). Byte-Program Operation The SSTSF00P/00P and SSTVF00P/00P devices are programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either or, whichever occurs last. The data is latched on the rising edge of either or, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth or, whichever occurs first. The Program operation, once initiated, will be completed, within 0 µs. See Figures and for and controlled Program operation timing diagrams and Figure 0 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Also, if a Byte-Program command is issued to a location in a protected Block, it will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of KByte. The Sector-Erase operation is initiated by executing a six-byte-command sequence with Sector-Erase command (0H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth pulse, while the command (0H) is latched on the rising edge of the sixth pulse. The internal Erase operation begins after the sixth pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Also, if a Sector- Erase command is issued to a sector in a protected block, it will be ignored. Mbit / Mbit MPF with Block-Protection Chip-Erase Operation The SSTSF00P/00P and SSTVF00P/00P devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the s state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (0H) with address H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth or, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table for the command sequence, Figure 0 for timing diagram, and Figure 0 for the flowchart. Any commands written during the Chip-Erase operation will be ignored. Also, if a block is protected, it will not be erased by this operation. Write Operation Status Detection The SSTSF00P/00P and SSTVF00P/00P devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ ) and Toggle Bit (DQ ). The End-of-Write detection mode is enabled after the rising edge of which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two () times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ ) When the SSTSF00P/00P and SSTVF00P/ 00P devices are in the internal Program operation, any attempt to read DQ will produce the complement of the true data. Once the Program operation is completed, DQ will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ will produce a 0. Once the internal Erase operation is completed, DQ will produce a. During a Block-Protection operation, any attempt to read DQ will produce the compliment of the true data. Once the Block-Protection operation is complete, DQ will produce true data. The Data# Polling is valid after the

3 rising edge of fourth (or ) pulse for Program operation. For Sector or Chip-Erase or Block-Protect, the Data# Polling is valid after the rising edge of sixth (or ) pulse. See Figure for Data# Polling timing diagram and Figure for a flowchart. Toggle Bit (DQ ) During the internal Program or Erase or Block-Protect operation, any consecutive attempts to read DQ will produce alternating 0 s and s, i.e., toggling between 0 and. When the internal Program or Erase or Block- Protect operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth (or ) pulse for Program operation. For Sector or Chip- Erase or Block-Protect, the Toggle Bit is valid after the rising edge of sixth (or ) pulse. See Figure for Toggle Bit timing diagram and Figure for a flowchart. Data Protection The SSTSF00P/00P and SSTVF00P/00P devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A or pulse of less than ns will not initiate a write cycle. V DD Power Up/Down Detection: The Write operation is inhibited when V DD is less than.v for SSTSF00P/ 00P. The Write operation is inhibited when V DD is less than.v. for SSTVF00P/00P. Write Inhibit Mode: Forcing low, high, or high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Block-Protection The SSTSF00P/00P and SSTVF00P/00P offer the Block-Protection feature. When Block-Protection feature is enabled, the top or bottom KByte Block (four sectors) is permanently write-protected, i.e., it cannot be erased or re-programmed. The Block-Protection feature is enabled by loading a sixbyte command to the device with Top Block-Protect command (0H) and address AAA, or Bottom Block- Protect command (0H) and address. The internal protection begins with the rising edge of the sixth or, whichever occurs first, and is completed in T PR (ms). The completion of this operation can be detected by Data# Polling or Toggle Bit. Bottom Block is in address space: to 0FFF. Top Block is in address space: C000 to FFFF for SSTSF/VF00P C000 to FFFF for SSTSF/VF00P The Block-Protection feature, once enabled, cannot be disabled. The Block-Protection feature can only be used with either the top or the bottom blocks, but not both. If the Block-Protection is activated for either one of the blocks, any subsequent attempt to protect the other block will be ignored. Any Sector-Erase or Byte-Program to the protected block of the device will be ignored. Refer to Figure for the timing diagram and Figure for the flowchart. Block-Protection Status The SSTSF00P/00P and SSTVF00P/00P have a Block Status that describes whether the Block- Protection feature of the device is disabled or enabled, and if enabled, whether the top or bottom block is protected. In order to determine this, a three-byte command is loaded to the device, followed by a read with Address Don t Care. The contents of DQ-DQ0 indicate the status of the device. Refer to Table for details of this operation, as well as Figure for the timing diagram and Figure for the flowchart. Software Data Protection (SDP) The SSTSF00P/00P and SSTVF00P/00P provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., program and erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byteload sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of six byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within T RC. Product Identification The Product Identification mode identifies the devices as SSTSF/VF00P and SSTSF/VF00P and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SSTSF00P/00P and SSTVF00P/00P devices. Users may wish to use the Software Product Identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see 0

4 Table for hardware operation or Table for software operation, Figure for the Software ID Entry and Read timing diagram and Figure for the Software ID Entry command sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode or Block-Protection Status mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table for software command codes, Figure for timing waveform and Figure for a flowchart. Mbit / Mbit MPF with Block-Protection TABLE : PRODUCT IDENTIFICATION TABLE Address Data Manufacturer s Code 0000H BF H Device Code SSTSF00P 000H H SSTSF00P 000H H SSTVF00P 000H H SSTVF00P 000H H 0 PGM T.0 FUNCTIONAL BLOCK DIAGRAM X-Decoder EEPROM Cell Array Memory Address Address Buffers & Latches Y-Decoder Control Logic I/O Buffers and Data Latches DQ - DQ0 0 ILL B.0 SECTOR MAPPING DIAGRAM SSTSF/VF00P SSTSF/VF00P Protected Block Top Block FFFF F000 E000 D000 C000 B000 A Bottom Block Protected Block Top Block FFFF F000 E000 D000 C000 B000 A Bottom Block Protected Block Protected Block 0 ILL F.

5 SSTSF/VF00P SSTSF/VF00P A A A A A A V DD A A A A A A A A A A A A A A V DD NC A A A A A A A 0 Standard Pinout Top View Die Up SSTSF/VF00P SSTSF/VF00P 0 0 A0 DQ DQ DQ DQ DQ V SS DQ DQ DQ0 A0 A A A A0 DQ DQ DQ DQ DQ V SS DQ DQ DQ0 A0 A A A FIGURE : PIN ASSIGNMENTS FOR -PIN TSOP (mm x mm) 0 ILL F0.0 SSTSF/VF00P SSTSF/VF00P A A A A A A A A A A A A0 DQ0 DQ DQ VSS NC A A A A A A A A A A A0 DQ0 DQ DQ VSS 0 -Pin PDIP Top View 0 0 SSTSF/VF00P SSTSF/VF00P VDD A A A A A A A0 DQ DQ DQ DQ DQ VDD A A A A A A A0 DQ DQ DQ DQ DQ 0 FIGURE : PIN ASSIGNMENTS FOR -PIN PDIP 0 ILL F0b.0

6 SSTSF/VF00P SSTSF/VF00P A A A A A A A A0 DQ0 A A A A A A A A0 DQ0 SSTSF/VF00P SSTSF/VF00P A A A A A A A NC VDD VDD A A SSTSF/VF00P SSTSF/VF00P 0 A A A A A A A A -Pin PLCC A A Top View 0 A0 DQ A0 DQ 0 SSTSF/VF00P SSTSF/VF00P DQ DQ DQ DQ VSS VSS DQ DQ DQ DQ DQ DQ DQ DQ 0 ILL F0a.0 FIGURE : PIN ASSIGNMENTS FOR -PIN PLCC TABLE : PIN DESCRIPTION Symbol Pin Name Functions A MS -A 0 Address Inputs To provide memory addresses. During Sector-Erase A MS -A address lines will select the sector. DQ -DQ 0 Data Input/output To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when or is high. Chip Enable To activate the device when is low. Output Enable To gate the data output buffers. Write Enable To control the Write operations. V DD Power Supply To provide.-.v supply for SSTSF00P/00P.-.V supply for SSTVF00P/00P Vss Ground NC No Connect Unconnected Pins Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P, A for SSTSF/VF00P 0 PGM T.0

7 TABLE : OPERATION MODES SELECTION Mode A DQ Address Read V IL V IL V IH A IN D OUT A IN Program V IL V IH V IL A IN D IN A IN Erase V IL V IH V IL X X Sector address, XXh for Chip-Erase Standby V IH X X X High Z X Write Inhibit X V IL X X High Z/D OUT X X X V IH X High Z/D OUT X Product Identification Hardware Mode V IL V IL V IH V H Manufacturer Code (BF) A () MS - A = V IL, A 0 = V IL Device Code () A MS - A = V IL, A 0 = V IH Software Mode V IL V IL V IH A IN See Table Block-Protection V IL V IH V IL X X See Table Block-Protection Status V IL V IL V IH X DQ-0 () X 0 PGM T. TABLE : SOFTWARE COMMAND SEQUENCE Command st Bus nd Bus rd Bus th Bus th Bus th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Byte-Program H AAH AAAH H H A0H BA () Data Sector-Erase H AAH AAAH H H 0H H AAH AAAH H SA () x 0H Chip-Erase H AAH AAAH H H 0H H AAH AAAH H H 0H Software ID Entry () H AAH AAAH H H 0H Software ID Exit () XXH F0H Software ID Exit () H AAH AAAH H H F0H Bottom Block- H AAH AAAH H H 0H H AAH AAAH H H 0H Protection Top Block- H AAH AAAH H H 0H H AAH AAAH H AAAH 0H Protection Block-Protection H AAH AAAH H H H Status () 0 PGM T.0 Notes: () H for SSTSF00P, H for SSTSF00P and H for SSTVF00P, H for SSTVF00P () A MS = Most Significant Address A MS = A for SSTSF/VF00P, A for SSTSF/VF00P () Address format A -A 0 (Hex). Addresses A, A and A are Don t Care for Command sequence for SSTSF/VF00P. Addresses A,A, A and A are Don t Care for Command sequence for SSTSF/VF00P. () SA x for Sector-Erase; uses A MS-A address lines A MS = Most Significant Address A MS = A for SSTSF/VF00P, A for SSTSF/VF00P () BA = Program Byte address () Both Software ID Exit operations are equivalent; also needed to exit Block-Protection mode. () With A MS -A =0; SST Manufacturer Code = BFH, is read with A 0 = 0, SF00P Device Code = H, SF00P Device Code = H, is read with A 0 =. VF00P Device Code = H, VF00P Device Code = H, is read with A 0 =. () The device does not remain in Software Product ID Mode if powered down. () The fourth cycle of this operation will be a Read of Address XXXX. DQ-0 = 0 for bottom Block protected DQ-0 = 0 for top Block protected DQ-0 = 00 for neither Block protected 0

8 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias... - C to + C Storage Temperature... - C to +0 C D. C. Voltage on Any Pin to Ground Potential V to V DD+ 0.V Transient Voltage (<0 ns) on Any Pin to Ground Potential V to V DD +.0V Voltage on A Pin to Ground Potential V to.v Package Power Dissipation Capability (Ta = C)....0W Through Hole Lead Soldering Temperature (0 Seconds) C Surface Mount Lead Soldering Temperature ( Seconds)... 0 C Output Short Circuit Current ()... 0 ma Note: () Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR SSTSF00P/00P Range Ambient Temp V DD Commercial 0 C to +0 C.-.V Industrial -0 C to + C.-.V OPERATING RANGE FOR SSTVF00P/00P AC CONDITIONS OF TEST Input Rise/Fall Time... ns Output Load C L = 0 pf for SSTSF00P/00P C L = 00 pf for SSTVF00P/00P See Figures A, B and Range Ambient Temp V DD Commercial 0 C to +0 C.-.V Industrial -0 C to + C.-.V

9 TABLE A: DC OPERATING CHARACTERISTICS V DD = V±0% FOR SSTSF00P/00P Limits Symbol Parameter Min Max Units Test Conditions I DD Power Supply Current ==V IL,=V IH, all I/Os open, Read 0 ma Address input = V IL/V IH, at f=/t RC Min., V DD=V DD Max Write 0 ma ==V IL, =V IH, V DD =V DD Max. I SB Standby V DD Current ma =V IH, V DD = V DD Max. (TTL input) I SB Standby V DD Current 00 µa =V IHC, V DD = V DD Max. (CMOS input) I LI Input Leakage Current µa V IN =GND to V DD, V DD = V DD Max. I LO Output Leakage Current µa V OUT =GND to V DD, V DD = V DD Max. V IL Input Low Voltage 0. V V DD = V DD Min. V IH Input High Voltage.0 V V DD = V DD Max. V IHC Input High Voltage (CMOS) V DD -0. V V DD = V DD Max. V OL Output Low Voltage 0. V I OL =. ma, V DD = V DD Min. V OH Output High Voltage. V I OH = -00 µa, V DD = V DD Min. V H Supervoltage for A pin.. V = =V IL, = V IH I H Supervoltage Current 00 µa = = V IL, = V IH, A = V H Max. for A pin 0 PGM Ta. TABLE B: DC OPERATING CHARACTERISTICS V DD =.-.V FOR SSTVF00P/00P Limits Symbol Parameter Min Max Units Test Conditions I DD Power Supply Current ==V IL,=V IH, all I/Os open, Read 0 ma Address input = V IL /V IH, at f=/t RC Min., V DD=V DD Max Write 0 ma ==V IL, =V IH, V DD =V DD Max. I SB Standby V DD Current µa =V IHC, V DD = V DD Max. I LI Input Leakage Current µa V IN =GND to V DD, V DD = V DD Max. I LO Output Leakage Current µa V OUT =GND to V DD, V DD = V DD Max. V IL Input Low Voltage 0. V V DD = V DD Min. V IH Input High Voltage 0. V DD V V DD = V DD Max. V IHC Input High Voltage (CMOS) V DD-0. V V DD = V DD Max. V OL Output Low Voltage 0. V I OL = 00 µa, V DD = V DD Min. V OH Output High Voltage V DD -0. V I OH = -00µA, V DD = V DD Min. V H Supervoltage for A pin.. V = =V IL, = V IH I H Supervoltage Current 00 µa = = V IL, = V IH, A = V H Max. for A pin 0 PGM Tb. 0

10 TABLE : RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units T () PU-READ Power-up to Read Operation 00 µs T () PU-WRITE Power-up to Write Operation 00 µs 0 PGM T.0 TABLE : CAPACITANCE (Ta = C, f= Mhz, other pins open) Parameter Description Test Condition Maximum C () I/O I/O Pin Capacitance V I/O = 0V pf C () IN Input Capacitance V IN = 0V pf Note: () 0 PGM T.0 This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE : RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N () END Endurance 0,000 Cycles JEDEC Standard A T () DR Data Retention 00 Years JEDEC Standard A0 V () ZAP_HBM ESD Susceptibility 000 Volts JEDEC Standard A Human Body Model V () ZAP_MM ESD Susceptibility 00 Volts JEDEC Standard A Machine Model I () LTH Latch Up 00 + I DD ma JEDEC Standard 0 PGM T.0 Note: () This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. AC CHARACTERISTICS TABLE A: READ CYCLE TIMING PARAMETERS V DD =.-.V FOR SSTSF00P/00P SSTSF00P- SSTSF00P- SSTSF00P- SSTSF00P- Symbol Parameter Min Max Min Max Units T RC Read Cycle Time ns T CE Chip Enable Access Time ns T AA Address Access Time ns T OE Output Enable Access Time 0 ns T () CLZ Low to Active Output 0 0 ns T () OLZ Low to Active Output 0 0 ns T () CHZ High to High-Z Output 0 ns T () OHZ High to High-Z Output 0 ns T () OH Output Hold from Address Change 0 0 ns 0 PGM Ta.0 Note: () This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 0

11 AC CHARACTERISTICS TABLE B: READ CYCLE TIMING PARAMETERS V DD =.-.V FOR SSTVF00P/00P SSTVF00P-0 SSTVF00P-0 SSTVF00P-0 SSTVF00P-0 Symbol Parameter Min Max Min Max Units T RC Read Cycle Time 0 0 ns T CE Chip Enable Access Time 0 0 ns T AA Address Access Time 0 0 ns T OE Output Enable Access Time ns T () CLZ Low to Active Output 0 0 ns T () OLZ Low to Active Output 0 0 ns T () CHZ High to High-Z Output 0 ns T () OHZ High to High-Z Output 0 ns T () OH Output Hold from Address Change 0 0 ns 0 PGM Tb.0 Note: () This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. TABLE 0: PROGRAM/ERASE CYCLE TIMING PARAMETERS V DD =.-.V FOR SSTSF00P/00P AND.-.V FOR SSTVF00P/00P Symbol Parameter Min Max Units T BP Byte-Program Time 0 µs T AS Address Setup Time 0 ns T AH Address Hold Time 0 ns T CS and Setup Time 0 ns T CH and Hold Time 0 ns T OES High Setup Time 0 ns T OEH High Hold Time 0 ns T CP Pulse Width 0 ns T WP Pulse Width 0 ns T WPH Pulse Width High 0 ns T CPH Pulse Width High 0 ns T DS Data Setup Time 0 ns T DH Data Hold Time 0 ns T IDA Software ID Access and Exit Time 0 ns T SE Sector-Erase ms T SCE Chip-Erase 00 ms T PR Block-Protection Time ms Note: () 0 PGM T0.0 This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 0

12 T RC T AA ADDRESS A MS-0 T CE T OE VIH T OLZ T OHZ TCHZ DQ-0 HIGH-Z TCLZ TOH DATA VALID DATA VALID HIGH-Z Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P; A for SSTSF/VF00P 0 ILL F0.0 FIGURE : READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A MS-0 AAA ADDR T AH T WP T DH T AS T WPH T DS T CH T CS DQ -0 AA A0 DATA SW0 SW SW BYTE (ADDR/DATA) Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P; A for SSTSF/VF00P 0 ILL F0.0 FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

13 INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A MS-0 AAA ADDR T AH T CP T DH T AS T CPH T DS T CH T CS DQ -0 AA A0 DATA SW0 SW SW BYTE (ADDR/DATA) Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P; A for SSTSF/VF00P 0 ILL F0.0 FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS A MS-0 T CE 0 T OEH T OES T OE DQ D D# D# D Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P; A for SSTSF/VF00P 0 ILL F0.0 FIGURE : DATA# POLLING TIMING DIAGRAM

14 ADDRESS A MS-0 T CE TOEH T OE T OES DQ Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P; A for SSTSF/VF00P TWO READ CYCLES WITH SAME OUTPUTS 0 ILL F0.0 FIGURE : TOGGLE BIT TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE TSE ADDRESS AMS-0 AAA AAA SAX TWP DQ-0 AA 0 AA 0 SW0 SW SW SW SW SW Note: This device also supports controlled Sector-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table 0) SA X = Sector Address Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P; A for SSTSF/VF00P 0 ILL F0.0 FIGURE : CONTROLLED SECTOR-ERASE TIMING DIAGRAM

15 SIX-BYTE CODE FOR CHIP-ERASE T SCE ADDRESS A MS-0 AAA AAA T WP DQ-0 AA 0 AA SW0 SW SW SW SW SW FIGURE 0: CONTROLLED CHIP-ERASE TIMING DIAGRAM ADDRESS A -0 0 Note: This device also supports controlled Chip-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table 0) Note: A MS = Most Significant Address A MS = A for SSTSF/VF00P; A for SSTSF/VF00P Three-Byte Sequence for Software ID Entry AAA ILL F.0 0 T IDA T WP DQ -0 T WPH AA 0 T AA BF Device ID SW0 SW SW Note: Device ID = H for SSTSF00P, H for SSTSF00P H for SSTVF00P, H for SSTVF00P 0 ILL F0.0 FIGURE : SOFTWARE ID ENTRY AND READ

16 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A-0 AAA DQ-0 AA F0 TIDA T WP T WHP SW0 SW SW 0 ILL F0.0 FIGURE : SOFTWARE ID EXIT AND RESET Six-Byte Code for Block-Protection T PR ADDRESS A -0 AAA AAA T AH T AS Note T WP T WPH TDS T DH DQ-0 AA 0 AA 0 SW0 SW SW SW SW SW 0 ILL F. Note: Address is AAAH for Top Block-Protection, H for Bottom Block-Protection. FIGURE : BLOCK-PROTECTION

17 ADDRESS A -0 Three-byte sequence for Block-Protection Status AAA T IDA T WP DQ -0 T WPH AA SW0 SW SW T AA Status Status = 0b for Top Block-Protection = 0b for Bottom Block-Protection = 00b for Neither Block-Protection 0 ILL F. FIGURE : BLOCK-PROTECTION STATUS 0

18 VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT AC test inputs are driven at V IHT (.0 V) for a logic and V ILT (0 V) for a logic 0. Measurement reference points for inputs and outputs are at V IT (. V) and V OT (. V) Input rise and fall times (0% «0%) are <0 ns. Note: V IT V INPUT Test V OT V OUTPUT Test V IHT V INPUT HIGH Test V ILT V INPUT LOW Test FIGURE A: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SSTSF00P/00P 0 ILL F. V IHT INPUT V IT REFERENCE POINTS V OT OUTPUT V ILT AC test inputs are driven at V IHT (0. V DD) for a logic and V ILT (0. V DD) for a logic 0. Measurement reference points for inputs and outputs are at V IT (0. V DD) and V OT (0. V DD) Input rise and fall times (0% «0%) are < ns. Note: VIT VINPUT Test VOT VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT LOW Test FIGURE B: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SSTVF00P/00P 0 ILL F. TEST LOAD EXAMPLE FOR SSTSF00P/00P TO TESTER VDD RL HIGH TEST LOAD EXAMPLE FOR SSTVF00P/00P TO DUT TO TESTER CL TO DUT 0 ILL Fb.0 CL RL LOW 0 ILL F. FIGURE : TEST LOAD EXAMPLES

19 Start Load data: AA Load data: Address: AAA Load data: A0 Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 0 0 ILL F.0 FIGURE : BYTE-PROGRAM ALGORITHM

20 Internal Timer Toggle Bit Data# Polling Byte- Program/Erase Initiated Byte- Program/Erase Initiated Byte- Program/Erase Initiated Wait TBP, TSCE, or TSE Read byte Read DQ Program/Erase Completed Read same byte No Is DQ = true data? Yes No Does DQ match? Yes Program/Erase Completed Program/Erase Completed 0 ILL F.0 FIGURE : WAIT OPTIONS 0

21 Software ID Entry Command Sequence Load data: AA Software ID Exit & Reset Command Sequence Load data: AA Load data: F0 Address: XX Load data: Address: AAA Load data: Address: AAA Wait TIDA Load data: 0 Load data: F0 Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 0 ILL F. 0 FIGURE : SOFTWARE ID COMMAND FLOWCHARTS

22 Chip-Erase Command Sequence Load data: AA Sector-Erase Command Sequence Load data: AA Load data: Address: AAA Load data: Address: AAA Load data: 0 Load data: 0 Load data: AA Load data: AA Load data: Address: AAA Load data: Address: AAA Load data: 0 Load data: 0 Address: SAX Wait TSCE Wait TSE Chip erased to FFH Sector erased to FFH 0 ILL F.0 FIGURE 0: ERASE COMMAND SEQUENCE

23 Block-Protection Status Command Sequence Bottom Block-Protection Command Sequence Top Block-Protection Command Sequence Load data: AA Load data: AA Load data: AA Load data: Address: AAA Load data: Address: AAA Load data: Address: AAA Load data: Load data: 0 Load data: 0 Wait TIDA Load data: AA Load data: AA Read Boot Block Status Load data: Address: AAA Load data: Address: AAA Issue Software ID Exit command Load data: 0 Load data: 0 Address: AAA 0 Wait TPR Wait TPR Bottom Block Protected Top Block Protected 0 ILL F0. FIGURE : BLOCK-PROTECTION FLOWCHARTS

24 Device Speed Suffix Suffix SSTxFxxxP - XXX - XX - XX Package Modifier H = pins Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (mm x mm) Temperature Range C = Commercial = 0 to 0 C I = Industrial = -0 to C Minimum Endurance = 0,000 cycles Read Access Speed = ns, = ns 0 = 0 ns, 0 = 0 ns Feature P = Block-Protection Device Density 00 = Megabit 00 = Megabit Voltage S =.-.V V =.-.V

25 SSTSF00P Valid combinations SSTSF00P--C-WH SSTSF00P--C-NH SSTSF00P--C-WH SSTSF00P--C-NH SSTSF00P--C-PH SSTSF00P--I-WH SSTSF00P--I-WH SSTSF00P--I-NH SSTSF00P--I-NH SSTSF00P Valid combinations SSTSF00P--C-WH SSTSF00P--C-NH SSTSF00P--C-WH SSTSF00P--C-NH SSTSF00P--C-PH SSTSF00P--I-WH SSTSF00P--I-WH SSTSF00P--I-NH SSTSF00P--I-NH SSTVF00P Valid combinations SSTVF00P-0-C-WH SSTVF00P-0-C-NH SSTVF00P-0-C-WH SSTVF00P-0-C-NH SSTVF00P-0-I-WH SSTVF00P-0-I-WH SSTVF00P-0-I-NH SSTVF00P-0-I-NH SSTVF00P Valid combinations SSTVF00P-0-C-WH SSTVF00P-0-C-NH SSTVF00P-0-C-WH SSTVF00P-0-C-NH 0 SSTVF00P-0-I-WH SSTVF00P-0-I-WH SSTVF00P-0-I-NH SSTVF00P-0-I-NH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.

26 PACKAGING DIAGRAMS Mbit / Mbit MPF with Block-Protection pin index C L PLCS..0.0 Base Plane Seating Plane BSC BSC 0 Note:. Complies with JEDEC publication MO-0 AP dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches..pdipph-ill. -PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH TOP VIEW SIDE VIEW BOTTOM VIEW Optional Pin # Identifier R. MAX..0 x R BSC BSC..00 BSC Min..0.0 Note:. Complies with JEDEC publication MS-0 AE dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches..plcc.nh-ill. -PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH

27 PIN # IDENTIFIER BSC Note: Complies with JEDEC publication MO- BA dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm. -PIN THIN SMALL OUTLINE PACKAGE (TSOP) MM X MM SST PACKAGE CODE: WH TSOP-WH-ILL. 0

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