512 Kbit / 1 Mbit / 2 Mbit (x8) Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A

Transcription

1 Kbit / Mbit / Mbit (x) Multi-Purpose Flash FEATURES: Organized as K x / K x / K x Single.0V Read and Write Operations Superior Reliability Endurance: 00,000 Cycles (typical) Greater than 00 years Data Retention Low Power Consumption: Active Current: 0 ma (typical) Standby Current: 0 µa (typical) Sector-Erase Capability Uniform KByte sectors Fast Read Access Time: and 0 ns Latched Address and Data PRODUCT DESCRIPTION The SSTSFA/00A/00A are CMOS Multi-Purpose Flash (MPF) manufactured with SST s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SSTSFA/00A/ 00A devices write (Program or Erase) with a.0v power supply. The SSTSFA/00A/00A device conforms to JEDEC standard pinouts for x memories. Featuring high performance Byte-Program, the SSTSFA/00A/00A devices provide a maximum Byte-Program time of 0 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 0,000 cycles. Data retention is rated at greater than 00 years. The SSTSFA/00A/00A devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time Fast Erase and Byte-Program: Sector-Erase Time: ms (typical) Chip-Erase Time: 0 ms (typical) Byte-Program Time: µs (typical) Chip Rewrite Time: seconds (typical) for SSTSFA seconds (typical) for SSTSF00A seconds (typical) for SSTSF00A Automatic Write Timing - Internal V PP Generation End-of-Write Detection Toggle Bit Data# Polling TTL I/O Compatibility JEDEC Standard Flash EEPROM Pinouts and command sets Packages Available -Pin PDIP -Pin PLCC -Pin TSOP (mm x mm) of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SSTSFA/00A/00A are offered in -pin TSOP and -pin PLCC packages. A 00 mil, -pin PDIP is also available. See Figures, and for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting low while keeping low. The address bus is latched on the falling edge of or, whichever occurs last. The data bus is latched on the rising edge of or, whichever occurs first Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc. 0- /00 These specifications are subject to change without notice.

2 Read The Read operation of the SSTSFA/00A/00A is controlled by and, both have to be low for the system to obtain data from the outputs. is used for device selection. When is high, the chip is deselected and only standby power is consumed. is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either or is high. Refer to Figure for the Read cycle timing diagram. Kbit / Mbit / Mbit Multi-Purpose Flash The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (0H) with address H in the last byte sequence. The Erase operation begins with the rising edge of the sixth or, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table for the command sequence, Figure 0 for timing diagram, and Figure for the flowchart. Any commands written during the Chip- Erase operation will be ignored. Byte-Program Operation The SSTSFA/00A/00A are programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either or, whichever occurs last. The data is latched on the rising edge of either or, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth or, whichever occurs first. The Program operation, once initiated, will be completed, within 0 µs. See Figures and for and controlled Program operation timing diagrams and Figure for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of KByte. The Sector-Erase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with Sector-Erase command (0H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth pulse, while the command (0H) is latched on the rising edge of the sixth pulse. The internal Erase operation begins after the sixth pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Chip-Erase Operation The SSTSFA/00A/00A provide Chip-Erase operation, which allows the user to erase the entire memory array to the s state. This is useful when the entire device must be quickly erased. 000 Silicon Storage Technology, Inc. Write Operation Status Detection The SSTSFA/00A/00A provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ ) and Toggle Bit (DQ ). The End-of- Write detection mode is enabled after the rising edge of, which initiates the program or erase cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two () times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ ) When the SSTSFA/00A/00A are in the internal Program operation, any attempt to read DQ will produce the complement of the true data. Once the Program operation is completed, DQ will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ will produce a 0. Once the internal Erase operation is completed, DQ will produce a. The Data# Polling is valid after the rising edge of fourth (or ) pulse for Program Operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth (or ) pulse. See Figure for Data# Polling timing diagram and Figure for a flowchart. Toggle Bit (DQ ) During the internal Program or Erase operation, any consecutive attempts to read DQ will produce alternating 0 s and s, i.e., toggling between 0 and. The Toggle Bit will begin with. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising 0- /00

3 edge of fourth (or ) pulse for Program operation. For Sector- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth (or ) pulse. See Figure for Toggle Bit timing diagram and Figure for a flowchart. Data Protection The SSTSFA/00A/00A provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A or pulse of less than ns will not initiate a Write cycle. V DD Power Up/Down Detection: The write operation is inhibited when V DD is less than.v. Write Inhibit Mode: Forcing low, high, or high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SSTSFA/00A/00A provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SSTSFA/00A/00A devices are shipped with the Software Data Protection permanently enabled. See Table for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within T RC. FUTIONAL BLOCK DIAGRAM Product Identification The product identification mode identifies the device as the SSTSFA, SSTSF00A and SSTSF00A and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SSTSFA/00A/00A. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table for hardware operation or Table for software operation, Figure for the software ID entry and read timing diagram and Figure for the ID entry command sequence flowchart. TABLE : PRODUCT IDENTIFICATION TABLE Address Data Manufacturer s ID 0000H BF H Device ID SSTSFA 000H B H SSTSF00A 000H B H SSTSF00A 000H B H 0 PGM T.0 Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table for software command codes, Figure for timing waveform and Figure for a flowchart. 0 X-Decoder SuperFlash Memory Memory Address Address Buffers & Latches Control Logic Y-Decoder I/O Buffers and Data Latches DQ - DQ0 0 ILL B. 000 Silicon Storage Technology, Inc. 0- /00

4 SSTSF00A SSTSF00A SSTSFA A A A A A A V DD A A A A A A A A A A A A V DD A A A A A A A A A A A A V DD A A A A A A 0 Standard Pinout Top View Die Up 0 0 SSTSFA SSTSF00A SSTSF00A A0 DQ DQ DQ DQ DQ V SS DQ DQ DQ0 A0 A A A A0 DQ DQ DQ DQ DQ V SS DQ DQ DQ0 A0 A A A A0 DQ DQ DQ DQ DQ V SS DQ DQ DQ0 A0 A A A FIGURE : PIN ASSIGNMENTS FOR -PIN TSOP (mm x mm) 0 ILL F0. SSTSF00A SSTSF00A SSTSFA SSTSFA SSTSF00A SSTSF00A A A A A A A A A A A A0 DQ0 DQ DQ VSS A A A A A A A A A A A0 DQ0 DQ DQ VSS A A A A A A A A A A0 DQ0 DQ DQ VSS 0 -Pin PDIP Top View 0 0 V DD A A A A A A0 DQ DQ DQ DQ DQ V DD A A A A A A0 DQ DQ DQ DQ DQ V DD A A A A A A A0 DQ DQ DQ DQ DQ 0 ILL F0a. FIGURE : PIN ASSIGNMENTS FOR -PIN PDIP 000 Silicon Storage Technology, Inc. 0- /00

5 SSTSF00A A A A V DD A SSTSF00A SSTSF00A SSTSFA 0 A A A A A A A A A A A A -Pin PLCC A A A Top View A A A 0 A A A A0 A0 A0 DQ0 DQ0 DQ0 0 FIGURE : PIN ASSIGNMENTS FOR -PIN PLCC SSTSFA SSTSF00A SSTSF00A SSTSFA SSTSF00A A A DQ DQ DQ A A DQ DQ DQ A VSS DQ VSS DQ VSS DQ V DD V DD DQ DQ DQ DQ DQ DQ DQ DQ DQ SSTSFA SSTSF00A SSTSF00A A A A A A A0 DQ A A A A A A0 DQ A A A A A A0 DQ 0 ILL F0b Silicon Storage Technology, Inc. 0- /00

6 TABLE : PIN DESCRIPTION Kbit / Mbit / Mbit Multi-Purpose Flash Symbol Pin Name Functions A MS -A 0 Address Inputs To provide memory addresses. During Sector-Erase A MS -A address lines will select the sector. DQ -DQ 0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when or is high. Chip Enable To activate the device when is low. Output Enable To gate the data output buffers. Write Enable To control the Write operations. V DD Power Supply To provide -volt supply (± 0%) V SS Ground No Connection Unconnected pins. Note: A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A 0 PGM T. TABLE : OPERATION MODES SELECTION Mode A DQ Address Read V IL V IL V IH A IN D OUT A IN Program V IL V IH V IL A IN D IN A IN Erase V IL V IH V IL X X Sector address, XXh for Chip-Erase Standby V IH X X X High Z X Write Inhibit X V IL X X High Z/D OUT X X X V IH X High Z/D OUT X Product Identification Hardware Mode V IL V IL V IH V H Manufacturer ID (BF) Device ID () A () MS - A = V IL, A 0 = V IL A () MS - A = V IL, A 0 = V IH Software Mode V IL V IL V IH A IN ID Code See Table Note: () Device Code = B for SSTSFA, B for SSTSF00A and B for SSTSF00A () A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A 0 PGM T Silicon Storage Technology, Inc. 0- /00

7 TABLE : SOFTWARE COMMAND SEQUEE Command st Bus nd Bus rd Bus th Bus th Bus th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Byte-Program H AAH AAAH H H A0H BA () Data Sector-Erase H AAH AAAH H H 0H H AAH AAAH H SAx () 0H Chip-Erase H AAH AAAH H H 0H H AAH AAAH H H 0H Software ID Entry H AAH AAAH H H 0H Software ID Exit XXH F0H Software ID Exit H AAH AAAH H H F0H 0 PGM T.0 Notes: () Address format A -A 0 (Hex), Address A is a Don t Care for the Command sequence for SSTSFA. Address A and A are "Don't Care" for the Command sequence for SSTSF00A. Address A, A and A are "Don't Care" for the Command sequence for SSTSF00A. () SA x for Sector-Erase; uses A MS-A address lines A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A () BA = Program Byte address () Both Software ID Exit operations are equivalent () With A MS -A =0; SST Manufacturer s ID = BFH, is read with A 0 = 0, SSTSFA Device ID = B H, is read with A 0 =. SSTSF00A Device ID = B H, is read with A 0 =. SSTSF00A Device ID = B H, is read with A 0 =. () The device does not remain in Software Product ID Mode if powered down. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias... - C to + C Storage Temperature... - C to +0 C D. C. Voltage on Any Pin to Ground Potential V to V DD + 0.V Transient Voltage (<0 ns) on Any Pin to Ground Potential V to V DD+.0V Voltage on A Pin to Ground Potential V to.v Package Power Dissipation Capability (Ta = C)....0W Through Hole Lead Soldering Temperature (0 Seconds) C Surface Mount Lead Soldering Temperature ( Seconds)... 0 C Output Short Circuit Current ()... 0 ma Note: () Outputs shorted for no more than one second. No more than one output shorted at a time. 0 OPERATING RANGE Range Ambient Temp V DD Commercial 0 C to +0 C V±0% Industrial -0 C to + C V±0% AC CONDITIONS OF TEST Input Rise/Fall Time... ns Output Load... C L = 0 pf See Figures and 000 Silicon Storage Technology, Inc. 0- /00

8 TABLE : RECOMMENDED SYSTEM POWER-UP TIMINGS Kbit / Mbit / Mbit Multi-Purpose Flash Symbol Parameter Minimum Units T () PU-READ Power-up to Read Operation 00 µs T () PU-WRITE Power-up to Write Operation 00 µs TABLE : DC OPERATING CHARACTERISTICS V DD = V±0% Limits Symbol Parameter Min Max Units Test Conditions I DD Power Supply Current ==V IL, =V IH, all I/Os open, Read 0 ma Address input = V IL/V IH, at f=/t RC Min., V DD =V DD Max Write 0 ma ==V IL, =V IH, V DD =V DD Max. I SB Standby V DD Current ma =V IH, V DD =V DD Max. (TTL input) I SB Standby V DD Current 00 µa =V IHC. (CMOS input) V DD = V DD Max. I LI Input Leakage Current µa V IN =GND to V DD, V DD = V DD Max. I LO Output Leakage Current µa V OUT =GND to V DD, V DD = V DD Max. V IL Input Low Voltage 0. V V DD = V DD Min. V IH Input High Voltage.0 V V DD = V DD Max. V OL Output Low Voltage 0. V I OL =. ma, V DD = V DD Min. V OH Output High Voltage. V I OH = -00µA, V DD = V DD Min. V H Supervoltage for A pin.. V = =V IL, = V IH I H Supervoltage Current 00 µa = = V IL, = V IH, A = V H Max. for A pin 0 PGM T. 0 PGM T.0 TABLE : CAPACITAE (Ta = C, f= Mhz, other pins open) Parameter Description Test Condition Maximum C () I/O I/O Pin Capacitance V I/O = 0V pf C () IN Input Capacitance V IN = 0V pf Note: () 0 PGM T.0 This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE : RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N () END Endurance 0,000 Cycles JEDEC Standard A T () DR Data Retention 00 Years JEDEC Standard A0 V () ZAP_HBM ESD Susceptibility 000 Volts JEDEC Standard A Human Body Model V () ZAP_MM ESD Susceptibility 00 Volts JEDEC Standard A Machine Model I () LTH Latch Up 00 + I DD ma JEDEC Standard Note: () 0 PGM T. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 000 Silicon Storage Technology, Inc. 0- /00

9 AC CHARACTERISTICS TABLE : READ CYCLE TIMING PARAMETERS V DD =.-.V SSTSFA/00A/00A- SSTSFA/00A/00A-0 Symbol Parameter Min Max Min Max Units T RC Read Cycle Time 0 ns T CE Chip Enable Access Time 0 ns T AA Address Access Time 0 ns T OE Output Enable Access Time ns T () CLZ Low to Active Output 0 0 ns T () OLZ Low to Active Output 0 0 ns T () CHZ High to High-Z Output ns T () OHZ High to High-Z Output ns T () OH Output Hold from Address Change 0 0 ns TABLE 0: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units T BP Byte-Program Time 0 µs T AS Address Setup Time 0 ns T AH Address Hold Time 0 ns T CS and Setup Time 0 ns T CH and Hold Time 0 ns T OES High Setup Time 0 ns T OEH High Hold Time 0 ns T CP Pulse Width 0 ns T WP Pulse Width 0 ns T WPH () Pulse Width High 0 ns T CPH () Pulse Width High 0 ns T DS Data Setup Time 0 ns T DH () Data Hold Time 0 ns T IDA () Software ID Access and Exit Time 0 ns T SE Sector-Erase ms T SCE Chip-Erase 00 ms 0 PGM T0.0 Note: () This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 0 PGM T Silicon Storage Technology, Inc. 0- /00

10 T RC T AA ADDRESS A MS-0 T CE T OE VIH T OLZ T OHZ DQ -0 T CHZ T HIGH-Z T OH CLZ HIGH-Z DATA VALID DATA VALID Note: A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A 0 ILL F0.0 FIGURE : READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A MS-0 AAA ADDR T AH T WP T DH T AS T WPH T DS T CH T CS DQ -0 AA A0 DATA SW0 SW SW BYTE (ADDR/DATA) 0 ILL F0.0 Note: A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM 000 Silicon Storage Technology, Inc /00

11 INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 AAA ADDR TAH TCP TDH TAS TCPH TDS DQ -0 T CS TCH AA A0 DATA SW0 SW SW BYTE (ADDR/DATA) 0 ILL F0.0 Note: A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE 0 TOEH TOES TOE DQ D D# D# D FIGURE : DATA# POLLING TIMING DIAGRAM Note: A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A 0 ILL F Silicon Storage Technology, Inc. 0- /00

12 ADDRESS A MS-0 T CE TOEH T OE T OES DQ Note TWO READ CYCLES Note: Toggle bit output is always high first. WITH SAME OUTPUTS A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A 0 ILL F0.0 FIGURE : TOGGLE BIT TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE T SE ADDRESS A MS-0 AAA AAA SA X T WP DQ -0 AA 0 AA 0 SW0 SW SW SW SW SW 0 ILL F0.0 Note: This device also supports controlled Sector-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table 0) SA X = Sector Address A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A FIGURE : CONTROLLED SECTOR-ERASE TIMING DIAGRAM 000 Silicon Storage Technology, Inc. 0- /00

13 ADDRESS A MS-0 SIX-BYTE CODE FOR CHIP-ERASE AAA AAA T SCE T WP DQ -0 AA 0 AA 0 Note: This device also supports controlled Chip-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table 0) SA X = Sector Address A MS = Most significant address A MS = A for SSTSFA, A for SSTSF00A and A for SSTSF00A FIGURE 0: CONTROLLED CHIP-ERASE TIMING DIAGRAM SW0 SW SW SW SW SW 0 ILL F.0 ADDRESS A-0 DQ-0 AAA TWP Three-byte sequence for Software ID Entry TWPH AA 0 SW0 SW SW TIDA TAA BF Device ID 0 Device ID = B for SSTSFA, B for SSTSF00A and B for SSTSF00A 0 ILL F0.0 FIGURE : SOFTWARE ID ENTRY AND READ 000 Silicon Storage Technology, Inc. 0- /00

14 THREE-BYTE SEQUEE FOR SOFTWARE ID EXIT AND RESET ADDRESS A -0 AAA DQ -0 AA F0 T IDA TWP T WHP SW0 SW SW 0 ILL F0.0 FIGURE : SOFTWARE ID EXIT AND RESET 000 Silicon Storage Technology, Inc. 0- /00

15 VIHT VILT INPUT VIT REFEREE POINTS VOT OUTPUT FIGURE : AC INPUT/OUTPUT REFEREE WAVEFORMS 0 ILL F.0 AC test inputs are driven at V IHT (.0 V) for a logic and V ILT (0 V) for a logic 0. Measurement reference points for inputs and outputs are V IT (. V) and V OT (. V). Inputs rise and fall times (0% «0%) are < ns. Note: VIT VINPUT Test VOT VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT LOW Test TEST LOAD EXAMPLE TO TESTER VDD RL HIGH 0 TO DUT CL RL LOW 0 ILL F. FIGURE : A TEST LOAD EXAMPLE 000 Silicon Storage Technology, Inc. 0- /00

16 Start Load data: AA Address: Load data: Address: AAA Load data: A0 Address: Byte Address/Byte Data Wait for end of Program (TBP' Data# Polling bit or Toggle bit operation) Program Completed 0 ILL F.0 FIGURE : BYTE-PROGRAM ALGORITHM 000 Silicon Storage Technology, Inc. 0- /00

17 Internal Timer Program/Erase Initiated Toggle Bit Byte-Program/ Sector Erase Initiated Data# Polling Byte-Program Initiated Wait TBP, TSCE, or TSE Read byte Read DQ Program/Erase Completed Read same byte No Is DQ = true data? Yes No Does DQ match? Write Completed Yes Write Completed 0 0 ILL F.0 FIGURE : WAIT OPTIONS 000 Silicon Storage Technology, Inc. 0- /00

18 Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Load data: AA Address: Load data: AA Address: Load data: F0 Address: XX Load data: Address: AAA Load data: Address: AAA Wait TIDA Load data: 0 Address: Load data: F0 Address: Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 0 ILL F.0 FIGURE : SOFTWARE PRODUCT COMMAND FLOWCHARTS 000 Silicon Storage Technology, Inc. 0- /00

19 Chip-Erase Command Sequence Load data: AA Address: Load data: Address: AAA Load data: 0 Address: Load data: AA Address: Load data: Address: AAA Load data: 0 Address: Wait TSCE Chip-Erase to FFH FIGURE : ERASE COMMAND SEQUEE Sector-Erase Command Sequence Load data: AA Address: Load data: Address: AAA Load data: 0 Address: Load data: AA Address: Load data: Address: AAA Load data: 0 Address: SAX Wait TSE Sector-Erase to FFH 0 ILL F Silicon Storage Technology, Inc. 0- /00

20 Device Speed Suffix Suffix SSTSFxxxA - XXX - XX - XX Kbit / Mbit / Mbit Multi-Purpose Flash Package Modifier H = leads Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (mm x mm) U = Unencapsulated die Temperature Range C = Commercial = 0 to 0 C I = Industrial = -0 to C Minimum Endurance = 0,000 cycles Read Access Speed = ns, 0 = 0 ns Version Device Density = Kilobit 00 = Megabit 00 = Megabit Voltage S =.-.V SSTSFA Valid combinations SSTSFA--C-WH SSTSFA--C-NH SSTSFA-0-C-WH SSTSFA-0-C-NH SSTSFA-0-C-PH SSTSFA-0-C-U SSTSFA--I-WH SSTSFA--I-NH SSTSFA-0-I-WH SSTSFA-0-I-NH SSTSF00A Valid combinations SSTSF00A--C-WH SSTSF00A--C-NH SSTSF00A-0-C-WH SSTSF00A-0-C-NH SSTSF00A-0-C-PH SSTSF00A-0-C-U SSTSF00A--I-WH SSTSF00A--I-NH SSTSF00A-0-I-WH SSTSF00A-0-I-NH SSTSF00A Valid combinations SSTSF00A--C-WH SSTSF00A--C-NH SSTSF00A-0-C-WH SSTSF00A-0-C-NH SSTSF00A-0-C-PH SSTSF00A-0-C-U SSTSF00A--I-WH SSTSF00A--I-NH SSTSF00A-0-I-WH SSTSF00A-0-I-NH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. 000 Silicon Storage Technology, Inc /00

21 PACKAGING DIAGRAMS pin index C L PLCS..0.0 Base Plane Seating Plane.0.00 Note: BSC. Complies with JEDEC publication MO-0 AP dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches BSC 0 -PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH.pdipPH-ILL. TOP VIEW SIDE VIEW BOTTOM VIEW 0 Optional Pin # Identifier R. MAX..0 x R BSC BSC..00 BSC Min..0.0 Note:. Complies with JEDEC publication MS-0 AE dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches..plcc.nh-ill. -PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH 000 Silicon Storage Technology, Inc. 0- /00

22 PIN # IDENTIFIER BSC Note:. Complies with JEDEC publication MO- BA dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm..tsop-wh-ill. -PIN THIN SMALL OUTLINE PACKAGE (TSOP) MM X MM SST PACKAGE CODE: WH Silicon Storage Technology, Inc. Sonora Court Sunnyvale, CA 0 Telephone 0--0 Fax or Literature FaxBack --, International Silicon Storage Technology, Inc. 0- /00