1 Mbit / 2 Mbit / 4 Mbitsn(x8) Many-Time Programmable Flash GLS37VF010 / GLS37VF020 / GLS37VF040

Transcription

1 Mbit / 2 Mbit / 4 Mbitsn(x8) Many-Time Programmable Flash FEATURES: GLS37VF52 / 00 / 020 / V-Read 52Kb / Mb / 2Mb / 4Mb (x8) MTP flash memories Organized as 28K x8 / 256K x8 / 52K x V Read Operation Superior Reliability Endurance: At least 000 Cycles Greater than 00 years Data Retention Low Power Consumption: Active Current: 0 ma (typical) Standby Current: 2 µa (typical) Fast Read Access Time: 70 ns Latched Address and Data Fast Byte-Program Operation: Byte-Program Time: 5 µs (typical) Chip Program Time: 2 seconds (typical) for GLS37VF00 4 seconds (typical) for GLS37VF020 8 seconds (typical) for GLS37VF040 Electrical Erase Using Programmer Does not require UV source Chip-Erase Time: 00 ms (typical) CMOS I/O Compatibility JEDEC Standard Byte-wide Flash EEPROM Pinouts Packages Available 32-lead PLCC 32-lead TSOP (8mm x 4mm) 32-pin PDIP Non-Pb (lead-free) packages available PRODUCT DESCRIPTION The GLS37VF00/020/040 devices are 28K x8 / 256K x8 / 52K x8 CMOS, Many-Time Programmable (MTP), low cost flash, manufactured with high performance Super- Flash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The GLS37VF00/020/040 can be electrically erased and programmed at least 000 times using an external programmer, e.g., to change the contents of devices in inventory. The GLS37VF00/020/040 have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide flash memories. Featuring high performance Byte-Program, the GLS37VF00/020/040 provide a typical Byte-Program time of 5 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 000 cycles. Data retention is rated at greater than 00 years. The GLS37VF00/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the GLS37VF00/020/040 are offered in 32- lead PLCC, 32-lead TSOP, and 32-pin PDIP packages. See Figures 2, 3, and 4 for pin assignments. Device Operation The GLS37VF00/020/040 devices are nonvolatile memory solutions that can be used instead of standard flash devices if in-system programmability is not required. It is functionally (Read) and pin compatible with industry standard flash products.the device supports electrical Erase operation via an external programmer. Read The Read operation of the GLS37VF00/020/040 is controlled by and. Both and have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from to output (T CE ). Data is available at the output after a delay of TOE from the falling edge of, assuming the pin has been low and the addresses have been stable for at least T CE -T OE. When the pin is high, the chip is deselected and a standby current of only 2 µa (typical) is consumed. is the output control and is 200 Greenliant Systems, Ltd. S /0

2 used to gate data from the output pins. The data bus is in high impedance state when either or is V IH. Refer to Figure 5 for the timing diagram. Byte-Program Operation The GLS37VF00/020/040 are programmed by using an external programmer. The programming mode is activated by asserting.4-2v on pin and V IL on pin. The device is programmed using a single pulse ( pin low) of 5 µs per byte. Using the MTP programming algorithm, the Byte-Program process continues byte-by-byte until the entire chip has been programmed. Refer to Figure for the flowchart and Figure 7 for the timing diagram. Chip-Erase Operation The only way to change a data from a 0 to is by electrical erase that changes every bit in the device to. The GLS37VF00/020/040 use an electrical Chip- Erase operation. The entire chip can be erased in 00 ms ( pin low). In order to activate erase mode, the.4-2v is applied to and A 9 pins while is low. All other address and data pins are don t care. The falling edge of will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figure 0 for the flowchart and Figure 6 for the timing diagram. Product Identification Mode The Product Identification mode identifies the devices as GLS37VF00, GLS37VF020, and GLS37VF040 and manufacturer as Greenliant. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force V H (.4-2V) on address A 9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A 0. For details, see Table 3 for hardware operation. TABLE : Product Identification Address Data Manufacturer s ID 0000H BFH Device ID GLS37VF00 000H C5H GLS37VF H C6H GLS37VF H C2H Design Considerations T.2 5 The GLS37VF00/020/040 should have a 0. µf ceramic high frequency, low inductance capacitor connected between V DD and GND. This capacitor should be placed as close to the package terminals as possible. and A 9 must remain stable at V H for the entire duration of an Erase operation. must remain stable at V H for the entire duration of the Program operation. X-Decoder SuperFlash Memory Memory Address Address Buffer Y-Decoder Control Logic I/O Buffers - 5 B. FIGURE : Functional Block Diagram Greenliant Systems, Ltd. S /0

3 GLS37VF040 GLS37VF020 GLS37VF00 GLS37VF00 GLS37VF020 GLS37VF VDD VDD VDD lead PLCC 9 Top View GLS37VF040 GLS37VF020 GLS37VF00 DQ DQ DQ VSS VSS VSS GLS37VF00 GLS37VF020 GLS37VF plc P02a.4 FIGURE 2: Pin Assignments for 32-lead PLCC GLS37VF040 GLS37VF020 GLS37VF V DD V DD V DD Standard Pinout Top View GLS37VF00 GLS37VF020 GLS37VF040 0 V SS DQ 0 V SS DQ 0 V SS DQ 5 32-tsop P0. FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 4mm) 200 Greenliant Systems, Ltd. 3 S /0

4 GLS37VF040 GLS37VF020 GLS37VF00 GLS37VF00 GLS37VF020 GLS37VF DQ VSS DQ VSS DQ VSS pin PDIP Top View VDD VDD VDD FIGURE 4: Pin Assignments for 32-pin PDIP 5 32-pdip P02b.2 TABLE 2: Pin Description Symbol Pin Name Functions A MS -A 0 Address Inputs To provide memory addresses. DQ 7 -DQ 0 Data Input/output To output data during Read cycles and receive input data during Program cycles. The outputs are in tri-state when or is high. Chip Enable To activate the device when is low. Write Enable To program or erase ( = V IL pulse during Program or Erase) Output Enable To gate the data output buffers during Read operation when low V DD Power Supply To provide 3.0V supply ( V) V SS Ground No Connection Unconnected pins.. A MS = Most significant address A MS = A 6 for GLS37VF00, A 7 for GLS37VF020, and A 8 for GLS37VF040 T2. 5 TABLE 3: Operation Modes Selection Mode A 9 DQ Address Read V IL V IH A IN V IL D OUT A IN Output Disable V IL X X V IH High Z A IN Standby V IH X X X High Z X Chip-Erase V IL V IL V H V H High Z X Byte-Program V IL V IL A IN V H D IN A IN Program/Erase Inhibit X V IH X X High Z X X X X V IL or V IH High Z/ D OUT X Product Identification V IL V IH V H V IL Manufacturer s ID (BFH) Device ID. Device ID = C5H for GLS37VF020, C6H for GLS37VF020, and C2H for GLS37VF A MS = Most significant address A MS = A 6 for GLS37VF00, A 7 for GLS37VF020, and A 8 for GLS37VF040 Note: X = V IL or V IH (or V H in case of and A 9 ) V H =.4-2V A MS 2 - A =V IL, A 0 =V IL A MS 2 - A =V IL, A 0 =V IH T Greenliant Systems, Ltd. S /0

5 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias C to +25 C Storage Temperature C to +50 C D. C. Voltage on Any Pin to Ground Potential V to V DD +0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential V to V DD +2.0V Voltage on A 9 Pin to Ground Potential V to 3.2V Package Power Dissipation Capability (T A = 25 C) W Through Hole Lead Soldering Temperature (0 Seconds) C Surface Mount Solder Reflow Temperature: with-pb units : 240 C for 3 seconds non-pb units: 260 C for 3 seconds Output Short Circuit Current ma. Certain with-pb package types are capable of 260 C for 3 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp V DD Commercial 0 C to +70 C V AC CONDITIONS OF TEST Input Rise/Fall Time ns Output Load C L = 00 pf See Figures 8 and 9 TABLE 4: Read Mode DC Operating Characteristics V DD = V (T A = 0 C to +70 C (Commercial)) Limits Symbol Parameter Min Max Units Test Conditions I DD V DD Read Current Address input=v ILT /V IHT, at f=/t RC Min V DD =V DD Max 2 ma =V IL, =V IHT, all I/Os open I SB Standby V DD Current 5 µa =V IHC, V DD =V DD Max I LI Input Leakage Current µa V IN =GND to V DD, V DD =V DD Max I LO Output Leakage Current 0 µa V OUT =GND to V DD, V DD =V DD Max V IL Input Low Voltage 0.8 V V DD =V DD Min V IH Input High Voltage 0.7 V DD V V DD =V DD Max V IHC Input High Voltage (CMOS) V DD -0.3 V V DD =V DD Max V OL Output Low Voltage 0.2 V I OL =00 µa, V DD =V DD Min V OH Output High Voltage V DD -0.3 V I OH =-00 µa, V DD =V DD Min I H Supervoltage Current for A µa ==V IL, A 9 =V H Max T Greenliant Systems, Ltd. 5 S /0

6 TABLE 5: Program/Erase DC Operating Characteristics V DD = V (T A = 25 C±5 C) Limits Symbol Parameter Min Max Units Test Conditions I DD V DD Erase or Program Current 20 ma =V IL, =V H, V DD =V DD Max, =V IL I LI Input Leakage Current µa V IN =GND to V DD, V DD =V DD Max I LO Output Leakage Current 0 µa V OUT =GND to V DD, V DD =V DD Max V H Supervoltage for A 9 and.4 2 V I H Supervoltage Current for A µa =V H Max, A 9 =V H Max, V DD =V DD Max, = V IL I H Supervoltage Current for 3 ma =V IL, =.4-2V, V DD =V DD Max, =V IL T5.2 5 TABLE 6: Recommended System Power-up Timings Symbol Parameter Minimum Units T PU-READ Power-up to Read Operation 00 µs T PU-WRITE Power-up to Write Operation 00 µs. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. T6. 5 TABLE 7: Capacitance (T A = 25 C, f= Mhz, other pins open) Parameter Description Test Condition Maximum C I/O I/O Pin Capacitance V I/O = 0V 2 pf C IN Input Capacitance V IN = 0V 6 pf. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. T7.0 5 TABLE 8: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method N END Endurance 0,000 Cycles JEDEC Standard 7 T DR Data Retention 00 Years JEDEC Standard 03 I LTH Latch Up 00 + I DD ma JEDEC Standard 78. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. T Greenliant Systems, Ltd. S /0

7 AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters V DD = V (T A = 0 C to +70 C (Commercial)) GLS37VF00-70 GLS37VF GLS37VF Symbol Parameter Min Max Units T RC Read Cycle Time 70 ns T CE Chip Enable Access Time 70 ns T AA Address Access Time 70 ns T OE Output Enable Access Time 35 ns T CLZ Low to Active Output 0 ns T OLZ Low to Active Output 0 ns T CHZ High to High-Z Output 25 ns T OHZ High to High-Z Output 25 ns T OH Output Hold from Address Change 0 ns. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. T9.3 5 TABLE 0: Program/Erase Cycle Timing Parameters V DD = V (T A = 25 C±5 C) Symbol Parameter Min Max Units T BP Byte-Program Time 20 µs T CES Setup Time µs T CEH Hold Time µs T AS Address Setup Time µs T AH Address Hold Time µs T DS Data Setup Time µs T DH Data Hold Time µs T PRT Rise Time for Program and Erase 50 ns T VPS Setup Time for Program and Erase µs T VPH Hold Time for Program and Erase µs T PW Program Pulse Width 5 25 µs T EW Erase Pulse Width ms T VR /A 9 Recovery Time for Erase µs T ART A 9 Rise Time to 2V during Erase 50 ns T S A 9 Setup Time during Erase µs T H A 9 Hold Time during Erase µs T Greenliant Systems, Ltd. 7 S /0

8 T RC T AA ADDRESS T CE T OE VIH T OLZ T OHZ -0 HIGH-Z TCLZ TOH DATA VALID TCHZ DATA VALID HIGH-Z 5 F03.0 FIGURE 5: Read Cycle Timing Diagram ADDRESS (EXCEPT ) TCEH -0 VH TVPS VDD VSS TPRT TVPH VH VIH TS TVR VIL TART TH TCES FIGURE 6: Chip-Erase Timing Diagram TEW 5 F Greenliant Systems, Ltd. S /0

9 T PC ADDRESS ADDRESS VALID T AS T AH T CEH T DS TDH DQ 7-0 HIGH-Z DATA VALID VH VDD T VPS T PRT VSS T PW T VPH T CES 5 F05.0 FIGURE 7: Byte-Program Timing Diagram 200 Greenliant Systems, Ltd. 9 S /0

10 V IHT INPUT V IT REFEREE POINTS V OT OUTPUT V ILT 5 F06. AC test inputs are driven at V IHT (0.9 V DD ) for a logic and V ILT (0. V DD ) for a logic 0. Measurement reference points for inputs and outputs are V IT (0.5 V) and V OT (0.5 V DD ). Input rise and fall times (0% 90%) are <5 ns. Note: V IT - V INPUT Test V OT - V OUTPUT Test V IHT - V INPUT HIGH Test V ILT - V INPUT LOW Test FIGURE 8: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 5 F07. FIGURE 9: A Test Load Example Greenliant Systems, Ltd. S /0

11 Start A 9 = V H, = V H = V IL Erase 00ms pulse ( = V IL ) = VIH / = VIL or VIH Wait TVR Recovery Time Read Device Compare all bytes to FF No Yes Device Passed Device Failed 5 F08.0 FIGURE 0: Chip-Erase Algorithm 200 Greenliant Systems, Ltd. S /0

12 Start Erase* = VH Address = First Location; Load Data = VIL Program 5 µs pulse ( = VIL) Increment Address No Last Address? Yes = VIL Wait TVR Read Device Compare all bytes to original data No Yes Device Passed Device Failed 5 F09.2 *See Figure 0 FIGURE : Byte-Program Algorithm Greenliant Systems, Ltd. S /0

13 PRODUCT ORDERING INFORMATION GLS 37 VF C - NH E XX XX XXXX - XXX - XX - XXX X Environmental Attribute E = non-pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type, die up, 8mm x 4mm) Operating Temperature C = Commercial = 0 to +70 C Minimum Endurance 3 =,000 cycles Read Access Speed 70 = 70 ns Device Density 040 = 4 Mbit 020 = 2 Mbit 00 = Mbit Voltage V = V Product Series 37 = Many-Time Programmable Flash Flash memories with flash pinout. Environmental suffix E denotes non-pb solder. Greenliant non-pb solder devices are RoHS Compliant. Valid combinations for GLS37VF00 GLS37VF C-NHE GLS37VF C-WHE GLS37VF C-PHE Valid combinations for GLS37VF020 GLS37VF C-NHE GLS37VF C-WHE GLS37VF C-PHE Valid combinations for GLS37VF040 GLS37VF C-NHE GLS37VF C-WHE GLS37VF C-PHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your Greenliant sales representative to confirm availability of valid combinations and to determine availability of new combinations. * Not recommended for new designs. 200 Greenliant Systems, Ltd. 3 S /0

14 PACKAGING DIAGRAMS TOP VIEW SIDE VIEW BOTTOM VIEW Optional Pin #.447 Identifier R x MAX R BSC BSC.050 BSC Min Note:. Complies with JEDEC publication 95 MS-06 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is.008 inches. 4. Coplanarity: 4 mils. FIGURE 2: 32-lead Plastic Lead Chip Carrier (PLCC) Greenliant Package Code: NH 32-plcc-NH Greenliant Systems, Ltd. S /0

15 Pin # Identifier BSC max. DETAIL Note: Complies with JEDEC publication 95 MO-42 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). mm 3. Coplanarity: 0. mm 4. Maximum allowable mold flash is 0.5 mm at the package ends, and 0.25 mm between leads tsop-WH-7 FIGURE 3: 32-lead Thin Small Outline Package (TSOP) 8mm x 4mm Greenliant Package Code: WH 200 Greenliant Systems, Ltd. 5 S /0

16 32 C L Pin # Identifier PLCS Base Plane Seating Plane BSC BSC 0 5 Note:. Complies with JEDEC publication 95 MO-05 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches. 32-pdip-PH-3 FIGURE 4: 32-pin Plastic Dual In-line Pins (PDIP) Greenliant Package Code: PH Greenliant Systems, Ltd. S /0

17 TABLE : Revision History Number Description Date Data Book Feb Part number changes - see page 3 for additional information Mar 2003 Clarified the Test Conditions for V DD Read Current parameter in Table 4 on page 5 Address input = V ILT /V IHT ==V ILT Data Book Nov 2003 Added non-pb MPNs and removed footnote (See page 3) 05 Removed 90 ns parts, related footnote, and MPNs (See page 3) Added 70 ns parts and MPNs for the PH package Changed Byte-Program time from 0 µs to 5 µs Updated chip program times Separated Supervoltage Current for A 9 and in Table 5 on page 6 06 Added non-pb 32-PDIP MPNs for, 2, and 4 Mbit devices Clarified the solder temperature profile under Absolute Maximum Stress Ratings on page 5 May 2004 Dec Changed program voltage from 2.6V to 2V globally Aug EOLed all valid combinations of SST37VF52, See S75(03). Apr 2007 Removed 64K x 8 organization and leaded parts 09 File name correction Apr Fixed mistake in document status by removing EOL May 2008 Transferred from SST to Greenliant May Greenliant Systems, Ltd. All rights reserved. Greenliant, the Greenliant logo and NANDrive are trademarks of Greenliant Systems, Ltd. All trademarks and registered trademarks are the property of their respective owners. These specifications are subject to change without notice. MTP is a trademark and SuperFlash is a registered trademark of Silicon Storage Technology, Inc., a wholly owned subsidiary of Microchip Technology Inc. 200 Greenliant Systems, Ltd. 7 S /0