PC2700/PC3200 SDRAM Registered DIMM Design Specification Revision 2.2 July 2006

Transcription

1 Page Pin PC2700/PC3200 SDRAM Registered DIMM Design Specification PC2700/PC3200 SDRAM Registered DIMM Design Specification Revision 2.2 July 2006 Release 16 Revision 2.2

2 Page Table of Contents Product Description...3 Environmental Requirements...5 Architecture...5 Component Details...16 DDR SDRAM Component Specifications...16 Register Component Specifications...18 PLL Component Specifications...21 Registered DIMM Details...24 DDR Registered DIMM Design File Releases...25 Component Types and Placement...26 DIMM Wiring Details...33 Signal Groups...33 Differential Clock Net Structures...35 Data Net Structures...41 Address and Control Net Structure...42 Cross Section Recommendations...55 Timing Budget...56 Serial PD Definition...58 Product Label...61 DIMM Mechanical Specifications...62 Supporting Hardware...63 Application Notes...64 Revision Log...65 Revision 2.2 Release 16

3 Page Product Description This specification defines the electrical and mechanical requirements for 184-pin, 2.5 Volt, PC2700/PC3200, 72-bit wide, Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR SDRAM DIMMs).These SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. PC2700/PC3200 refers to the JEDEC standard DIMM naming convention in which PC2700 indicates a DIMM running at 167 MHz clock speed (offering 2,667 MB/s peak bandwidth) and PC3200 indicates a DIMM running at 200 MHz clock speed (offering 3.2 MB/s peak bandwidth). Reference design examples are included which provide an initial basis for Registered DIMM designs. Modifications to these reference designs may be required to meet all system timing, signal integrity, and thermal requirements for PC2700/PC3200 support. All registered DIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. Product Family Attributes DIMM organization DIMM dimensions RAW CARD A, B, C DIMM dimensions RAW CARD D, F, G, H, J DIMM dimensions RAW CARD E DIMM dimensions RAW CARD K, M, N, L x72 ECC 5.25"(nom) x 1.125"(nom) x 0.165"(max); MO-206D, Variation BA "(nom) x 1.20"(nom) x 0.165"(max); MO-206D, Variation CA "(nom) x 1.20"(nom) x 0.272"(max); MO-206D, Variation CB "(nom) x 0.720"(nom) x 0.165"(max); MO-206?, Variation? Pin count 184 SDRAMs supported Capacity 64 Mb, 128 Mb, 256 Mb, 512 Mb, 1 Gb 64 MB, 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB Serial PD Consistent with DDR SPD, Rev 1.0 Voltage options PC2700 (Raw Cards A, B, C, D, E, F) volt (V DD / V DDQ ) Voltage options PC3200 (Raw Cards A, B, C, G, H, J) volt (V DD / V DDQ ) Interface SSTL_2 This document consolidates specification for both PC2700 and PC3200 registered DIMMs. Some of the raw cards in this specification are only running at PC2700, while others run at PC2700 and PC3200. Raw Card Status Raw Card A/K 1 bank x8 B/L 2 bank x 8 C/M 1 bank x4 D/N 2 bank x4 E 2 bank x4 F 2 bank x4 G 1 bank x8 H 2 bank x8 J 1 bank x4 PC2700 X X X X X X PC3200 X X X X X X 1. currently under investigation. Release 16 Revision 2.2

4 Page Environmental Requirements DDR SDRAM Registered DIMMs are intended for use in standard office environments that have limited capacity for heating and air conditioning. Environmental Parameters Symbol Parameter Rating Units Notes T OPR Operating temperature (ambient) 0 to +55 C 1 H OPR Operating humidity (relative) 10 to 90 % 1 T STG Storage temperature -50 to +100 C 1 H STG Storage humidity (without condensation) 5 to 95 % 1 P BAR Barometric pressure (operating & storage) 105 to 69 K Pascal 1, 2 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. Architecture Pin Description Pin Name Description Pin Name Description A0 - A15 SDRAM address bus (A14 and A15 are NC on raw cards in this spec) CK0 SDRAM clock (negative line of differential pair) BA0 - BA1 SDRAM bank select SCL IIC serial bus clock for EEPROM DQ0 - DQ63 DIMM memory data bus SDA IIC serial bus data line for EEPROM CB0 - CB7 DIMM ECC check bits SA0 - SA2 IIC slave address select for EEPROM RAS SDRAM row address strobe V DD SDRAM positive power supply CAS SDRAM column address strobe V DDQ SDRAM I/O Driver positive power supply WE SDRAM write strobe V REF SDRAM I/O reference supply S0 - S3 SDRAM chip select lines (Physical banks 0, 1, 2, and 3) V SS Power supply return (ground) 0-1 SDRAM clock enable lines V Serial EEPROM positive power supply (Supports both 2.5 Volt and 3.3 Volt operation) DDSPD DQS0 - DQS8 SDRAM data strobes NC Spare Pins (no connect) (0-8), DQS(9-17) SDRAM data masks (x8-based x72 DIMMs) SDRAM data strobes (x4-based x72 DIMMs) RESET V DDID VDD Identification Flag FETEN CK0 SDRAM clock (positive line of differential pair) TEST Reset pin (forces register outputs low) External control pin for DIMMs with FET switches in DQ path Used by memory bus analysis tools (unused on memory DIMMs) Revision 2.2 Release 16

5 Page Input/Output Functional Description Symbol Type Polarity Function CK0 CK0 0, 1 S0, S1, S2, S3 RAS, CAS, WE SSTL SSTL SSTL SSTL SSTL Positive Edge Negative Edge Active High Active Low Active Low Positive line of the differential pair of system clock inputs that drives input to the on-dimm PLL. (All DDR SDRAM addr/cntl inputs are sampled on the rising edge of their associated clocks.) Negative line of the differential pair of system clock inputs that drives the input to the on-dimm PLL. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. V REF Supply Reference voltage for SS inputs V DDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity BA0, BA1 SSTL Selects which SDRAM bank of four is activated. A0 - A9, A10/AP, A11 - A15 SSTL During a Bank Activate command cycle, A0-A15 define the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A12 define the column address (CA0-CA12) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge. On Raw cards described in this specification A14 and A15 are NC DQ0 - DQ63, CB0 - CB7 SSTL Data and Check Bit Input/Output pins 0-8 SSTL Active High Masks write data when high, issued concurrently with input data. Both and DQ have a write latency of one clock once the write command is registered into the SDRAM. V DD, V SS Supply Power and ground for the DDR SDRAM input buffers and core logic DQS0-DQS8 SSTL Negative and Positive Edge Data strobe for input and output data. SA0-2 SDA SCL These signals are tied at the system planar to either V SS or V DD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. V DDSPD RESET Supply LV- CMOS FETEN SSTL Active Low TEST NC Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports both 2.3 Volt and 3.3 Volt operation). This signal is asynchronous and driven low to the register to guarantee that the register outputs are Active Low low. This signal is reserved for FET switch DIMMs that may use external control to enable/disable FET pass gates in the DIMM data path. When high, devices are off and in a high impedance state. When low, they are in a low impedance state and data can be read from or written to memory. The TEST pin is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) Release 16 Revision 2.2

6 Page xx 184-Pin DDR SDRAM DIMM Pin Assignments Front Side (left side 1-52, right side 53-92) Pin # x64 2 Non-Parity x72 ECC Pin # Back Side (left side , right side ) x64 2 Non-Parity x72 ECC Front Side (left side 1-52, right side 53-92) Pin # x64 2 Non-Parity x72 ECC Pin # Back Side (left side , right side ) x64 2 Non-Parity x72 ECC 1 V REF V REF 93 V SS V SS 48 A0 A0 140 NC 8,DQS17 2 DQ0 DQ0 94 DQ4 DQ4 49 NC CB2 141 A10 A10 3 V SS V SS 95 DQ5 DQ5 50 V SS V SS 142 NC CB6 4 DQ1 DQ1 96 V DDQ V DDQ 51 NC CB3 143 V DDQ V DDQ 5 DQS0 DQS0 97 0, DQS9 0, DQS9 52 BA1 BA1 144 NC CB7 6 DQ2 DQ2 98 DQ6 DQ6 KEY KEY 7 V DD V DD 99 DQ7 DQ7 53 DQ32 DQ V SS V SS 8 DQ3 DQ3 100 V SS V SS 54 V DDQ V DDQ 146 DQ36 DQ36 9 NC, A15 NC, A NC NC 55 DQ33 DQ DQ37 DQ37 10 RESET RESET 102 NC, TEST 3 NC, TEST 3 56 DQS4 DQS4 148 V DD V DD 11 V SS V SS 103 NC,FETEN NC,FETEN 57 DQ34 DQ ,DQS13 4,DQS13 12 DQ8 DQ8 104 V DDQ V DDQ 58 V SS V SS 150 DQ38 DQ38 13 DQ9 DQ9 105 DQ12 DQ12 59 BA0 BA0 151 DQ39 DQ39 14 DQS1 DQS1 106 DQ13 DQ13 60 DQ35 DQ V SS V SS 15 V DDQ V DDQ 107 1,DQS10 1,DQS10 61 DQ40 DQ DQ44 DQ44 16 NC (CK1) 1 NC (CK1) V DD V DD 62 V DDQ V DDQ 154 RAS RAS 17 NC (CK1) 1 NC (CK1) DQ14 DQ14 63 WE WE 155 DQ45 DQ45 18 V SS V SS 110 DQ15 DQ15 64 DQ41 DQ V DDQ V DDQ 19 DQ10 DQ CAS CAS 157 S0 S0 20 DQ11 DQ V DDQ V DDQ 66 V SS V SS 158 S1 S NC (BA2) NC (BA2) 67 DQS5 DQS ,DQS14 5,DQS14 22 V DDQ V DDQ 114 DQ20 DQ20 68 DQ42 DQ V SS V SS 23 DQ16 DQ NC, A12 NC, A12 69 DQ43 DQ DQ46 DQ46 24 DQ17 DQ V SS V SS 70 V DD V DD 162 DQ47 DQ47 25 DQS2 DQS2 117 DQ21 DQ21 71 NC, S2 NC, S2 163 NC, S3 NC, S3 26 V SS V SS 118 A11 A11 72 DQ48 DQ V DDQ V DDQ 27 A9 A ,DQS11 2,DQS11 73 DQ49 DQ DQ52 DQ52 28 DQ18 DQ V DD V DD 74 V SS V SS 166 DQ53 DQ53 29 A7 A7 121 DQ22 DQ22 75 NC (CK2) 1 NC (CK2) NC, A13 NC, A13 30 V DDQ V DDQ 122 A8 A8 76 NC (CK2) 1 NC (CK2) V DD V DD 31 DQ19 DQ DQ23 DQ23 77 V DDQ V DDQ 169 6,DQS15 6,DQS15 32 A5 A5 124 V SS V SS 78 DQS6 DQS6 170 DQ54 DQ54 NC = No Connect; NU = Not Useable; 1. These pins reserved for unbuffered DDR DIMMs. Systems supporting both unbuffered and registered DIMMs might have active signals connected to those pins. 2. No x64 organized PC2700/PC3200 Registered DIMMs are currently planned 3. The TEST pin is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) Revision 2.2 Release 16

7 Page Pin DDR SDRAM DIMM Pin Assignments Front Side (left side 1-52, right side 53-92) Pin # x64 2 Non-Parity x72 ECC Pin # Back Side (left side , right side ) x64 2 Non-Parity x72 ECC 33 DQ24 DQ A6 A6 79 DQ50 DQ DQ55 DQ55 34 V SS V SS 126 DQ28 DQ28 80 DQ51 DQ V DDQ V DDQ 35 DQ25 DQ DQ29 DQ29 81 V SS V SS 173 NC, A14 NC, A14 36 DQS3 DQS3 128 V DDQ V DDQ 82 V DDID V DDID 174 DQ60 DQ60 37 A4 A ,DQS12 3,DQS12 83 DQ56 DQ DQ61 DQ61 38 V DD V DD 130 A3 A3 84 DQ57 DQ V SS V SS 39 DQ26 DQ DQ30 DQ30 85 V DD V DD 177 7,DQS16 7,DQS16 40 DQ27 DQ V SS V SS 86 DQS7 DQS7 178 DQ62 DQ62 41 A2 A2 133 DQ31 DQ31 87 DQ58 DQ DQ63 DQ63 42 V SS V SS 134 NC CB4 88 DQ59 DQ V DDQ V DDQ 43 A1 A1 135 NC CB5 89 V SS V SS 181 SA0 SA0 44 NC CB0 136 V DDQ V DDQ 90 NU NU 182 SA1 SA1 45 NC CB1 137 CK0 CK0 91 SDA SDA 183 SA2 SA2 46 V DD V DD 138 CK0 CK0 92 SCL SCL 184 V DDSPD V DDSPD 47 NC DQS8 139 V SS V SS Front Side (left side 1-52, right side 53-92) Pin # x64 2 Non-Parity x72 ECC Pin # Back Side (left side , right side ) x64 2 Non-Parity NC = No Connect; NU = Not Useable; 1. These pins reserved for unbuffered DDR DIMMs. Systems supporting both unbuffered and registered DIMMs might have active signals connected to those pins. 2. No x64 organized PC2700/PC3200 Registered DIMMs are currently planned 3. The TEST pin is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) x72 ECC Release 16 Revision 2.2

8 Page this is achor for Axxx Block Diagram: Raw Card Version A, G, K:(x72 DIMM, populated as one bank of x8 DDR SDRAMs) RS0 DQS0 0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 4 I/O 5 I/O 6 I/O 7 D0 DQS DQS4 4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS DQS1 1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 4 I/O 5 I/O 6 I/O 7 D1 DQS DQS5 5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 4 I/O 5 I/O 6 I/O 7 D5 DQS DQS2 2/DQS11 DQS3 3/DQS12 DQS8 8/DQS17 S0 BA0-BA1 A0-A13 RAS CAS WE PCK PCK DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 R E G I S T E R I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 D2 D3 D8 DQS DQS DQS DQS6 6/DQS15 DQS7 7/DQS16 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQS DQS D7 I/O 4 I/O 5 I/O 6 I/O 7 VDDSPD Serial PD VDDQ D0- D8 VDD D0-D8 VREF D0-D8 VSS D0-D8 VDDID Strap: see Note 4 Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS///S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 ohms. 4. V DDID strap connections (for memory device V DD, V DDQ ): STRAP OUT (OPEN): V DD = V DDQ STRAP IN (V SS ): V DD V DDQ. 5. SDRAM placement alternates between the back and front sides of the DIMM. CK0, CK PLL* 6. Address and control resistors should be 22 ohms. * Wire per Clock Loading Table/Wiring Diagrams RS0 : SDRAMs D0-D8 RBA0-RBA1 BA0-BA1: SDRAMs D0-D8 RA0-RA13 A0-A13: SDRAMs D0-D8 RRAS RAS: SDRAMs D0-D8 RCAS CAS: SDRAMs D0-D8 R0 : SDRAMs D0- D8 RWE WE: SDRAMs D0-D8 RESET SCL WP A0 Serial PD A1 A2 SA0 SA1 SA2 SDA Revision 2.2 Release 16

9 Page This is anchor for Bxx Block Diagram: Raw Card Version B, H and L (x72 DIMM, populated as two physical banks of x8 DDR SDRAMs) RS1 RS0 DQS0 0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 4/DQS13 DQS DQS DQS DQS DQ32 D0 D9 DQ33 D4 D13 DQ34 I/O 4 I/O 5 I/O 6 I/O 7 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 5/DQS14 DQS DQS DQS DQ40 D1 D10 DQ41 D5 D14 DQ42 I/O 4 I/O 5 I/O 6 I/O 7 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS2 2/DQS11 DQS3 3/DQS12 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 8/DQS17 S0 S1 BA0-BA1 A0-A13 RAS CAS 0 1 WE PCK PCK CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 R E G I S T E R I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 D2 D3 DQS DQS I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 D11 D12 DQS DQS DQS6 6/DQS15 DQS7 7 DQS16 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 D6 D7 DQS DQS I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS VDDSPD D8 Serial PD D17 Serial PD VDDQ D0-D17 SCL SDA VDD D0-D17 I/O 4 I/O 4 WP A0 A1 A2 I/O 5 I/O 5 VREF D0-D17 SA0 SA1 SA2 I/O 6 I/O 6 VSS D0-D17 I/O 7 I/O 7 VDDID Strap: see Note 4 RS0 : SDRAMs D0-D8 CK0, CK PLL* RS1 : SDRAMs D9-D17 * Wire per Clock Loading Table/Wiring Diagrams RBA0-RBA1 BA0-BA1: SDRAMs D0-D17 RA0-RA13 A0-A13: SDRAMs D0-D17 Notes: RRAS RAS: SDRAMs D0-D17 1. DQ-to-I/O wiring may be changed within a byte. RCAS CAS: SDRAMs D0-D17 2. DQ/DQS///S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 ohms. R0 : SDRAMs D0-D8 4. V DDID strap connections (for memory device V DD, V DDQ ): R1 : SDRAMs D9-D17 STRAP OUT (OPEN): V DD = V RWE WE: SDRAMs D0-D17 DDQ STRAP IN (V SS ): V DD V DDQ. RESET 5. RS0 and RS1 alternate between the back and front sides of the DIMM. 6. Address and control resistors should be 22 ohms. D15 D16 DQS DQS Release 16 Revision 2.2

10 Page anchor for C: xxxx Block Diagram: Raw Card Version C, J, M (Populated as one physical bank of x4 DDR SDRAMs) VSS RS0 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQ0 DQ1 DQ2 DQ3 DQ8 DQ9 DQ10 DQ11 DQ16 DQ17 DQ18 DQ19 DQ24 DQ25 DQ26 DQ27 DQ32 DQ33 DQ34 DQ35 DQ40 DQ41 DQ42 DQ43 DQ48 DQ49 DQ50 DQ51 DQ56 DQ57 DQ58 DQ59 CB0 CB1 CB2 CB3 S0 BA0-BA1 A0-A13 RAS CAS WE PCK PCK R E G I S T E R DQS DQS DQS DQS DQS DQS DQS DQS DQS D0 D1 D2 D3 D4 D5 D6 D7 D8 0/DQS9 1/DQS10 DQ4 DQ5 DQ6 DQ7 DQ12 DQ13 DQ14 DQ15 2/DQS11 DQ20 DQ21 DQ22 DQ23 3/DQS12 4/DQS13 5/DQS14 6/DQS15 DQ28 DQ29 DQ30 DQ31 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 DQ46 DQ47 DQ52 DQ53 DQ54 DQ55 7/DQS16 DQ60 DQ61 DQ62 DQ63 8/DQS17 CB4 CB5 CB6 CB7 DQS D9 DQS DQS DQS DQS DQS DQS D10 D11 D12 D13 D14 DQS D15 DQS D16 D17 VDDSPD VDDQ VDD VREF VSS RS : SDRAMs D0-D17 RBA0-RBA1 BA0-BA1: SDRAMs D0-D17 RA0-RA13 A0-A13: SDRAMs D0-D17 RRAS RAS: SDRAMs D0-D17 RCAS CAS: SDRAMs D0-D17 RA : SDRAMs D0-D17 RWE WE: SDRAMs D0-D17 CK0, CK PLL* RESET * Wire per Clock Loading Table/Wiring Diagrams D0-D17 D0-D17 D0-D17 D0-D17 VDDID Strap: see Note 4 SCL WP A0 Serial PD A1 A2 SA0 SA1 SA2 Serial PD SDA Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS///S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 ohms. 4. V DDID strap connections (for memory device V DD, V DDQ ): STRAP OUT (OPEN): V DD = V DDQ STRAP IN (V SS ): V DD V DDQ. 5. Address and control resistors should be 22 ohms. Revision 2.2 Release 16

11 Page anchor for D: xxxx Block Diagram: Raw Card Version D, F, N (Populated as two physical bank of x4 DDR SDRAMs) RS0 R0 RS1 DQS00 DQ00 DQ01 DQ02 DQ03 DQS01 DQ08 DQ09 DQ10 DQ11 DQS10 DQ12 DQ13 DQ14 DQ15 DQS09 DQ04 DQ05 DQ06 DQ07 DQS11 DQ20 DQ21 DQ22 DQ23 DQS02 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS17 CB04 CB05 CB06 CB07 DQS12 DQ28 DQ29 DQ30 DQ31 R1 DQS U04 DQS U12 DQS U08 DQS U16 DQS U24 DQS U28 DQS DQS U00 DQS U20 U32 S0 S1 BA0-BA1 A0-A13 RAS CAS 0 1 WE PCK PCK U06 U02 R E G I S T E R S U14 U10 U22 U18 U26 U30 U34 DQS07 DQ56 DQ57 DQ58 DQ59 DQS06 DQ48 DQ49 DQ50 DQ51 DQS15 DQ52 DQ53 DQ54 DQ55 DQS16 DQ60 DQ61 DQ62 DQ63 DQS14 DQ44 DQ45 DQ46 DQ47 DQS05 DQ40 DQ41 DQ42 DQ43 DQS04 DQ32 DQ33 DQ34 DQ35 DQS08 CB00 CB01 CB02 CB03 DQS13 DQ36 DQ37 DQ38 DQ39 DQS U05 DQS U01 DQS U09 DQS U21 DQS U28 DQS U13 DQS U33 U07 U03 U11 U23 U15 U31 DQS U19 U17 DQS U25 U27 U35 VDDSPD VDDQ VDD VREF VSS Serial PD U00-U36 U00-U36 U00-U36 U00-U36 VDDID Strap: see Note 4 Serial PD Notes: 1. DQ-to-I/O wiring may be changed withina byte. 2. DQ/DQS///S relationships mustbe maintained as shown. 3. DQ/DQS resistors should be 18 ohms. 4. V DDID strap connections - (for memory device V DD, V DDQ ): STRAP OUT (OPEN): V DD = V DDQ STRAP IN (V SS ): V DD V DDQ. 5. Address and control resistors should be- 22 ohms. RS0 : SDRAMs U00.U02... U34 RS1 : SDRAMs U01.U03... U35 RBA0-RBA1 BA0-BA1: SDRAMs U00-U35 RA0-RA13 A0-A13: SDRAMs U00-U35 RRAS RAS: SDRAMs U00-U35 RCAS CAS: SDRAMs U00 - U35 R0 : SDRAMs U00, U02, U04... U34 R1 : SDRAMs U01, U03, U05... U35 RWE WE: SDRAMs U00-U35 CK0, CK PLL* RESET * Wire per Clock Loading Table/Wiring Diagrams SCL WP A0 A1 A2 SA0 SA1 SA2 SDA Release 16 Revision 2.2

12 Page anchor for D: xxxx Block Diagram: Raw Card Version E (Populated as two physical bank of x4 DDR Stacked SDRAMs) RS0 R0 RS1 DQS00 DQ00 DQ01 DQ02 DQ03 DQS01 DQ08 DQ09 DQ10 DQ11 DQS10 DQ12 DQ13 DQ14 DQ15 DQS09 DQ04 DQ05 DQ06 DQ07 DQS11 DQ20 DQ21 DQ22 DQ23 DQS02 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS17 CB04 CB05 CB06 CB07 DQS12 DQ28 DQ29 DQ30 DQ31 R1 DQS DQS DQS DQS DQS DQS U05 DQS U06 DQS DQS U15 U14 U16 U07 U08 U18 U17 S0 S1 BA0-BA1 A0-A13 RAS CAS 0 1 WE PCK PCK R E G I S T E R S DQS07 DQ56 DQ57 DQ58 DQ59 DQS06 DQ48 DQ49 DQ50 DQ51 DQS15 DQ52 DQ53 DQ54 DQ55 DQS16 DQ60 DQ61 DQ62 DQ63 DQS14 DQ44 DQ45 DQ46 DQ47 DQS05 DQ40 DQ41 DQ42 DQ43 DQS04 DQ32 DQ33 DQ34 DQ35 DQS08 CB00 CB01 CB02 CB03 DQS13 DQ36 DQ37 DQ38 DQ39 DQS DQS DQS DQS DQS DQS DQS U13 DQS DQS U12 U21 U22 U20 U11 U10 U09 U19 VDDSPD VDDQ VDD VREF VSS Serial PD U05-U22 U05-U22 U05-U22 U05-U22 VDDID Strap: see Note 4 Serial PD Notes: 1. DQ-to-I/O wiring may be changed withina byte. 2. DQ/DQS///S relationships mustbe maintained as shown. 3. DQ/DQS resistors should be 22 ohms. 4. V DDID strap connections - (for memory device V DD, V DDQ ): STRAP OUT (OPEN): V DD = V DDQ STRAP IN (V SS ): V DD V DDQ. 5. Address and control resistors should be- 22 ohms. RS0 : SDRAMs U05-U22 RS1 : SDRAMs U05-U22 RBA0-RBA1 BA0-BA1: SDRAMs U05-U22 RA0-RA13 A0-A13: SDRAMs U02-U22 RRAS RAS: SDRAMs U05-U22 RCAS CAS: SDRAMs U05 - U22 R0 : SDRAMs U05-U22 R1 : SDRAMs U05-U22 RWE WE: SDRAMs U05-U22 CK0, CK PLL* RESET * Wire per Clock Loading Table/Wiring Diagrams SCL WP A0 A1 A2 SA0 SA1 SA2 SDA Revision 2.2 Release 16

13 Page jhhx Differential Clock Net Wiring (CK0, CK0) 0ns (nominal) PLL SDRAM OUT1 120Ω CK0 120Ω IN SDRAM CK0 (Typically two registers per DIMM) Reg Ω OUT N C 120Ω C Feedback Reg The clock delay from the input of the PLL clock to the input of any SDRAM or register will be set to 0ns (nominal), with the exception of raw cards G, H and J. See Clocking Timing Methodology on page Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible. Release 16 Revision 2.2

14 Page Register Functional Assignments Raw Card Versions A (Two 1:1 Registers) Raw Card Versions B, C, D, E, F (Two 1:2 Registers) Register 1 Register 2 Register 1 Register 2 In Out In Out In Out In Out A1 RA1 A0 RA0 RA1A RA0A A1 A0 A2 RA2 A10 RA10 RA1B RA0B A3 RA3 S0 RS0 RA2A RA10A A2 A10 A4 RA4 A13 2 RA13 RA2B RA10B A5 RA5 CAS RCAS RA3A RS0A A3 S0 A6 RA6 RAS RRAS RA3B RS0B A7 RA7 BA0 RBA0 RA4A RS1A A8 RA8 BA1 RBA1 A4 RA4B S1 3 RS1B A9 RA9 WE RWE RA5A RCASA A5 CAS A11 RA11 RA5B RCASB A12 1 RA12 RA6A RRASA A6 RAS 0 R0 RA6B RRASB A7 RA7A RA7B BA0 RBA0A RBA0B A8 RA8A RA8B BA1 RBA1A RBA1B A9 RA9A RA9B WE RWEA RWEB A11 RA11A RA11B A13 2 RA13A RA13B A12 1 RA12A RA12B 0 R0A R0B 1 3 R1A R1B 1. Only used with 256Mbit, 512Mbit and 1 Gbit SDRAMs. 2. Only used with 1 Gbit SDRAMs. 3. R/C B, D, E, F only Revision 2.2 Release 16

15 Page Component Details DDR SDRAM Component Specifications The DDR SDRAM components used with this DIMM design specification are intended to be consistent with JEDEC Standard JESD-21C and JESD-79 (DDR333 parameter set for PC2700 and DDR400 parameter set for PC3200). DDR SDRAM component specification violations also violate the DDR SDRAM Registered DIMM specifications. DDR SDRAM BGA Components (60 pin TFBGA, 12 x 9 array, 1.00 mm x 0.80 mm pitch, MO-233 Variation AA;68 pin TFBGA: 16 x 9 array, 1.00 mm x 0.80 mm pitch: MO-233 Variation AC (with support balls) Raw Card Supported DRAM Outline (width x length) max. MO-233 Variation supported # balls A, B, C, G, H, J 10.0 mm x 18.0 mm AA, AC 60/68 D 8.0 mm x 14.0 mm AA 60 E 12.0 ( ) mm x 21.9 mm tbd 62/70 F,K, M, N, L 10.0 mm x 12.0 mm AA supported only if no de-coupling capacitors are placed in between the DRAMs Ball Assignments for 64 Mb, 128 Mb, 256 Mb, 512 Mb and 1 Gb Top View (for reference only, numbering applies to Variation AA) max. width A B C D E F G H for stacked only J K L M 1.0 mm 0.8 mm max. length Note: dotted circles indicate the location of support balls which might be present on large devices; R/C s A, B, C and E have landing pads for these support balls; R/C D and F do not. Release 16 Revision 2.2

16 Page x8 Ballout for 64 Mb, 128 Mb, 256 Mb, 512 Mb and 1 Gb DDR SDRAMs (Top View) VSSQ DQ7 VSS A VDD DQ0 VDDQ NC VDDQ DQ6 B DQ1 VSSQ NC NC VSSQ DQ5 C DQ2 VDDQ NC NC VDDQ DQ4 D DQ3 VSSQ NC NC VSSQ DQS E NC VDDQ NC VREF VSS F NC VDD A13, NC CK CK G WE CAS A12, NC H RAS A11 A9 J BA1 BA0 A8 A7 K A0 A10 / AP A6 A5 L A2 A1 A4 VSS M VDD A3 x4 Ballout for 64 Mb, 128 Mb, 256 Mb, 512 Mb and 1 Gb DDR SDRAMs (Top View) (NB = no ball) VSSQ NC VSS A VDD NC VDDQ NC VDDQ DQ3 B DQ0 VSSQ NC NC VSSQ NC C NC VDDQ NC NC VDDQ DQ2 D DQ1 VSSQ NC NC VSSQ DQS E NC VDDQ NC VREF VSS F NC VDD A13, NC NB, 1 CK CK G WE CAS NB, 1 A12, NC, 0 H RAS, 0 A11 A9 J BA1 BA0 A8 A7 K A0 A10 / AP A6 A5 L A2 A1 A4 VSS M VDD A3 Revision 2.2 Release 16

17 Page Register Component Specifications Please refer to the vendor register data sheets for all technical specifications and requirements. DIMM Register Use Raw Card Version # of Banks # of SDRAMs per output Register Type Register Package Register Speed Grade PC2700 Register Speed Grade PC3200 Quantity A 1 9 1:1 14-bit TSSOP 1 SSTV SSTVN 2 B 2 8 / 10 1:2 13-bit TSSOP 2 SSTV, SSTVN SSTVN 2 C 1 8 / 10 1:2 13-bit TSSOP 2 SSTV, SSTVN SSTVN 2 D :2 13-bit VFQFP 3 SSTVM N/A 4 2 E 2 16 / 20 1:2 13-bit VFQFP 3 SSTVM N/A 4 2 F :2 13-bit VFQFP 3 SSTVM N/A 4 2 G 1 9 1:2 13-bit VFQFP 3 SSTVF SSTVF 2 H 2 8 / 10 1:2 13-bit VFQFP 3 SSTVF SSTVF 2 J 1 8 / 10 1:2 13-bit VFQFP 3 SSTVF SSTVF 2 K 1 9 1:2 13-bit VFQFP3 SSTV SSTVF 2 M 1 8/10 1:2 13-bit VFQFP3 SSTV SSTVF 2 N :2 13-bit VFQFP3 SSTV SSTVF 2 L 2 8 / 10 1:2 13-bit VFQFP3 SSTV SSTVF 2 1. The reference design uses registers in 48-pin TSSOP (MO-153 Variation ED) 2. The reference designs use registers in 64-pin TSSOP (MO-153 Variation EF) 3. The reference designs use registers in 56-pin VFQFP(MLF2) (MO-220 Variation VLLD-2 ) 4. currently under investigation The following specifications for the register are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the device. Detailed information on the registers may be found in JESD82-3B (1:1) and JESD82-4C (1:2). Release 16 Revision 2.2

18 Page Critical Register Specifications for PC2700 Register Symbol Parameter Conditions T A = 0-70 C V DD = 2.5V ± 0.2V t CK Clock Frequency MHz t PD t PDSS Clock to Output Time Clock to Output Time (one or all switching) 30 pf to GND and 50 ohms to V DD /2 30pF to GND, 1K to GND, 1K to VDD Min Max Units SSTV ns SSTVM, SSTVN ns SSTVF (VFQFP) ns t SS SSO adder to t PD all outputs switching 0.3 ns t RST Reset to Output Time 5 ns 1:1 14-bit and 1:2 13-bit t SL t SL Output Slew Rate Output Slew Rate 30 pf to GND and 50 ohms to V DD /2 30pF to GND, 1K to GND, 1K to VDD t SU Setup time, fast slew rate see notes 1 and 3 SSTV, SSTVM, SSTVN V/ns SSTVF (VFQFP) V/ns SSTV 0.75 SSTVM, SSTVN, SSTVF 0.65 SSTV 0.9 Setup time, slow slew rate see notes 2 and 3 SSTVM, SSTVN 0.8 ns SSTVF 0.75 t H Hold time, fast slew rate see notes 1 and Hold time, slow slew rate see notes 2 and C IN(CK) Clock Input Capacitance pf ns C IN(data ) Data Input Capacitance pf 1. For data signal, input slew rate > 1 V/ns. 2. For data signal, input slew rate > 0.5 V/ns and < 1V/ns. 3. For CK and CK signals, input slew rates are > 1 V/ns Revision 2.2 Release 16

19 Page Critical Register Specifications for PC3200 Register Symbol Parameter Conditions T A = 0-70 C V DD = 2.6V ± 0.1V t CK Clock Frequency MHz Min Max Units t PD Clock to Output Time 30 pf to GND and 50 ohms to V DD /2 SSTVN (TSSOP) ns t PDSS Clock to Output Time (one or all switching) 30pF to GND, 1K to GND, 1K to VDD SSTVF (VFQFP) ns t SS SSO adder to t PD all outputs switching SSTVN (TSSOP) 0.3 ns t RST Reset to Output Time 5 ns 1:1 14-bit and 1:2 13-bit t SL t SL Output Slew Rate Output Slew Rate 30 pf to GND and 50 ohms to V DD /2 30pF to GND, 1K to GND, 1K to VDD SSTVN (TSSOP) V/ns SSTVF (VFQFP) V/ns t SU Setup time, fast slew rate see notes 1 and ns Setup time, slow slew rate see notes 2 and ns t H Hold time, fast slew rate see notes 1 and Hold time, slow slew rate see notes 2 and C IN(CK) Clock Input Capacitance pf Register Sourcing C IN(data ) Data Input Capacitance pf 1. For data signal, input slew rate > 1 V/ns. 2. For data signal, input slew rate > 0.5 V/ns and < 1V/ns. 3. For CK and CK signals, input slew rates are > 1 V/ns ns for SSTVN ns for SSTVN This document is not intended to be an approved vendor list for support chip components. Although it is recommended that all DDR SDRAM RDIMM registers meet the specifications documented above, it is up to each DIMM producer to select the registers and register vendors which meet these requirements, and to guarantee robustly designed DIMMs. Release 16 Revision 2.2

20 Page PLL Component Specifications Please refer to the vendor PLL data sheets for all technical specifications and requirements. Below is a chart explaining which PLLs are used on each DIMM type. DIMM PLL Use Raw Card # of Banks PLL Type # of SDRAMs per output Package PC2700 PC3200 Quantity A 1 1:10 1 TSSOP 1 CV857, CVF857 CVF857 1 B 2 1:10 2 TSSOP 1 CV857, CVF857 CVF857 1 C 1 1:10 2 TSSOP 1 CV857, CVF857 CVF857 1 D 2 1:10 4 TSSOP 1 CV857, CVF857 N/A 3 1 E 2 1:10 2 stacks VFQFP 2 CVF857 N/A 3 1 F 2 1:10 4 VFQFP 2 CVF857 N/A 3 1 G 1 1:10 1 VFQFP 2 CVF857 CVF857 1 H 2 1:10 2 VFQFP 2 CVF857 CVF857 1 J 1 1:10 2 VFQFP 2 CVF857 CVF857 1 K 1 1:10 1 VFQFP2 CVF857 CVF857 1 M 1 1:10 2 VFQFP2 CVF857 CVF857 1 N 1 1:10 4 VFQFP2 CVF857 CVF857 1 L 2 1:10 2 VFQFP2 CVF857 CVF The reference design uses a PLL in 48-pin TSSOP (MO-153 Variation ED) 2. The reference design uses a PLL in 40-pin VFQFP (MLF2) (MO-220 Variation VJJD-2 with E2 = D2 = 2.9 +/-0.15 mm) 3. currently under investigation The following specifications for the PLL are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the device. Detailed information on this part, including driver characteristics, may be found in JESD82-1 and JESD82-1A. Revision 2.2 Release 16

21 Page Critical PLL Specifications for PC2700 Device Symbol Parameter Conditions T A = 0-70 C V DD = 2.5 V ± 0.2 V Units Notes Min Max f CK Operating Clock Frequency MHz 1 f CK Application Clock Frequency MHz 1 t SPE Static Phase Error Application Load ps 2 t SK Output Clock Skew Application Load 100 ps 2 1:10, 2.5 volt t SL Output Slew Rate 1 3 V/ns 2 t JIT (per) Period 3, 4 t JIT (cc) Cycle-to-Cycle ps t JIT (hper) Half-period t STAB PLL Stabilization Time 100 μs C IN Input Capacitance pf 1. The PLL used on the registered DIMM needs to support SSC synthesizers with a Modulation Frequency of 30 to 50 khz and a Clock Frequency Deviation of -0.5%. PLL designs should target the following values: Greater than 1.2 MHz PLL loop bandwidth Less than degrees of phase angle 2. The application load is defined in Differential Clock Net Structures on page Period jitter defines the largest variation in clock period, around a nominal clock period. 4. Period jitter and half-period jitter are independent from each other. Critical PLL Specifications for PC3200 Device Symbol Parameter Conditions T A = 0-70 C V DD = 2.6 V ± 0.1 V Units Notes Min Max f CK Operating Clock Frequency MHz 1 f CK Application Clock Frequency MHz 1 t SPE Static Phase Error Application Load ps 2 t SK Output Clock Skew Application Load 100 ps 2 1:10, 2.5 volt t SL Output Slew Rate 1 3 V/ns 2 t JIT (per) Period ps 3, 4 t JIT (cc) Cycle-to-Cycle ps t JIT (hper) Half-period ps 4 t STAB PLL Stabilization Time 100 μs C IN Input Capacitance pf 1. The PLL used on the registered DIMM needs to support SSC synthesizers with a Modulation Frequency of 30 to 50 khz and a Clock Frequency Deviation of -0.5%. PLL designs should target the following values: Greater than 1.2 MHz PLL loop bandwidth Less than degrees of phase angle 2. The application load is defined in Differential Clock Net Structures on page Period jitter defines the largest variation in clock period, around a nominal clock period. 4. Period jitter and half-period jitter are independent from each other. Release 16 Revision 2.2

22 Page PLL Sourcing This document is not intended to be an approved vendor list for support chip components. Although it is recommended that all DDR SDRAM Registered DIMM PLLs meet the specifications documented above, it is up to each DIMM producer to select the PLL and PLL vendors which meet these requirements, and to guarantee robustly operating DIMMs. Revision 2.2 Release 16

23 Page Registered DIMM Details DDR SDRAM Module Configurations (Reference Designs) (Page 1 of 2) Raw Card Version DIMM SDRAM Capacity Organization Density Organization # of SDRAMs SDRAM Package Type # of Physical Banks # of Banks in SDRAM # of Address bits row/col 64 MB 8Mx72 64 Mbit 8Mx / 68 ball BGA /9 128 MB 16Mx Mbit 16Mx / 68 ball BGA /10 A, G 256 MB 32Mx Mbit 32Mx / 68 ball BGA / MB 64Mx Mbit 64Mx / 68 ball BGA /11 1 GB 128Mx72 1 Gbit 128Mx / 68 ball BGA / MB 16Mx72 64 Mbit 8Mx / 68 ball BGA /9 256 MB 32Mx Mbit 16Mx / 68 ball BGA /10 B, H 512 MB 64Mx Mbit 32Mx / 68 ball BGA /10 1 GB 128Mx Mbit 64Mx / 68 ball BGA /11 2 GB 256Mx72 1 Gbit 128Mx / 68 ball BGA / MB 16Mx72 64 Mbit 16Mx / 68 ball BGA / MB 32Mx Mbit 32Mx / 68 ball BGA /11 C, J 512 MB 64Mx Mbit 64Mx / 68 ball BGA /11 1 GB 128Mx Mbit 128Mx / 68 ball BGA /12 2 GB 256Mx72 1 Gbit 256Mx / 68 ball BGA / MB 16Mx72 64 Mbit 16Mx ball BGA / MB 32Mx Mbit 32Mx ball BGA /11 D 1 GB 64Mx Mbit 64Mx ball BGA /11 2 GB 128Mx Mbit 128Mx ball BGA /11 4 GB 256Mx72 1 Gbit 256Mx ball BGA / MB 16Mx72 64 Mbit 2x16Mx / 70ball BGA / MB 32Mx Mbit 2x32Mx / 70ball BGA /11 E 1 GB 64Mx Mbit 2x64Mx / 70ball BGA /11 2 GB 128Mx Mbit 2x128Mx / 70ball BGA /11 4 GB 256Mx72 1 Gbit 2x256Mx / 70ball BGA / MB 16Mx72 64 Mbit 16Mx ball BGA / MB 32Mx Mbit 32Mx ball BGA /11 F 1 GB 64Mx Mbit 64Mx ball BGA /11 2 GB 128Mx Mbit 128Mx ball BGA /11 4 GB 256Mx72 1 Gbit 256Mx ball BGA /12 Release 16 Revision 2.2

24 Page DDR SDRAM Module Configurations (Reference Designs) (Page 2 of 2) Raw Card Version DIMM SDRAM Capacity Organization Density Organization # of SDRAMs SDRAM Package Type # of Physical Banks # of Banks in SDRAM # of Address bits row/col 64 MB 8Mx72 64 Mbit 8Mx ball BGA /9 128 MB 16Mx Mbit 16Mx ball BGA /10 K 256 MB 32Mx Mbit 32Mx ball BGA / MB 64Mx Mbit 64Mx ball BGA /11 1 GB 128Mx72 1 Gbit 128Mx ball BGA / MB 16Mx72 64 Mbit 8Mx Ball / MB 32Mx Mbit 16Mx Ball /11 M 512 MB 64Mx Mbit 32Mx Ball /11 1 GB 128Mx Mbit 64Mx Ball /12 2 GB 256Mx72 1 Gbit 128Mx Ball / MB 16Mx72 64 Mbit 16Mx / 62Ball / MB 32Mx Mbit 32Mx / 62 Ball /11 N 1 GB 64Mx Mbit 64Mx / 62 Ball /11 2 GB 128Mx Mbit 128Mx / 62 Ball /11 4 GB 256Mx72 1 Gbit 256Mx / 62 Ball / MB 16Mx72 64 Mbit 8Mx / 62 Ball /9 256 MB 32Mx Mbit 16Mx / 62 Ball /10 L 512 MB 64Mx Mbit 32Mx / 62 Ball /10 1 GB 128Mx Mbit 64Mx / 62 Ball /11 2 GB 256Mx72 1 Gbit 128Mx / 62 BAll /11 Revision 2.2 Release 16

25 Page Input Loading Matrix Signal Names Input Device Raw Card Version A, G B, H C, J D E F Clock (CK0, CK0) PLL Chip Select, Clock Enable (S0, 0) Register Chip Select, Clock Enable (S1, 1) Register N/A 1 N/A Addresses and Controls (A0-A13, BA0, BA1, RAS, CAS, WE) Register Data and Strobe (DQ, DQS) DDR SDRAM Data Mask () DDR SDRAM 1 2 N/A N/A N/A N/A SCL, SDA, SA EEPROM DDR Registered DIMM Design File Releases Reference Design file updates will be released as needed. This Registered DIMM specification will reflect the most recent Design files, but may also be updated to reflect clarifications to the specification only; in these cases the Design files will not be updated. The following table outlines the most recent Design file releases. Note: Future Design file releases will include both a date and a revision label. All changes to the Design file are also documented in detail within the read-me file. Raw Card Version Specification Revision Applicable Design File Notes A 0.8 A0 B 0.8 B0 C 0.8 C0 Original Release 8/3/2001 Dec 2005 registration ballot passed Original Release 6/10/2001 Dec 2005 registration ballot passed Original Release 9/16/2001 March 2006 registration ballot passed D 1.11 D0 Original Release 2/21/2002 March 2006 registration ballot passed E 1.2 E0 Original Release 08/01/2003 F 1.3 F0 Original Release 07/30/2003 G 0.5 G0 Original Release 7/30/2003 H 0.5 H0 Original Release TBD J 0.5 J0 Original Release 7/30/2003 K 2.2 K0 Dec 2005 registration ballot passed L 2.2 L0 June 2006 registration ballot passed M 2.2 M0 Dec 2005 registration ballot passed N 2.2 N0 Dec 2005 registration ballot passed Release 16 Revision 2.2

26 Page Component Types and Placement Components shall be surface mounted on both sides of the PCB and positioned on the PCB to meet the minimum and maximum trace lengths required for DDR SDRAM signals. Bypass capacitors for DDR SDRAM devices must be located near the device power pins. The following layouts suggest placement for the Raw Card Versions A, B, C, D, E, F, G, H and J. Exact spacing is not provided, but should be based on manufacturing constraints and signal routing constraints imposed by this design guide. The external dimensions are controlled by MO-206. The numbers in the drawings are for reference only. Example: Raw Card A (single-sided, BGA DRAMs, TSSOP supports) Front: PLL (2X) Register Register Side Back: (single-sided) (2) ± ±.004 Note: All dimensions are for reference only. See MO-206 for details. Millimeters Inches Revision 2.2 Release 16

27 Page Example: Raw Card B and C (double-sided, BGA DRAMs, TSSOP supports) Front PLL (2X) Register Side (2) Back Register 1.27 ± ±.004 Note: All dimensions are for reference only. See MO-206 for details. Millimeters Inches Release 16 Revision 2.2

28 Page Example: Raw Card D (double-sided, BGA DRAMs, TSSOP PLL, MLF2 register) Front PLL (2X) , Register Side (2) Back Register ± ±.004 Note: All dimensions are for reference only. See MO-206 for details. Millimeters Inches Revision 2.2 Release 16

29 Page Example: Raw Card E (double-sided, BGA Stacked DRAMs, MLF PLL, MLF2 register) Front PLL (2X) Register Side (2) Back Register ± ±.004 Note: All dimensions are for reference only. See MO-206 for details. Millimeters Inches Release 16 Revision 2.2

30 Page Example: Raw Card F (double-sided, BGA DRAMs, MLF PLL, MLF2 register) Front (2X) , Register Side (2) Back PLL Register ± ±.004 Note: All dimensions are for reference only. See MO-206 for details. Millimeters Inches Revision 2.2 Release 16

31 Page Example: Raw Card G (single-sided, BGA DRAMs, VFQFN & VFEQFP supports) Front Example: Raw Card H (double-sided, BGA DRAMs, VFQFN, VFQFP supports) Front Back Release 16 Revision 2.2

32 Page Example: Raw Card J (double-sided, BGA DRAMs, VFQFN, & VFQFP Supports) Front Back Revision 2.2 Release 16

33 Page Example: Raw Card K (Single-sided, BGA DRAMs) Front Back Release 16 Revision 2.2

34 Page Example: Raw Card M / N (Double-sided, BGA DRAMs) Front Back Revision 2.2 Release 16

35 Page Example: Raw Card L (Double-sided, BGA DRAMs) Front Back Release 16 Revision 2.2

36 Page DIMM Wiring Details Signal Groups This specification categorizes DDR SDRAM timing-critical signals into eight groups. The following table summarizes the signals contained in each group.. Signal Group Signals In Group Raw Card Version Page PLL Input / Unused Clocks CK, CK A, B, C, D, E,F, G, H, J 38 PLL Output PCK[9:0], PCK[9:0], FBOUT, FBOUT A, B, C, D, E,F, G, H, J 38, 40 Data DQ[63:0], CB[7:0] A, B, C, D, E,F, G, H, J 49 DQS[8:0] A, B, C, D, E, F, G, H, J 49 DQS DQS[17:0] C, J 49 [0:8] A, B, G, H 49 Address and Control Lead-in Nets Address and Control Post-Register Nets Chip Select, Clock Enable General Net Structure Routing Guidelines Net structures and lengths must satisfy signal quality and setup/hold time requirements for the memory interface. Net structure diagrams for each signal group are shown in the following sections. Each diagram is accompanied by a trace length table that lists the minimum and maximum allowable lengths for each trace segment and/or net. The general routing requirements are as follows Route all signal traces except clocks using 4/6 rules, i.e. 4 mil traces and 6 mil minimum spacing between adjacent traces. Raw card F has 4 mil trace to trace spacing for the ADD/CMD post register bus. Route clocks using 4 mil lines and 6 mil spaces between differential clock pairs. Route clocks using at least 90% of the total trace length in the inner layers. Route clocks keeping a maximum space between differential pairs and all other nets (18 mils minimum). Route clocks keeping a maximum space between loops of differential pairs (36 mils minimum). Explanation of Net Structure Diagrams A[13:0], BA[1:0], RAS, CAS, WE, [0,1], [0,1] A[13:0], BA[1:0], RAS, CAS, WE, A, B, C, D, E, F, G, H, J 51 A 33 B, C, E 34,39 D, F 37,40 G 58 H, J [0], [0] A 33 [0,1], [0,1] B [0], [0] C, E 54 [0,1], [0,1] D, F 38,41 [0], [0] G [0,1], [0,1] H [0], [0] J The net structure routing diagrams provide a reference design example for each raw card version. These Revision 2.2 Release 16

37 Page designs provide an initial basis for registered DIMM designs. The diagrams should be used to determine individual signal wiring on a DIMM for any supported configuration. Only transmission lines (represented as cylinders and labeled with trace length designators TL ) represent physical trace segments. All other lines are zero in length. To verify DIMM functionality, a full simulation of all signal integrity and timing is required. The given net structures and trace lengths are not inclusive for all solutions. Once the net structure has been determined, the permitted trace lengths for the net structure can be read from the table below each net structure routing diagram. Some configurations require the use of multiple net structure routing diagrams to account for varying load quantities on the same signal. All diagrams define one load as one SDRAM input. It is highly recommended that the net structure routing data in this document be simulated by the user. Net Structure Example A 512 MB double-sided x72 DIMM using 256 Mbit, 32 M x 8 SDRAM devices would have a data net structure as shown in the following diagram. DIMM Connector TL0 22 ohms ± 5% TL1 SDRAM Pin Release 16 Revision 2.2

38 Page Differential Clock Net Structures DDR SDRAM clock signals must be carefully routed to meet the following requirements: Signal quality Rise/Fall time Cross point of the differential pair into the SDRAM and register JEDEC-compatible reference delays Minimal segment length differences (less than 100 mils total) between clocks of the same function PLL input net segment length is newly defined and optimized for high speed DDR Registered DIMMs.. Net Structure of Clock Lead-in to PLL Input (Raw Cards A, B, C, D, E, F, G): CK0, CK0 PLL Clock Input Unloaded clocks CK1, CK2 No Connection C1 DIMM Connector CK0 CK0 R1 TL0 TL1 Raw Card A, D, F PLL Raw Card G Trace Lengths of Clock Lead-in Net to PLL Input ( Raw Cards (A, B, C, D, E, F, G, K, M, N): Raw Card TL0 (CK) TL0 (CK) (CK) (CK) TL0+ TL1 (CK) TL1 (CK) (CK) (CK) C1 (pf) R1 (ohms) A NA NA B, C 1.00 N/A NA NA 120 1, 2 D, F NA NA E 1.04 N/A NA NA G K M N All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. The termination resistor is placed after the pin of the PLL for RawCards B and C. Notes Revision 2.2 Release 16

39 Page Net Structure of Clock Lead-in to PLL Input (Raw Cards H, J) Unloaded Clock s CK1, CK2 No Connection DIMM Connector CK0 CK0 TL0 PLL Clock Input C1 TL1 R1 PLL Trace Lengths of Clock Lead-in Net to PLL Input (Raw Cards H, J) Raw Card TL0 (CK) TL0 (CK) TL1 (CK) TL1 (CK) (CK) (CK) TL0 +TL1 + R1 (ohms) C1 (pf) Notes H, J All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. Net Structure of Clock Lead-in to PLL Input (Raw Card L) Unloaded Clock s CK1, CK2 No Connection PLL Clock Input DIMM Connector CK0 CK0 TL1 PLL C1 R1 Trace Lengths of Clock Lead-in Net to PLL Input (Raw Card L) Raw Card TL1 (CK) TL1 (CK) (CK) (CK) (CK) (CK) (CK) (CK) (CK) (CK) R1 (ohms) L All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. C1 (pf) Notes Release 16 Revision 2.2

40 Page Net Structure of PLL Feedback Path (Raw Cards A, B, C, D, E, F, K): PLL Feedback Path PLL FBIN FBIN TL1 R1 C1 RAW CARD B, C C1 RAW CARD E only FBOUT FBOUT TL0 C1 RAW CARD A, D, F Trace Lengths for PLL Feedback Path (Raw Cards A, B, C, D, E, F, K): Raw Card TL0 TL1 TL0+TL1+ R1 C1 Min Max Min Max Min Max Min Max Min Max Min Max [ohms] [pf] Notes A N/A N/A , 2 B, C N/A , 2, 3 D, F N/A N/A , 2, 3 E N/A , 2, 3 K , 2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. All capacitances are given in pf and must be kept within a tolerance of ± 5%. 3. The termination resistor and loading capacitor are both placed as close to the input pins of the PLL as possible. Revision 2.2 Release 16

41 Page Net Structure of PLL Feedback Path (Raw Cards M, N, and L): PLL Feedback Path FBIN FBIN TL1 R1 C1 PLL FBOUT FBOUT TL0 Trace Lengths for PLL Feedback Path (Raw Cards M, N, and L): Raw Card TL0 TL1 TL0+TL1+ R1 C1 Min Max Min Max Min Max Min Max Min Max Min Max [ohms] [pf] Notes M N/A N/A , 2 N N/A N/A , 2 L N/A N/A , 2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. All capacitances are given in pf and must be kept within a tolerance of ± 5%. 3. The termination resistor and loading capacitor are both placed as close to the input pins of the PLL as possible. Net Structure of PLL Feedback Path (Raw Card G) PLL Feedback Path FBIN FBIN TL1 R1 C1 PLL FBOUT FBOUT TL0 Release 16 Revision 2.2

42 Page Trace Lengths for PLL Feedback Path (Raw Card G) TL0 TL1 R1 C1 Raw Card Notes Min Max Min Max Min Max Min Max [ohms] [pf] G ,2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. All capacitances are given in pf and must be kept within a tolerance of ± 5%. Net Structure of PLL Feedback Path (Raw Cards H, J) PLL Feedback Path FBIN FBIN C1 PLL TL1 FBOUT FBOUT TL0 R1 Trace Lengths for PLL Feedback Path (Raw Cards H, J) Raw Card TL0 TL1 TL0+TL1+ R1 C1 Min Max Min Max Min Max Min Max [ohms] [pf] Notes H ,2 J ,2 1. All distances are given in inches and must be kept within a tolerance of ± 0.01 inch. 2. All capacitances are given in pf and must be kept within a tolerance of ± 5%. Revision 2.2 Release 16

43 Page Net Structure of PLL Output to SDRAM PLL Output to SDRAM Load PLL not present on Raw Card A, G TL1 Raw Card E SDRAM not present on Raw Card A, G CK CK TL0 R1 SDRAM SDRAM RAW CARD - D, F only TL1 SDRAM Raw Card E Trace Lengths for PLL Clock Output to SDRAM Nets Raw Card TL0 TL1 TL0 + TL1 Min Max Min Max Min Max Min Max R1 [ohms] Notes A B, C E D, F G H J K Raw Card TL0 TL1 + Min Max Min Max Min Max Min Max R1 [ohms] Notes N N L All distances are in inches and should be kept within a tolerance of ± 0.01 inch. Release 16 Revision 2.2