PMC429-4/8/16/32 Hardware Manual

Transcription

1 PMC429-4/8/16/32 Hardware Manual 4/8/16/32 Channel Conduction Cooled ARINC429 Module for PMC November 2014 V02.00 Rev. C

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3 PMC429-4/8/16/32 Hardware Manual 4/8/16/32 Channel Conduction Cooled ARINC429 Module for PMC V02.00 Rev. C November 2014

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5 Table of Contents...1 Section 1 INTRODUCTION 1.1 General How This Manual... 2 is Organized 1.3 Applicable... 2 Documents Industry Documents Product Specific... Documents 3 Section 2 STRUCTURE...4 OF THE PMC Section 3 INSTALLATION 3.1 Installing the... 5 PMC429-4/8/16/32 Module Installation Instructions The PMC Connector Connections... 6 to the I/O Signals Connection to the... ARINC429 Interface Connection to the... Trigger Signals Rear I/O Connector Front Panel Connector... 9 Section 4 TECHNICAL...11 DATA Section 5 NOTES Acronyms and Abbreviations II

6 1 INTRODUCTION 1.1 General DOCUMENT HISTORY Version Date Author V02.00 Rev. A October 2010 Troy Troshynski/Melissa Amarawardana V02.00 Rev. B December 2012 Drake Dingeman/Troy Troshynski V02.00 Rev. C November 2014 Melissa Amarawardana Description Creation of Manual Technical Specification Updates Format updates This document comprises the Hardware Manual for the PMC429-4/8/16/32 PCI Mezzanine Card. The document covers the hardware installation, the board connections, a general description of the hardware architecture, and the technical data of the PMC429. For programming information, refer to the according documents listed in the Applicable Documents section of this manual. The PMC429 module is a member of AIT's family of advanced PMCbus modules for analyzing, simulating, monitoring, and testing of avionics databus systems. The PMC module is a conduction cooled module that is designed to be plugged onto either a host carrier board to adapt to standard PCI, VME or CPCI buses, or on an embedded host computer with PMC ports. The PMC429 provides four, eight, 16, or 32 fully configurable ARINC429 channels, whereby the four, eight, and 16 channel boards are a build variant of the 32 channel board. Each channel can be individually configured by software as a transmit or receive channel with shared front plate and rear I/O connector outputs and inputs. An optional daughter board may be assembled providing support for front panel I/O of the ARINC429 signals and the addition of support for IRIG-B encode, decode, and absolute time synchronization. Addition of the optional daughter board also provides access to a trigger output signal. On transmit channels, the PMC429 acts as an autonomously operating bus traffic simulator supporting multiple modes of transmission sequencing, including label rate oriented, scheduled, and acyclic transmissions. Full error injection capabilities are available, whereby the error injection is programmable individually for each channel and label. For a special transmission operating mode, the parity bit can be used alternately as an additional data bit. The bit time and duty cycle of the transmit bus signals can be individually controlled, with +/8nS accuracy for each transmit channel. For the receive channels, the PMC429 provides an advanced monitor and analyzer function with unique onboard error detection, triggering, and filtering capabilities. The minimum bit time 1

7 (data + null) and the maximum data time can be individually controlled, with +/-8nS accuracy for each receive channel. Both functions are available concurrently and independent from each other. The hardware architecture provides resources to guarantee that the performance of one function is not affected by the current load of the other function. 1.2 How This Manual is Organized This is comprised of the following sections: Section 1, INTRODUCTION, contains an overview of this manual. Section 2, STRUCTURE OF THE PMC429, describes the physical hardware interfaces on the PMC429 using a block diagram and a description of each main component. Section 3, INSTALLATION, describes the steps required to install the PMC429 device and to connect the device to other external interfaces, including ARINC429 interfaces, IRIG-B, and triggers. Section 4, TECHNICAL DATA, describes the technical specification of the PMC429. Refer to the ARINC429 Object Wrapper Library Reference Manual for programming information. 1.3 Applicable Documents The following documents shall be considered to be a part of this document to the extent that they are referenced herein. In the event of conflict between the documents referenced and the contents of this document, the contents of this document shall have precedence Industry Documents ARINC MARK 33 Digital Information Transfer System (DITS) ARINC specification , Published: March 10, 1993 Draft Standard for CMC, P1386 / Draft 2.4, Jan 12th, 2001 Draft Standard for PMC, P1386 / Draft 2.4, Jan 12th, 2001 Draft Standard for CCPMC, Draft 1.8, July 21st, 1999 ANSI/VITA (R2005) 2

8 1.3.2 Product Specific Documents ARINC429 Object Wrapper Library Reference Manual, provides a detailed description of the high level object oriented programming interface between host application programs and the PMC429. 3

9 2 STRUCTURE OF THE PMC429 The structure of the PMC429 board is shown in the following block diagram. The PMC429 consists of a main PMC module and an optional daughter board which adds front panel I/O access to the ARINC429 signals, IRIB encoder/decoder capabilities, and an output trigger signal. Figure 2: Structure of the PMC429 The four primary components of the main PMC module are: PCI to Local Bus Bridge Generator/Analyzer FPGA SDRAM (128 Mbyte) ARINC429 Transceivers The primary components of the optional daughter card are: VHDCI connector IRIG-B Encoder/Decoder 4

10 3 INSTALLATION 3.1 Installing the PMC429-4/8/16/32 Module The PMC429 features full PCI 'plug-and-play' capability. There are no jumpers or switches on the board which have to be modified by the user. Note: We recommend that you use a wrist strap for any installations. If there is no wrist wrap available, then touch a metal plate on your system to ground yourself and discharge any static electricity during the installation work. The following instructions describe how to install the PMC429 module in your system. Follow the instructions carefully to avoid any damage on the device Installation Instructions To Install the PMC429 Module 5 1. Shut down your system and all peripheral devices. Unplug the power cord from the wall outlet. Inserting or removing modules with power applied may result in damage to the module devices. 2. Remove the system cover to gain access to the system slots. 3. Remove the PMC carrier (board or host) from the system slot. 4. Remove the PMC slot filler panel from the host front panel. 5. Place the PMC429 mezzanine module on top of the carrier with the PMC connectors on the PMC429 aligned with the corresponding connectors on the carrier. Ensure the correct size of the Bezel with ESD-gasket on the host front panel and the correct size of the voltage keying pins. Then connect the PMC connectors smoothly. 6. Align the standoffs on the PMC429 module with the carrier. Install the screws through the holes in the carrier and the spacers. Tighten the screws. 7. Install the complete board into its card slot. Ensure the module is seated properly in the backplane connectors. Take care not to damage or bend connector pins. Secure the board. 8. Replace the cover of your system.

11 Connect system with power source and turn on the power to your system. The PMC Connector The PMC connectors are assigned to support the draft standard of physical and environmental layer for PCI 64 Bit Mezzanine cards (PMC Draft Standard incl. P / Draft 2.4) Pn1/Jn1 Pn2/Jn2 Pn3/Jn3 Pn4/Jn4 64 Bit PCI Interface 64 Bit PCI Interface 64 Bit PCI Interface Rear I/O 3.2 Connections to the I/O Signals Connection to the ARINC429 Interface For each channel, the transmitter and receiver share two pins (TxRx_a (TRUE) / TxRx_b (COMPLEMENT)) on the front connector. Make sure that only one transmitter is connected on one ARINC connection Connection to the Trigger Signals When the front panel mezzanine is assembled, the front panel connector provides access to a trigger output signal and the IRIG input/output signals in addition to the ARINC429 receive and transmit signals. The IRIG-IN and IRIG-OUT signals shall be connected depending on the time tagging method used as described below: Single AIT module with no external IRIG source: no connections required Multiple AIT modules with common synchronization requirement: no connections 6

12 required Single or multiple AIT modules with external IRIG source: connect IRIG source to IRIG-IN and GND of all modules Multiple AIT modules with no external IRIG source: connect the IRIG-OUT signal and the GND of the module you have chosen as the time master to all IRIG-IN and GND signals (including the master's) 7

13 3.2.3 Rear I/O Connector Table 3.2.3: Rear I/O Connector Pin-Out Pin No. Signal Direction Type Pin No. Signal Direction Type 1 TxRx_a_32 33 TxRx_a_1 2 TxRx_b_32 34 TxRx_b_1 3 TxRx_a_30 35 TxRx_a_2 4 TxRx_a_25 36 TxRx_b_2 5 TxRx_b_30 37 TxRx_a_3 6 TxRx_b_25 38 TxRx_b_3 7 TxRx_b_29 39 TxRx_a_4 8 TxRx_a_26 40 TxRx_b_4 9 TxRx_a_31 41 TxRx_a_5 10 TxRx_b_26 42 TxRx_b_5 11 TxRx_b_31 43 TxRx_a_6 12 TxRx_a_27 44 TxRx_b_6 13 TxRx_a_29 45 TxRx_a_7 14 TxRx_b_27 46 TxRx_b_7 15 TxRx_a_17 47 TxRx_a_8 16 TxRx_a_28 48 TxRx_b_8 17 TxRx_b_17 49 TxRx_a_9 18 TxRx_b_28 50 TxRx_b_9 19 TxRx_a_18 51 TxRx_a_10 20 TxRx_b_18 52 TxRx_b_10 21 TxRx_a_19 53 TxRx_a_11 22 TxRx_b_19 54 TxRx_b_11 23 TxRx_a_20 55 TxRx_a_12 24 TxRx_b_20 56 TxRx_b_12 25 TxRx_a_21 57 TxRx_a_13 26 TxRx_b_21 58 TxRx_b_13 27 TxRx_a_22 59 TxRx_a_14 28 TxRx_b_22 60 TxRx_b_14 29 TxRx_a_23 61 TxRx_a_15 30 TxRx_b_23 62 TxRx_b_15 31 TxRx_a_24 63 TxRx_a_16 32 TxRx_b_24 64 TxRx_b_16 8

14 3.2.4 Front Panel Connector The front panel connector is a 68-pin VHDCI I/O connector. Table 3.2.4: Front Panel Pin-Out 9 Pin No. Signal Direction Pin No. Signal Direction 1 TxRx_a_1 35 TxRx_b_1

15 2 TxRx_a_2 36 TxRx_b_2 3 TxRx_a_3 37 TxRx_b_3 4 TxRx_a_4 38 TxRx_b_4 5 TxRx_a_5 39 TxRx_b_5 6 TxRx_a_6 40 TxRx_b_6 7 TxRx_a_7 41 TxRx_b_7 8 TxRx_a_8 42 TxRx_b_8 9 TxRx_a_9 43 TxRx_b_9 10 TxRx_a_10 44 TxRx_b_10 11 TxRx_a_11 45 TxRx_b_11 12 TxRx_a_12 46 TxRx_b_12 13 TxRx_a_13 47 TxRx_b_13 14 TxRx_a_14 48 TxRx_b_14 15 TxRx_a_15 49 TxRx_b_15 16 TxRx_a_16 50 TxRx_b_16 17 TxRx_a_30 51 TxRx_b_30 18 TxRx_a_31 52 TxRx_b_31 19 TxRx_a_17 53 TxRx_b_17 20 TxRx_a_18 54 TxRx_b_18 21 TxRx_a_19 55 TxRx_b_19 22 TxRx_a_20 56 TxRx_b_20 23 TxRx_a_21 57 TxRx_b_21 24 TxRx_a_22 58 TxRx_b_22 25 TxRx_a_23 59 TxRx_b_23 26 TxRx_a_24 60 TxRx_b_24 27 TxRx_a_29 61 TxRx_b_29 28 GND Pow. 62 TRIGGER_OUT OUT 29 IRIG_IN IN 63 IRIG_OUT OUT 30 TxRx_a_25 64 TxRx_b_25 31 TxRx_a_26 65 TxRx_b_26 32 TxRx_a_27 66 TxRx_b_27 33 TxRx_a_28 67 TxRx_b_28 34 TxRx_a_32 68 TxRx_b_32 10

16 4 TECHNICAL DATA PCI Interface: Fully compatible with PCI Standard (Revision 2.2) 3.3V PMC (5V tolerant I/Os), 64 bit, 33MHz/66MHz bus operation Clock speed up to 66MHz with no wait states Memory: 128 Mbyte DDR2 SDRAM Channels: Up to 32 channels, each software programmable as transmit or receive Programmable bit time in 8nS steps Programmable duty cycle in 8nS steps Encoder: Decoder: Time Tagging: IRIG Input: Error injection capabilities: Gap errors Parity errors Bit count high/low errors Coding errors Programmable minimum bit time in 8nS steps Programmable maximum data portion (of a bit) time in 8nS steps Error detection capabilities: Gap errors Parity errors Bit count high/low errors Coding errors For absolute time tagging a special time code processor implements a 45 bit time tag (20 bits microseconds + 25 bits raw binary seconds) Resolution: Width: Signal Type: Signal Waveform Modulation Ratio: Input Amplitude: Input Impedance: Coupling: Time Jitter: Lock time: IRIG Output: 11 Signal Type: Signal Waveform: Modulation Ratio: <10nS 14 BCD digits (400 days) Single ended analog Amplitude modulated sine wave or square wave 3:1 to 6:1 0.2Vpp to 3Vpp > 3k Ohm AC coupled +/- 5nS (typical, module to module) depending on input signal quality 1 to 5 seconds depending on input signal quality Single ended analog Amplitude modulated sine wave 3:1

17 Output Amplitude: Output Impedance: +/- 1.5 volts 1.3 ohms typ. (designed for 50 ohm load) Connectors: Front Panel: Back Plane: 68-pin VHDCI Compliant with PMC Draft Standard incl. P / Draft 2.4 Dimensions: 74mm X 143.7mm Hole and connector dimensions and locations per: ANSI/VITA (R2005) Supply Voltage: PC Supply Power (Operating): +3.3V: +3.3V(+/- 5%) +5.0V(+/- 5%) +/-12V(+/- 5%) 1.25 Amps (Idle or Active) +5V: 0.35 Amps (Idle) 0.88 Amps (Active*) 1.18 Amps (Active**) +12V: 0 Amps -12V: 0 Amps Total Power: 5.88 Watts (Idle) 8.5 Watts (Active*) 10 Watts (Active**) Active* Channels Transmitting at full rate, single receive load Active** Channels Transmitting at full rate, single receive load and 400 Ohm parallel resistive load on each channel) Temperature: -40 C to +85 C Operating -40 C to +85 C Storage Humidity: 0 to 95% (non condensing) 12

18 5 NOTES 5.1 Acronyms and Abbreviations ARINC ADC ALBI ARM BIP BIU DAC DRAM EDO EEPROM EPROM FLASH FPGA IRIG IRIG B I/O LCA PC PROM PCI PSC RISC RAM SDK SIMM SRAM SSRAM TCP UART 13 AERONAUTICAL RADIO, INC. Analog to Digital Converter ASP Local Bus Interface Advanced RISC Machine Bus Interface Processor Bus Interface Unit Digital to Analog Converter Dynamic Random Access Memory Enhanced Data Output Electrically Erasable and Programmable Read Only Memory Erasable Programmable Read Only Memory Page oriented electrical erasable and programmable memory Field Programmable Gate Array Inter Range Instrumentations Group Inter Range Instrumentations Group Time code Format Type B Input/Output Logic Cell Array (XILINX - Programmable Gate Array) Personal Computer Programmable Read Only Memory Peripheral component interconnect PCI and System Controller Reduced Instruction Set Computer Random Access Memory AIT's Software Development Kit Single Inline Memory Module Static Random Access Memory Synchronous Static Random Access Memory Time Code Processor Universal Asynchronous Receiver and Transmitter