PCI-C429P Hardware Manual

Transcription

1 PCI-C429P Hardware Manual 4/8/16/32 Channel ARINC429 Test & Simulation Module for PCI/PCI-X November 2014 V02.00 Rev. C

2

3 PCI-C429P Hardware Manual 4/8/16/32 Channel ARINC429 Test & Simulation Module for PCI/PCI-X V02.00 Rev. C November 2014

4

5 Table of Contents...1 Section 1 INTRODUCTION 1.1 General How This Manual... 2 is Organized 1.3 Applicable... 2 Documents Industry Documents Product Specific... Documents 3 Section 2 STRUCTURE...4 OF THE PCI-C429 MODULE...6 Section 3 INSTALLATION 3.1 Installing the... 6 PCI-C429P Module Installation Instructions Board Connectors Connections... 8 to the I/O Signals PCI-C429P Front... Panel Connector (J3) PCI-C429P Rear... I/O Connector (J4) ARINC429 Connections IRIG Connections Section 4 TECHNICAL...13 DATA Section 5 NOTES Acronyms and Abbreviations II

6 1 INTRODUCTION 1.1 General Document History Version Date Author V01.00 Rev. A 27-May-2008 T. Troshynski Description Creation of document V02.00 Rev. A September 2010 M. Applied new AIT format, technical edits Amarawardana V02.00 Rev. B December 2012 M. Technical updates Amarawardana V02.00 Rev. C November 2014 M. Format Updates Amarawardana This document comprises the Hardware Manual for the PCI-C429P hardware module which is a member of AIT's family of advanced ARINC429 test and simulation modules. This document covers the hardware installation, the board connections, a general description of the hardware architecture, and specific electrical and physical technical data of the module. For programming information, refer to the according documents listed in the Applicable Documents section of this manual. The PCI-C429P module is a standard PCI half length module that is designed to be plugged into both 5V and 3.3V PCI and PCI-X host systems. The PCI-C429P provides four, eight, 16, or 32 fully configurable ARINC429 channels, whereby the four, eight, and 16 channel boards are a build variant of the 32 channel board. Each channel can be individually configured by software as a transmit or receive channel with shared front plate and rear I/O connector outputs and inputs. On transmit channels, the PCI-C429P acts as an autonomously operating bus traffic simulator supporting multiple modes of transmission sequencing, including label rate oriented, scheduled, and acyclic transmissions. Full error injection capabilities are available, whereby the error injection is programmable individually for each channel and label. For a special transmission operating mode, the parity bit can be used alternately as an additional data bit. The bit time and duty cycle of the transmit bus signals can be individually controlled, with +/8nS accuracy for each transmit channel. For the receive channels, the PCI-C429P provides an advanced monitor and analyzer function with unique onboard error detection, triggering, and filtering capabilities. The minimum bit time (data + null) and the maximum data time can be individually controlled, with +/-8nS accuracy for each receive channel. Both functions are available concurrently and independent from each other. The hardware 1

7 architecture provides resources to guarantee that the performance of one function is not affected by the current load of the other function. The modules provide an onboard IRIG B Time Decoder/Encoder in support of time synchronization with external equipment. Each module may be configured to synchronize its internal clock to an input IRIG B time signal. Additionally, the module may also be configured as an IRIG-B time source capable of providing a reference time signal. Additionally, an output trigger signal is provided in order to trigger external equipment based on programmable ARINC429 bus conditions. 1.2 How This Manual is Organized This is comprised of the following sections: Section 1, INTRODUCTION, contains an overview of this manual. Section 2, STRUCTURE OF THE PCI-C429, describes the physical hardware interfaces on the PCI-C429 using a block diagram and a description of each main component. Section 3, INSTALLATION, describes the steps required to install the PCI-C429 device and to connect the device to other external interfaces, including ARINC429 interfaces, IRIG-B, and triggers. Section 4, TECHNICAL DATA, describes the technical specification of the PCIC Applicable Documents The following documents shall be considered to be a part of this document to the extent that they are referenced herein. In the event of conflict between the documents referenced and the contents of this document, the contents of this document shall have precedence Industry Documents ARINC MARK 33 Digital Information Transfer System (DITS) ARINC specification , Published: March 10, 1993 Draft Standard for CMC, P1386 / Draft 2.4, Jan 12th, 2001 Draft Standard for PMC, P1386 / Draft 2.4, Jan 12th, 2001 Draft Standard for CCPMC, Draft 1.8, July 21st, 1999 ANSI/VITA (R2005) ANSI/VITA PMC-P4 mapping to VME-P2 PCI Local Bus Specification, R2.3 PCI-X Addendum to PCI Local Bus Specification, R1.0a 2

8 PCI-to-PCI Bridge Architecture Specification, Revision Product Specific Documents ARINC429 Object Wrapper Library Reference Manual, provides a detailed description of the high level object oriented programming interface between host application programs and the PCI-C429. 3

9 2 STRUCTURE OF THE PCI-C429 MODULE Figure 2: Structure of the PCI-C429 4

10 The primary components of the PCI-C429 are: PCI to Local Bus Bridges The PCI/PCI-X to PCI/PCI-X bridge and the PCI to Local Bus bridge provide a bridge between the host PCI or PCI-X back plane and the onboard local data bus. The bridges allow the PCI-C429P module to be inserted into PCI or PCI-X host system slots. 3.3V or 5V signalling is supported as well as 32-bit or 64-bit operations. 33/66/100/133 MHz back plane clock rates are also supported. ARINC429 Core FPGA The ARINC429 Core FPGA is implemented in a Xilinx Virtex 4. The Core FPGA supports all of the ARINC429 encode/decode, error injection/detection, and time tagging logic. SDRAM (128 Mbyte) The 128 MB SDRAM provides storage for bus transmit and receive buffers. ARINC429 Transceivers The ARINC 429 Transceivers provide the physical encoding and decoding of the ARINC429 bus signals. IRIG-B Encoder/Decoder The IRIG-B Encoder/Decoder supplies the logic needed to generate an IRIG-B output time signal from the modules internal clock as well as the logic needed to synchronize the modules internal clock to an external IRIG-B time signal. 5

11 3 INSTALLATION 3.1 Installing the PCI-C429P Module The PCI-C429P features full PCI 'plug-and-play' capability. There are no jumpers or switches on the board which have to be modified by the user. Note: We recommend that you use a wrist strap for any installations. If there is no wrist wrap available, then touch a metal plate on your system to ground yourself and discharge any static electricity during the installation work. The following instructions describe how to install the PCI-C429P module in your system. Follow the instructions carefully to avoid any damage on the device Installation Instructions To Install the PCI-C429P Module: 1. Shut down your system and all peripheral devices. Unplug the power cord from the wall outlet. (Inserting or removing modules with power applied may result in damage to the module devices.) 2. Remove the system cover to gain access to the system slots. 3. Place the PCI-C429P module into an open PCI or PCI-X slot in your system. 4. Replace the cover of your system. 5. Connect system with power source and turn on the power to your system. 6

12 3.1.2 Board Connectors The PCI-C429P has a universal 64-Bit edge connector (J1A/J1B) that will allow it to be inserted into both 32-Bit and 64-Bit 3.3V and 5V PCI/PCI-X card slots. For PCI operations, the card supports both 33 and 66 MHz. For PCI-X operations, 66, 100, and 133 MHz is supported. The PCI-C429P provides user access to the ARINC429 bus signals, IRIG-B input/output signals, and trigger output signal at the front panel 68-pin VHDCI (J3) connector. The ARINC429 bus signals are also accessible at the rear mail DIN 96 (J4) connector. 7

13 3.2 Connections to the I/O Signals PCI-C429P Front Panel Connector (J3) The PCI-C429P front panel connector (J3) is a 68-pin VHDCI connector that provides access to the ARINC429 bus signals, IRIG-B input/output signals, and the trigger output signal. The pin out for the PCI-C429P is given in the table on the following page. Figure & Table I: Front Panel Pin Assignments Pin No. Signal Direction Pin No. Signal Direction 1 TxRx_a_1 35 TxRx_b_1 2 TxRx_a_2 36 TxRx_b_2 3 TxRx_a_3 37 TxRx_b_3 4 TxRx_a_4 38 TxRx_b_4 5 TxRx_a_5 39 TxRx_b_5 6 TxRx_a_6 40 TxRx_b_6 7 TxRx_a_7 41 TxRx_b_7 8

14 9 8 TxRx_a_8 42 TxRx_b_8 9 TxRx_a_9 43 TxRx_b_9 10 TxRx_a_10 44 TxRx_b_10 11 TxRx_a_11 45 TxRx_b_11 12 TxRx_a_12 46 TxRx_b_12 13 TxRx_a_13 47 TxRx_b_13 14 TxRx_a_14 48 TxRx_b_14 15 TxRx_a_15 49 TxRx_b_15 16 TxRx_a_16 50 TxRx_b_16 17 TxRx_a_30 51 TxRx_b_30 18 TxRx_a_31 52 TxRx_b_31 19 TxRx_a_17 53 TxRx_b_17 20 TxRx_a_18 54 TxRx_b_18 21 TxRx_a_19 55 TxRx_b_19 22 TxRx_a_20 56 TxRx_b_20 23 TxRx_a_21 57 TxRx_b_21 24 TxRx_a_22 58 TxRx_b_22 25 TxRx_a_23 59 TxRx_b_23 26 TxRx_a_24 60 TxRx_b_24 27 TxRx_a_29 61 TxRx_b_29 28 GND Pow. 62 TRIGGER_OUT OUT 29 IRIG_IN IN 63 IRIG_OUT OUT 30 TxRx_a_25 64 TxRx_b_25 31 TxRx_a_26 65 TxRx_b_26 32 TxRx_a_27 66 TxRx_b_27 33 TxRx_a_28 67 TxRx_b_28 34 TxRx_a_32 68 TxRx_b_32

15 Table II: Signal Descriptions Signal Description TxRx_a_x ARINC 429 Channel x Tx and Rx (True) TxRx_b_x ARINC 429 Channel x Tx and Rx (Compliment) IRIG_IN IRIG-B Input IRIG_OUT IRIG-B Output TRIGGER_OUT Trigger Output GND Ground 10

16 3.2.2 PCI-C429P Rear I/O Connector (J4) Table 3.2.2: PCI-C429P Rear I/O Connector (J4) Pin Assignments 11 J4 (Row C) Pin# Signal J4(Row A) Pin# J4 (Row A) 1 TxRx_a_32 1 TxRx_b_32 2 TxRx_a_30 2 TxRx_a_25 3 TxRx_b_30 3 TxRx_b_25 4 TxRx_b_29 4 TxRx_a_26 5 TxRx_a_31 5 TxRx_b_26 6 TxRx_b_31 6 TxRx_a_27 7 TxRx_a_29 7 TxRx_b_27 8 TxRx_a_17 8 TxRx_a_28 9 TxRx_b_17 9 TxRx_b_28 10 TxRx_a_18 10 TxRx_b_18 11 TxRx_a_19 11 TxRx_b_19 12 TxRx_a_20 12 TxRx_b_20 13 TxRx_a_21 13 TxRx_b_21 14 TxRx_a_22 14 TxRx_b_22 15 TxRx_a_23 15 TxRx_b_23 16 TxRx_a_24 16 TxRx_b_24 17 TxRx_a_1 17 TxRx_b_1 18 TxRx_a_2 18 TxRx_b_2 19 TxRx_a_3 19 TxRx_b_3 20 TxRx_a_4 20 TxRx_b_4 21 TxRx_a_5 21 TxRx_b_5 22 TxRx_a_6 22 TxRx_b_6 23 TxRx_a_7 23 TxRx_b_7 24 TxRx_a_8 24 TxRx_b_8 25 TxRx_a_9 25 TxRx_b_9 26 TxRx_a_10 26 TxRx_b_10 27 TxRx_a_11 27 TxRx_b_11 28 TxRx_a_12 28 TxRx_b_12 29 TxRx_a_13 29 TxRx_b_13 30 TxRx_a_14 30 TxRx_b_14 31 TxRx_a_15 31 TxRx_b_15 32 TxRx_a_16 32 TxRx_b_16

17 3.2.3 ARINC429 Connections For each channel, the transmitter and receiver share two pins (TxRx_a (TRUE) / TxRx_b (COMPLEMENT)) on the front connector. Make sure that only one transmitter is connected on one ARINC connection IRIG Connections The IRIG_IN and IRIG_OUT signals of the PCI-C429P are provided at the front panel connector (J3). The IRIG_IN and IRIG_OUT signals shall be connected depending on the time tagging method use as described below: Single AIT module with no external IRIG source: no connections required Multiple AIT modules with common synchronization requirement: no connections required Single or multiple AIT modules with external IRIG source: connect IRIG source to IRIG-IN and GND of all modules Multiple AIT modules with no external IRIG source: connect the IRIG-OUT signal and the GND of the module you have chosen as the time master to all IRIG-IN and GND signals (including the master's) 12

18 4 TECHNICAL DATA PCI Interface: Fully compatible with PCI Standard (Revision 2.3) and PCI-X (R1.0a) PCI half length card with Universal PCI connector PCI: 3.3V (5V tolerant I/Os) 32/64 bit, 33MHz/66MHz bus operation PCI-X: 3.3V 32/64 bit, 66/100/133 MHz Memory: 128 Mbyte DDR2 SDRAM Channels: Up to 32 channels, each software programmable as transmit or receive Programmable bit time in 8nS steps Programmable duty cycle in 8nS steps Encoder: Decoder: Time Tagging: IRIG Input: Error injection capabilities: Gap errors Parity errors Bit count high/low errors Coding errors Programmable minimum bit time in 8nS steps Programmable maximum data portion (of a bit) time in 8nS steps Measurement of gap between two labels in the range from <<TBD>> Error detection capabilities: Gap errors Parity errors Bit count high/low errors Coding errors For absolute time tagging a special time code processor implements a 45 Bit time tag (20 bits microseconds + 25 bits raw binary seconds) Resolution: Width: Signal Type: Signal Waveform: Modulation Ratio: Input Amplitude: Input Impedance: Coupling: Time Jitter: 13 <10nS 14 BCD digits (400 days) Single ended analog Amplitude modulated sine wave or square wave 3:1 to 6:1 0.2Vpp to 3Vpp > 3k Ohm AC coupled +/- 5nS (typical, module to module) depending on input signal quality

19 Lock time: 1 to 5 seconds depending on input signal quality IRIG Output: Signal Type: Signal Waveform: Modulation Ratio: Output Amplitude: Output Impedance: Single ended analog Amplitude modulated sine wave 3:1 +/- 1.5 volts 1.3 ohms typ. (designed for 50 ohm load) Connectors: J3 (Front Panel): J4 (Rear I/O): 68-pin VHDCI DIN96 (Male) J1 (Back Plane): Universal PCI/PCI-X Edge Connector Dimensions: Supply Voltage: Standard 1/2 Length PCI Card with universal 64-bit PCI Edge Connector PC Supply: +3.3V(+/- 5%) +5.0V(+/- 5%) +/-12V(+/- 5%) Power (Operating): +3.3V: 1.25 Amps (Idle or Active) +5V: 0.35 Amps (Idle) 0.88 Amps (Active*) 1.18 Amps (Active**) +12V: 0 Amps -12V: 0 Amps Total Power: 5.88 Watts (Idle) 8.5 Watts (Active*) 10 Watts (Active**) Active* Channels Transmitting at full rate, single receive load Active** Channels Transmitting at full rate, single receive load and 400 Ohm parallel resistive load on each channel) Temperature: -40 C to +85 C Operating -40 C to +85 C Storage Humidity: 0 to 95% (non condensing) 14

20 5 NOTES 5.1 Acronyms and Abbreviations ADC AFDX ALBI ANSI ARINC ARM BC BIP BIU CM cpci CPLD CPU DAC DC-DC DIP DMA DRAM DSUB EDO EEPROM EPROM FIFO FLASH FPGA GND IEEE IRIG IRIG-B I/O LCA LED MIL-STD µsec OWL PC PCI PCIe PMC 15 Analog to Digital Converter Avionics Full Duplex Databus Local Bus Interface American National Standards Institute Aeronautical Radio, Incorporated Advanced RISC Machine Bus Controller Bus Interface Processor Bus Interface Unit Chronological Bus Monitor Compact PCI Coupled Central Processing Unit Digital to Analog Converter Direct Current to Direct Current (power conversion) Data Interface Processor Direct Memory Access Dynamic Random Access Memory D-Subminiature Enhanced Data Output Electrically Erasable and Programmable Read Only Memory Erasable Programmable Read Only Memory First in/first out Page oriented electrical erasable and programmable memory Field Programmable Gate Array Ground Institute of Electric and Electronic Engineers Inter Range Instrumentations Group Inter Range Instrumentations Group Time code Format Type B Input/Output Logic Cell Array (XILINX - Programmable Gate Array) Light-emitting Diode Military Standard microsecond Object Wrapper Library Personal Computer Peripheral Component Interconnect Peripheral Component Interconnect Express PCI Mezzanine Card

21 PROM PSC PXI PXIe RAM RISC RMW RS-232 RT RTPTP RXD SDK SIMM SRAM SSRAM TBD TCP TTL TXD UART USB VME VME64 VXI XMC Programmable Read Only Memory PCI and System Controller PCI Extensions for Instrumentation PCI Extensions for Instrumentation Express Random Access Memory Reduced Instruction Set Computer Read-Modify-Write Recommended Standard No.232 (US-Norm) Remote Terminal Remote Terminal Production Test Plan Received Data AIT's Software Development Kit Single Inline Memory Module Static Random Access Memory Synchronous Static Random Access Memory To be determined Time Code Processor Transistor-Transistor Logic Transmitted Data Universal Asynchronous Receiver and Transmitter Universal Serial Bus VERSAmodule Eurocard VME 64bit extension VME Extensions for Instrumentation PCI Express Mezzanine Card 16