M16C/62P Group (M16C/62P, M16C/62PT)

Transcription

1 16 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES Before using this material, please visit our website to verify that this is the most updated document available. Rev Revision date: Sep 01,

2 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page ( When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

3 How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 *1 Symbol Address After Reset XXX XXX 00h *5 Bit Symbol XXX0 Bit Name b1 b0 0 0: XXX Function *2 XXX1 XXX Bit 0 1: XXX 1 0: Do not set a value 1 1: XXX (b2) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. *3 (b4 - b3) Reserved Bit Set to "0" WO *4 XXX5 XXX6 XXX Bit Function varies depending on mode of operation *1 *2 *3 *4 *5 Blank:Set to "0" or "1" according to the application 0: Set to "0" 1: Set to "1" X: Nothing is assigned : Read and write RO: Read only 0: XXX XXX7 XXX Bit RO 1: XXX WO: Write only : Nothing is assigned Reserved bit Reserved bit. Set to specified value. Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to "0" when writing to this bit. Do not set to this value The operation is not guaranteed when a value is set. Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode. Follow the text in each manual for binary and hexadecimal notations.

4 3. M16C Family Documents The following documents were prepared for the M16C family. (1) Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note Application examples of peripheral functions Sample programs Introduction to the basic functions in the M16C family Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to confirm that this is the most current document available.

5 Table of Contents 1. Overview Applications Performance Outline Block Diagram Product List Pin Configuration Pin Description Central Processing Unit (CPU) Data Registers (R0, R1, R2 and R3) Address Registers (A0 and A1) Frame Base Register (FB) Interrupt Table Register (INTB) Program Counter (PC) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Static Base Register (SB) Flag Register (FLG) Carry Flag (C Flag) Debug Flag (D Flag) Zero Flag (Z Flag) Sign Flag (S Flag) Register Bank Select Flag (B Flag) Overflow Flag (O Flag) Interrupt Enable Flag (I Flag) Stack Pointer Select Flag (U Flag) Processor Interrupt Priority Level (IPL) Reserved Area Memory Special Function Register (SFR) Reset Hardware Reset Reset on a Stable Supply Voltage Power-on Reset Voltage Down Detection Reset (Hardware Reset 2) Software Reset Watchdog Timer Reset Oscillation Stop Detection Reset A-1

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7 10.5 System Clock Protection Function Oscillation Stop and Re-oscillation Detect Function Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt) How to Use Oscillation Stop and Re-oscillation Detect Function Protection Interrupt Type of Interrupts Software Interrupts Undefined Instruction Interrupt Overflow Interrupt BRK Interrupt INT Instruction Interrupt Hardware Interrupts Special Interrupts Peripheral Function Interrupts Interrupts and Interrupt Vector Fixed Vector Tables Relocatable Vector Tables Interrupt Control I Flag IR Bit ILVL2 to ILVL0 Bits and IPL Interrupt Sequence Interrupt Response Time Variation of IPL when Interrupt Request is Accepted Saving Registers Returning from an Interrupt Routine Interrupt Priority Interrupt Priority Resolution Circuit INT Interrupt NMI Interrupt Key Input Interrupt Address Match Interrupt Watchdog Timer Count source protective mode Cold start / Warm start DMAC Transfer Cycles Effect of Source and Destination Addresses Effect of BYTE Pin Level A-3

8 Effect of Software Wait Effect of RDY Signal DMA Transfer Cycles DMA Enable DMA Request Channel Priority and DMA Transfer Timing Timers Timer A Timer Mode Event Counter Mode One-shot Timer Mode Pulse Width Modulation (PWM) Mode Timer B Timer Mode Event Counter Mode Pulse Period and Pulse Width Measurement Mode Three-Phase Motor Control Timer Function Serial I/O UARTi (i=0 to 2) Clock Synchronous serial I/O Mode Clock Asynchronous Serial I/O (UART) Mode Special Mode 1 (I2C mode) Special Mode Special Mode 3 (IE mode) Special Mode 4 (SIM Mode) (UART2) SI/O3 and SI/O SI/Oi Operation Timing CLK Polarity Selection Functions for Setting an SOUTi Initial Value A/D Converter Mode Description One-Shot Mode Repeat mode Single Sweep Mode Repeat Sweep Mode Repeat Sweep Mode Function Resolution Select Function Sample and Hold Extended Analog Input Pins External Operation Amplifier (Op-Amp) Connection Mode A-4

9 Current Consumption Reducing Function Output Impedance of Sensor under A/D Conversion D/A Converter CRC Calculation Programmable I/O Ports Port Pi Direction Register (PDi Register, i = 0 to 13) Port Pi Register (Pi Register, i = 0 to 13) Pull-up Control Register 0 to Pull-up Control Register 3 (PUR0 to PUR3 Registers) Port Control Register (PCR Register) Flash Memory Version Memory Map Boot Mode Functions To Prevent Flash Memory from Rewriting ROM Code Protect Function ID Code Check Function CPU Rewrite Mode EW0 Mode EW1 Mode Flash memory Control Register (FIDR, FMR0 and FMR1 registers) Precautions on CPU Rewrite Mode Software Commands Data Protect Function Status Register Full Status Check Standard Serial I/O Mode ID Code Check Function Example of Circuit Application in the Standard Serial I/O Mode Parallel I/O Mode User ROM and Boot ROM Areas ROM Code Protect Function Electrical Characteristics Electrical Characteristics (M16C/62P) Electrical Characteristics (M16C/62PT) Usage Precaution Reset Bus PLL Frequency Synthesizer Power Control Protect A-5

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11 Appendix 1. Package Dimensions 359 Appendix 2. Differences Between M16C/62P and M16C/62A 361 Register Index A-7

12 SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Chip select control register Address match interrupt enable register Protect register Data bank register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 Address match interrupt register 1 Voltage detection register 1 Voltage detection register 2 Chip select expansion control register PLL control register 0 Processor mode register 2 PM0 PM1 CM0 CM1 CSR AIER PRCR DBR CM2 WDTS WDC RMAD0 RMAD1 VCR1 VCR2 CSE PLC0 PM2 001Fh Voltage down detection interrupt register D4INT 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh DMA0 source pointer DMA0 destination pointer DMA0 transfer counter DMA0 control register DMA1 source pointer DMA1 destination pointer DMA1 transfer counter DMA1 control register SAR0 DAR0 TCR0 DM0CON SAR1 DAR1 TCR1 DM1CON NOTES : 1. The blank areas are reserved and cannot be accessed by users h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh INT3 interrupt control register Timer B5 interrupt control register Timer B4 interrupt control register, UART1 BUS collision detection interrupt control register Timer B3 interrupt control register, UART0 BUS collision detection interrupt control register SI/O4 interrupt control register INT5 interrupt control register SI/O3 interrupt control register, INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A/D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register INT3IC TB5IC TB4IC, U1BCNIC TB3IC, U0BCNIC S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC B-1

13 SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h Flash identification register 01B5h Flash memory control register 1 01B6h 01B7h Flash memory control register 0 01B8h 01B9h Address match interrupt register 2 01BAh 01BBh Address match interrupt enable register 2 01BCh 01BDh Address match interrupt register 3 01BEh 01BFh 01C0h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh Peripheral clock select register 025Fh 0260h to 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh FIDR FMR1 FMR0 RMAD2 AIER2 RMAD3 PCLKR NOTES : 1. The blank areas are reserved and cannot be accessed by users. 2. This register is included in the flash memory version. (2) (2) (2) h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh Timer B3, 4, 5 count start flag Timer A1-1 register Timer A2-1 register Timer A4-1 register TA11 TA21 Three-phase PWM control register 0 INVC0 Three-phase PWM control register 1 INVC1 Three-phase output buffer register 0 IDB0 Three-phase output buffer register 1 IDB1 Dead time timer DTT Timer B2 interrupt occurrence frequency set counter ICTB2 Timer B3 register Timer B4 register Timer B5 register Timer B3 mode register Timer B4 mode register Timer B5 mode register Interrupt cause select register 2 Interrupt cause select register SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate generator UART0 special mode register 4 UART0 special ode register 3 UART0 special mode register 2 UART0 special mode register UART1 special mode register 4 UART1 special mode register 3 UART1 special mode register 2 UART1 special mode register UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register TBSR TA41 TB3 TB4 TB5 TB3MR TB4MR TB5MR IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB B-2

14 SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0380h Count start flag TABSR 124, C0h C1h A/D register 0 AD h Clock prescaler reset flag CPSRF 125, C2h 0382h One-shot start flag ONSF C3h A/D register 1 AD h Trigger select register TRGSR 125, C4h 0384h Up-down flag UDF C5h A/D register 2 AD h 03C6h A/D register 3 AD h 03C7h Timer A0 register TA h 03C8h A/D register 4 AD h 03C9h Timer A1 register TA1 124, h 03CAh A/D register 5 AD Ah 03CBh Timer A2 register TA2 124, Bh 03CCh A/D register 6 AD Ch 03CDh Timer A3 register TA Dh 03CEh A/D register 7 AD Eh 03CFh Timer A4 register TA4 124, Fh 03D0h 0390h 03D1h Timer B0 register TB h 03D2h 0392h Timer B1 register TB D3h 0393h 03D4h A/D control register 2 ADCON h 03D5h Timer B2 register TB2 139, h 03D6h A/D control register 0 ADCON h Timer A0 mode register TA0MR D7h A/D control register 1 ADCON h Timer A1 mode register TA1MR 123, D8h D/A register 0 DA h Timer A2 mode register TA2MR 123, D9h 0399h Timer A3 mode register TA3MR DAh D/A register 1 DA Ah Timer A4 mode register TA4MR 123, DBh 039Bh Timer B0 mode register TB0MR DCh D/A control register DACON Ch Timer B1 mode register TB1MR DDh 039Dh Timer B2 mode register TB2MR DEh Port P14 control register PC Eh Timer B2 special mode register TB2SC DFh Pull-up control register 3 PUR Fh 03E0h Port P0 register P A0h UART0 transmit/receive mode register U0MR E1h Port P1 register P A1h UART0 bit rate generator U0BRG E2h Port P0 direction register PD A2h 03E3h Port P1 direction register PD1 235 UART0 transmit buffer register U0TB A3h 03E4h Port P2 register P A4h UART0 transmit/receive control register 0 U0C E5h Port P3 register P A5h UART0 transmit/receive control register 1 U0C E6h Port P2 direction register PD A6h 03E7h Port P3 direction register PD A7h UART0 receive buffer register U0RB E8h Port P4 register P A8h UART1 transmit/receive mode register U1MR E9h Port P5 register P A9h UART1 bit rate generator U1BRG EAh Port P4 direction register PD AAh 03EBh UART1 transmit buffer register U1TB 158 Port P5 direction register PD ABh 03ECh Port P6 register P ACh UART1 transmit/receive control register 0 U1C EDh Port P7 register P ADh UART1 transmit/receive control register 1 U1C EEh Port P6 direction register PD AEh 03EFh Port P7 direction register PD7 235 UART1 receive buffer register U1RB AFh 03F0h Port P8 register P B0h UART transmit/receive control register 2 UCON F1h Port P9 register P B1h 03F2h Port P8 direction register PD B2h 03F3h Port P9 direction register PD B3h 03F4h Port P10 register P B4h 03F5h Port P11 register P B5h 03F6h Port P10 direction register PD B6h 03F7h Port P11 direction register PD B7h 03F8h Port P12 register P B8h DMA0 request cause select register DM0SL F9h Port P13 register P B9h 03FAh Port P12 direction register PD BAh DMA1 request cause select register DM1SL FBh Port P13 direction register PD BBh 03FCh Pull-up control register 0 PUR BCh 03FDh Pull-up control register 1 PUR1 238 CRC data register CRCD BDh 03FEh Pull-up control register 2 PUR BEh 03BFh CRC input register CRCIN FFh Port control register PCR 239 NOTES : 1. The blank areas are reserved and cannot be accessed by users. 2. This register is included in the flash memory version. B-3

15 1. Overview The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the highperformance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 Applications Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile, etc Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

16 1. Overview 1.2 Performance Outline Table 1.1 to table 1.3 list performance outline of M16C/62P group (M16C/62P, M16C/62PT). Table 1.1 Performance Outline of M16C/62P group (M16C/62P) (128-pin version) Item Performance M16C/62P CPU Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operation Mode Single-chip, memory expansion and microprocessor mode Memory Space 1 Mbyte (Available to 4 Mbytes by memory space expansion function) Memory Capacity See Table 1.4 and 1.5 Product List Peripheral Port Input/Output : 113 pins, Input : 1 pin Function Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels Three phase motor control circuit Serial I/O 3 channels Clock synchronous, UART, I 2 C bus (1), IEBus (2) 2 channels Clock synchronous A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels Clock Generation Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function Voltage Detection Circuit Available (option (4) ) Supply Voltage VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(bclk)=24mhz) Electric VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(bclk)=10mhz) Characteristics Power Consumption 14 ma (VCC1=VCC2=5V, f(bclk)=24mhz) 8 ma (VCC1=VCC2=3V, f(bclk)=10mhz) 1.8 µa (VCC1=VCC2=3V, f(xcin)=32khz, wait mode) 0.7 µ A (VCC1=VCC2=3V, stop mode) Flash Memory Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V Version Program and Erase Endurance 100 times (all area) or 1,000 times (user ROM area without block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature 20 to 85 o C 40 to 85 o C (3) Package 128-pin plastic mold LQFP NOTES: 1. I 2 C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Sep., Please inquire about a release schedule. 4. All options are on request basis. page 2

17 1. Overview Table 1.2 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (100-pin version) Item Performance M16C/62P M16C/62PT (Note 4) CPU Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operation Mode Single-chip, memory expansion and Single-chip mode microprocessor mode Memory Space 1 Mbyte (Available to 4 Mbytes by 1 Mbyte memory space expansion function) Memory Capacity See Table 1.4 to 1.7 Product List Peripheral Port Input/Output : 87 pins, Input : 1pin function Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels Three phase motor control circuit Serial I/O 3 channels Clock synchronous, UART, I 2 C bus (1), IEBus (2) 2 channels Clock synchronous A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels Clock Generation Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function Voltage Detection Circuit Available (option (5) ) Absent Electric Supply Voltage VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 VCC1=VCC2=4.0V to 5.5 V characteristics (f(bclk)=24mhz) (f(bclk)=24mhz) VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(bclk)=10mhz) Power Consumption 14 ma (VCC1=VCC2=5V, f(bclk)=24mhz) 14 ma (VCC1=VCC2=5V, f(bclk)=24mhz) 8 ma (VCC1=VCC2=3V, f(bclk)=10mhz) 2.0 µa (VCC1=VCC2=5V, 1.8 µa (VCC1=VCC2=3V, f(xcin)=32khz, wait mode) f(xcin)=32khz, wait mode) 0.8 µ A (VCC1=VCC2=5V, stop mode) 0.7 µ A (VCC1=VCC2=3V, stop mode) Flash memory Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V Version Program and Erase Endurance 100 times (all area) or 1,000 times (user ROM area without block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature 20 to 85 o C T version : 40 to 85 o C 40 to 85 o C (3) V version : 40 to 125 o C Package 100-pin plastic mold QFP, LQFP NOTES: 1. I 2 C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Sep., Please inquire about a release schedule. 4. Use the M16C/62PT on VCC1 = VCC2. 5. All options are on request basis. page 3

18 1. Overview Table 1.3 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (80-pin version) Item Performance M16C/62P M16C/62PT CPU Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operation Mode Single-chip mode Memory Space 1 Mbyte Memory Capacity See Table 1.4 to 1.7 Product List Peripheral Port Input/Output : 70 pins, Input : 1pin function Multifunction Timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer) Timer B : 16 bits x 6 channels (Timer B1 is internal timer) Serial I/O 2 channels Clock synchronous, UART, I 2 C bus (1), IEBus (2) 1 channel Clock synchronous, I 2 C bus (1), IEBus (2) 2 channels Clock synchronous (1 channel is only for transmission) A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels Clock Generating Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function Voltage Detection Circuit Available (option (4) ) Absent Electric Supply Voltage VCC1=3.0 to 5.5V, (f(bclk)=24mhz) VCC1=4.0 to 5.5V, (f(bclk)=24mhz) characteristics VCC1=2.7 to 5.5V, (f(bclk)=10mhz) Power Consumption 14 ma (VCC1=5V, f(bclk)=24mhz) 14 ma (VCC1=5V, f(bclk)=24mhz) 8 ma (VCC1=3V, f(bclk)=10mhz) 2.0 µa (VCC1=5V, 1.8 µa (VCC1=3V, f(xcin)=32khz, wait mode) f(xcin)=32khz, wait mode) 0.8 µ A (VCC1=5V, stop mode) Flash 0.7 µ A (VCC1=3V, stop mode) Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V memory Version Program and Erase Endurance 100 times (all area) or 1,000 times (user ROM area without block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature 20 to 85 o C T version : 40 to 85 o C 40 to 85 o C(option) V version : 40 to 125 o C Package 80-pin plastic mold QFP NOTES : 1. I 2 C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Sep., Please inquire about a release schedule. 4. All options are on request basis. page 4

19 1. Overview 1.3 Block Diagram Figure 1.1 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version, figure 1.2 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit Watchdog timer (15 bits) DMAC (2 channels) D/A converter (8 bits X 2 channels) <VCC2 ports> (4) <VCC1 ports> (4) A/D converter (10 bits X 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O (8 bits X 3 channels) CRC arithmetic circuit (CCITT ) (Polynomial : X 16 +X 12 +X 5 +1) M16C/60 series16-bit CPU core R0H R0L R1H R1L R2 R3 A0 A1 FB SB USP ISP INTB PC FLG System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Clock synchronous serial I/O (8 bits X 2 channels) Memory ROM (1) RAM (2) Multiplier <VCC1 ports> (4) Port P7 Port P8 Port P8_5 Port P9 Port P <VCC1 ports> (4) <VCC2 ports> (4) Port P11 Port P14 Port P12 Port P13 (3) (3) (3) (3) NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. Ports P11 to P14 exist only in 128-pin version. 4. Use M16C/62PT on VCC1= VCC2. Figure 1.1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram page 5

20 1. Overview Port P0 Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Watchdog timer (15 bits) DMAC (2 channels) D/A converter (8 bits X 2 channels) Port P2 Port P3 Port P4 A/D converter (10 bits X 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O (2 channels) UART (1 channel) (3) CRC arithmetic circuit (CCITT ) (Polynomial : X 16 +X 12 +X 5 +1) M16C/60 series16-bit CPU core R0H R1H R2 R3 A0 A1 FB (4) R0L R1L SB USP ISP INTB PC FLG Port P5 Port P6 System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Clock synchronous serial I/O (8 bits X 2 channels) Memory ROM (1) RAM (2) Multiplier (4) Port P7 Port P8 Port P8_5 Port P9 Port P NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. To use a UART2, set the CRD bit in the U2C0 register to 1 (CTS/RTS function disabled). 4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to 1 (output mode), and set the output data to 0 ( L ) using the program. Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram page 6

21 1. Overview 1.4 Product List Tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages, table 1.8 lists the product code of flash memory version and ROMless version for M16C/62P, and table 1.9 lists the product code of flash memory version for M16C/62PT. Figure 1.4 shows the marking diagram of flash memory version and ROMless version for M16C/62P, and figure 1.5 shows the marking diagram of flash memory version for M16C/62PT. Please specify the mark of the mask ROM version at the time of ROM order. Table 1.4 Product List (1) (M16C/62P) As of Sep Type No. ROM Capacity RAM Capacity Package Type Remarks M30622M6P-XXXFP 100P6S-A M30622M6P-XXXGP 48 Kbytes 4 Kbytes 100P6Q-A M30623M6P-XXXGP (D) 80P6S-A M30622M8P-XXXFP 100P6S-A M30622M8P-XXXGP 64 Kbytes 4 Kbytes 100P6Q-A M30623M8P-XXXGP (D) 80P6S-A M30622MAP-XXXFP 100P6S-A M30622MAP-XXXGP 96 Kbytes 5 Kbytes 100P6Q-A M30623MAP-XXXGP M30620MCP-XXXFP M30620MCP-XXXGP M30621MCP-XXXGP M30622MEP-XXXFP M30622MEP-XXXGP M30623MEP-XXXGP M30622MGP-XXXFP M30622MGP-XXXGP M30623MGP-XXXGP M30624MGP-XXXFP M30624MGP-XXXGP M30625MGP-XXXGP M30622MWP-XXXFP M30622MWP-XXXGP M30623MWP-XXXGP M30624MWP-XXXFP M30624MWP-XXXGP M30625MWP-XXXGP M30626MWP-XXXFP M30626MWP-XXXGP M30627MWP-XXXGP (D): Under development (D) (D) (D) (D) (D) (D) (D) 128 Kbytes 192 Kbytes 256 Kbytes 320 Kbytes 10 Kbytes 12 Kbytes 12 Kbytes 20 Kbytes 16 Kbytes 24 Kbytes 31 Kbytes 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A Mask ROM version page 7

22 1. Overview Table 1.5 Product List (2) (M16C/62P) Type No. M30622MHP-XXXFP M30622MHP-XXXGP M30623MHP-XXXGP M30624MHP-XXXFP M30624MHP-XXXGP M30625MHP-XXXGP M30626MHP-XXXFP M30626MHP-XXXGP M30627MHP-XXXGP (D) (D) (D) ROM Capacity ROM Capacity Package Type Remarks 384 Kbytes 16 Kbytes 24 Kbytes 31 Kbytes 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A 100P6S-A 100P6Q-A 128P6Q-A Mask ROM version As of Sep M30626MJP-XXXFP M30626MJP-XXXGP (P) (P) 512 Kbytes 31 Kbytes 100P6S-A 100P6Q-A M30627MJP-XXXGP (P) 128P6Q-A M30622F8PFP M30622F8PGP 64K+4 Kbytes 4 Kbytes 100P6S-A 100P6Q-A M30623F8PGP (D) 80P6S-A M30620FCPFP 100P6S-A M30620FCPGP 128K+4 Kbytes 10 Kbytes 100P6Q-A M30621FCPGP M30624FGPFP (D) 80P6S-A 100P6S-A M30624FGPGP 256K+4 Kbytes 20 Kbytes 100P6Q-A Flash memory version M30625FGPGP 128P6Q-A M30626FHPFP 100P6S-A M30626FHPGP 384K+4 Kbytes 31 Kbytes 100P6Q-A M30627FHPGP 128P6Q-A M30626FJPFP (P) 100P6S-A M30626FJPGP (P) 512K+4 Kbytes 31 Kbytes 100P6Q-A M30627FJPGP (P) 128P6Q-A M30622SPFP M30622SPGP M30620SPFP M30620SPGP 4 Kbytes 10 Kbytes 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A ROMless version (D): Under development (P): Under planning page 8

23 1. Overview Table 1.6 Product List (3) (T version (M16C/62PT)) Type No. M3062CM6T-XXXFP M3062CM6T-XXXGP M3062EM6T-XXXGP M3062CM8T-XXXFP M3062CM8T-XXXGP M3062EM8T-XXXGP M3062CMAT-XXXFP M3062CMAT-XXXGP M3062EMAT-XXXGP M3062AMCT-XXXFP M3062AMCT-XXXGP M3062BMCT-XXXGP M3062CF8TFP M3062CF8TGP M3062AFCTFP M3062AFCTGP M3062BFCTGP M3062JFHTFP M3062JFHTGP (D): Under development (P): Under planning ROM Capacity RAM Capacity Package Type Remarks (D) 100P6S-A (D) 48 Kbytes 4 Kbytes 100P6Q-A (P) (D) (D) (P) (D) (D) (P) (D) (D) (P) (D) (D) (D) (D) (P) (D) (D) 64 Kbytes 96 Kbytes 128 Kbytes 64 Kbytes 128K+4 Kbytes 384K+4 Kbytes 4 Kbytes 5 Kbytes 10 Kbytes 4 Kbytes 10 Kbytes 31 Kbytes 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A Mask ROM version Flash memory version As of Sep T Version (High reliability 85 C Version) Table 1.7 Product List (4) (V version (M16C/62PT)) Type No. M3062CM6V-XXXFP M3062CM6V-XXXGP M3062EM6V-XXXGP M3062CM8V-XXXFP M3062CM8V-XXXGP M3062EM8V-XXXGP M3062CMAV-XXXFP M3062CMAV-XXXGP M3062EMAV-XXXGP M3062AMCV-XXXFP M3062AMCV-XXXGP M3062BMCV-XXXGP M3062AFCVFP M3062AFCVGP M3062BFCVGP M3062JFHVFP M3062JFHVGP (D): Under development (P): Under planning (P) (P) (P) (P) (P) (P) (P) (P) (P) (D) (D) (P) (D) (D) (P) (P) (P) ROM Capacity RAM Capacity Package Type Remarks 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes 128K+4 Kbytes 384K+4 Kbytes 4 Kbytes 4 Kbytes 5 Kbytes 10 Kbytes 10 Kbytes 31 Kbytes 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A 80P6S-A 100P6S-A 100P6Q-A Mask ROM version Flash memory version As of Sep V Version (High reliability 125 C Version) page 9

24 1. Overview Type No. M M H P X X X F P Package type: FP : Package GP : Package 100P6S-A 80P6Q-A, 100P6Q-A, 128P6Q-A ROM No. Omitted for flash memory version and ROMless version Classification P : M16C/62P T : T version (M16C/62PT) V : V version (M16C/62PT) ROM capacity: 6: 48 Kbytes 8: 64 Kbytes A: 96 Kbytes C: 128 Kbytes E: 192 Kbytes G: 256 Kbytes W: 320 Kbytes H: 384 Kbytes J: 512 Kbytes Memory type: M: Mask ROM version F: Flash memory version S: ROMless version Shows RAM capacity, pin count, etc Numeric : M16C/62P Alphabet : M16C/62PT M16C/62P Group M16C Family Figure 1.3 Type No., Memory Size, and Package page 10

25 1. Overview Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P Flash Memory Version Product Code D3 D5 D7 D9 U3 U5 U7 U9 Package Lead-included Lead-free Internal ROM (User ROM Area Without Block 1) Program and Erase Endurance 100 1, ,000 Temperature Range 0 C to 60 C Internal ROM (Block A, Block 1) Program and Erase Endurance , ,000 Temperature Range 0 C to 60 C -40 C to 85 C -20 C to 85 C 0 C to 60 C -40 C to 85 C -20 C to 85 C Operating Ambient Temperature -40 C to 85 C -20 C to 85 C -40 C to 85 C -20 C to 85 C -40 C to 85 C -20 C to 85 C -40 C to 85 C -20 C to 85 C ROMless Version D3 D5 U3 U5 Lead-included Lead-free -40 C to 85 C -20 C to 85 C -40 C to 85 C -20 C to 85 C M1 6C M30626FHPFP B D 5 XXXXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package) Chip version and product code B : Shows chip version. Henceforth, whenever it changes a version, it continues with B, C, and D. D5 : Shows Product code. (See table 1.8 Product Code) Date code seven digits The product without marking of chip version of the flash memory version and the ROMless version corresponds to the chip version A. Figure 1.4 Marking Diagram of Flash Memory version and ROMless version for M16C/62P (Top View) page 11

26 1. Overview Table 1.9 Product Code of Flash Memory version for M16C/62PT Flash Memory Version T Version V Version T Version V Version T Version V Version T Version V Version Product Code B B7 U U7 Package Lead-included Lead-free Internal ROM (User ROM Area Without Block 1) Program and Erase Endurance 100 1, ,000 Temperature Range 0 C to 60 C Internal ROM (Block A, Block 1) Program and Erase Endurance , ,000 Temperature Range 0 C to 60 C -40 C to 85 C -40 C to 125 C 0 C to 60 C -40 C to 85 C -40 C to 125 C Operating Ambient Temperature -40 C to 85 C -40 C to 125 C -40 C to 85 C -40 C to 125 C -40 C to 85 C -40 C to 125 C -40 C to 85 C -40 C to 125 C M1 6C M3062JFHTFP YYY XXXXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package) Date code seven digits Product code. (See table 1.9 Product Code) : Product code B P B F : Product code U B 7 : Product code B7 U 7 : Product code U7 NOTES: 1. : Blank Figure 1.5 Marking Diagram of Flash Memory version for M16C/62PT (Top View) page 12

27 1. Overview 1.5 Pin Configuration Figures 1.6 to 1.9 show the pin configurations (top view). PIN CONFIGURATION (top view) P1_1/D9 P1_2/D10 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_1/TB1IN/SIN3 P9_2/TB2IN/SOUT3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1 = VCC2. P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT (1) P6_7/TXD1/SDA1 P6_6/RXD1/SCL1 Package: 128P6Q-A Figure 1.6 Pin Configuration (Top View) page 13

28 1. Overview PIN CONFIGURATION (top view) P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN <VCC2> (2) M16C/62P Group (M16C/62P, M16C/62PT) <VCC1> (2) P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_1/TB1IN/SIN3 P9_2/TB2IN/SOUT3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1 = VCC2. P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT (1) Package: 100P6S-A Figure 1.7 Pin Configuration (Top View) page 14

29 1. Overview PIN CONFIGURATION (top view) P1_2/D10 P1_1/D9 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 NOTES: P1_3/D11 P1_4/D12 P9_0/TB0IN/CLK3 BYTE P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) P9_4/DA1/TB4IN P9_3/DA0/TB3IN P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P9_1/TB1IN/SIN3 P9_2/TB2IN/SOUT3 CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS VSS P3_0/A8(/-/D7) VCC2 <VCC2> (2) XIN VCC1 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 M16C/62P Group (M16C/62P, M16C/62PT) <VCC1> (2) P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1 = VCC2. P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT (1) P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_2/CLK2/TA1OUT/V Package: 100P6Q-A Figure 1.8 Pin Configuration (Top View) page 15

30 1. Overview PIN CONFIGURATION (top view) P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 P4_2 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN M16C/62P Group (M16C/62P, M16C/62PT) P4_3 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT (1) P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_6/TA3OUT P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_0/TB0IN/CLK3 CNVSS(BYTE) P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN P8_0/TA4OUT P7_7/TA3IN P0_7/AN0_7 P2_0/AN2_0 P2_1/AN2_1 P2_2/AN2_2 P2_3/AN2_3 P2_4/AN2_4 P2_5/AN2_5 P2_6/AN2_6 P2_7/AN2_7 P9_6/ANEX1/SOUT4 NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. Package: 80P6S-A Figure 1.9 Pin Configuration (Top View) page 16

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32 1. Overview Table 1.11 Pin Description (100-pin and 128-pin Version) (2) Signal Name Pin Name I/O Type Power Supply (1) Description Main clock input Main clock output XIN XOUT I O VCC1 VCC1 I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use the external clock, input the Sub clock input Sub clock output BCLK output (2) Clock output INT interrupt input NMI interrupt input Key input interrupt input Timer A Timer B Three-phase motor control output Serial I/O I 2 C mode XCIN XCOUT BCLK CLKOUT INT0 to INT2 INT3 to INT5 NMI KI0 to KI3 TA0OUT to TA4OUT TA0IN to TA4IN ZP TB0IN to TB5IN U, U, V, V, W, W CTS0 to CTS2 RTS0 to RTS2 CLK0 to CLK4 RXD0 to RXD2 SIN3, SIN4 TXD0 to TXD2 SOUT3, SOUT4 CLKS1 SDA0 to SDA2 SCL0 to SCL2 I O O O I I I I I/O I I I O I O I/O I I O O O I/O I/O VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 I : Input O : Output I/O : Input and output clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (3). To use the external clock, input the clock from XCIN and leave XCOUT open. Outputs the BCLK signal. The clock of the same cycle as fc, f8, or f32 is outputted. Input pins for the INT interrupt Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. Input pins for the key input interrupt These are timer A0 to timer A4 I/O pins. (except the output of TAOUT for the N- channel open drain output.) These are timer A0 to timer A4 input pins. Input pin for the Z-phase. These are timer B0 to timer B5 input pins. These are Three-phase motor control output pins. These are send control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data input pins. These are serial data output pins. (except TXD2 for the N-channel open drain output.) These are serial data output pins. This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (except SDA2 for the N-channel open drain output.) These are transfer clock I/O pins. (except SCL2 for the N-channel open drain output.) NOTES: 1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 2. This pin function in M16C/62PT cannot be used. 3. Ask the oscillator maker the oscillation characteristic. page 18