M16C/64 Group Hardware Manual

Transcription

1 REJ9B M6C/64 Group Hardware Manual RENESAS MCU M6C FAMILY / M6C/6 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website ( Rev..5 Revision Date: Mar 7, 29

2 Notes regarding these materials. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. ( ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: () artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges.. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 2. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 3. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.

3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

4 HOW TO USE THIS MANUAL. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the M6C/64 Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type Description Document Title Document No. Datasheet Hardware overview and electrical characteristics M6C/64 Group Datasheet REJ3B26 Hardware manual Hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. M6C/64 Group Hardware Manual Software Manual Descriptions of Instruction set M6C/6, M6C/ 2, M6C/Tiny Series Software Manual Application note Renesas technical update Information on using peripheral functions and application examples Sample programs Information on writing programs in assembly language and C Product specifications, updates on documents, etc. Available from Renesas Technology Web site. This hardware manual REJ9B37

5 2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. () Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word register, bit, or pin to distinguish the three categories. Examples the PM3 bit in the PM register P3_5 pin, VCC pin (2) Notation of Numbers The indication b is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication h is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: b Hexadecimal: EFAh Decimal: 234

6 3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 b2 b b * Symbol Address After Reset XXX XXX h Bit Symbol XXX XXX XXX bits Bit Name b b : XXX : XXX : Do not set. : XXX Function *2 (b2) Nothing is assigned. If necessary, set to. When read, the content is undefined. *3 (b3) Reserved bits Set to. *4 XXX4 XXX bits Function varies according to the operating mode. XXX5 WO XXX6 XXX7 XXX bit : XXX : XXX RO * Blank: Set to or according to the application. : Set to. : Set to. X: Nothing is assigned. *2 : Read and write. RO: Read only. WO: Write only. : Nothing is assigned. *3 Reserved bit Reserved bit. Set to specified value. *4 Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to. Do not set to a value Operation is not guaranteed when a value is set. Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes.

7 4. List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation.

8 Table of Contents SFR Page Reference...B-. Overview.... Features..... Applications....2 Specifications Product List Block Diagram Pin Assignments Pin Functions Central Processing Unit (CPU) Data Registers (R, R, R2 and R3) Address Registers (A and A) Frame Base Registers (FB) Interrupt Table Register (INTB) Program Counter (PC) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Static Base Register (SB) Flag Register (FLG) Carry Flag (C Flag) Debug Flag (D Flag) Zero Flag (Z Flag) Sign Flag (S Flag) Register Bank Select Flag (B Flag) Overflow Flag (O Flag) Interrupt Enable Flag (I Flag) Stack Pointer Select Flag (U Flag) Processor Interrupt Priority Level (IPL) Reserved Space... 6 A-

9 3. Memory Special Function Registers (SFRs) Reset Hardware Reset Reset on a Stable Supply Voltage Power-on Reset Brown-out Reset Software Reset Watchdog Timer Reset Oscillation Stop Detection Reset Internal Space Voltage Detection Circuit Brown-out Reset Low Voltage Detection Interrupt Limitations on Exiting Stop Mode Limitations on Exiting Wait Mode Cold Start-up / Warm Start-up Discrimination Processor Mode Types of Processor Mode Setting Processor Modes Internal Memory Bus Bus Mode Separate Bus Multiplexed Bus Bus Control Address Bus Data Bus Chip Select Signal Read and Write Signals ALE Signal RDY Signal A- 2

10 8.2.7 HOLD Signal BCLK Output External Bus Status When Internal Area IS Accessed Software Wait Memory Space Expansion Function Mbyte Mode Addresses 4h to 3FFFFh, Ch to FFFFFh Addresses 4h to BFFFFh Clock Generation Circuit Type of the Clock Generation Circuit Main Clock Sub Clock khz On-Chip Oscillator Clock (foco-s) PLL Clock CPU Clock and Peripheral Function Clock CPU Clock and BCLK Peripheral Function Clock (f, fc32) Clock Output Function Power Control Normal Operating Mode Wait Mode Stop Mode System Clock Protection Function Oscillation Stop and Re-Oscillation Detect Function Operation When CM27 bit = (Oscillation Stop Detection Reset) Operation When CM27 bit = (Oscillation Stop and Re-oscillation Detect Interrupt) How to Use Oscillation Stop and Re-Oscillation Detect Function Protection Interrupt Type of Interrupts Software Interrupts Undefined Instruction Interrupt... A- 3

11 2.2.2 Overflow Interrupt INT Instruction Interrupt Hardware Interrupts Special Interrupts Peripheral Function Interrupts Interrupts and Interrupt Vector Fixed Vector Tables Relocatable Vector Tables Interrupt Control I Flag IR Bit Bits ILVL2 to ILVL and IPL Interrupt Sequence Interrupt Response Time Variation of IPL when Interrupt Request IS Accepted Saving Registers Returning from an Interrupt Routine Interrupt Priority Interrupt Priority Level Select Circuit INT Interrupt NMI Interrupt Key Input Interrupt Address Match Interrupt Watchdog Timer Count Source Protection Mode Disabled Count Source Protection Mode Enabled DMAC Transfer Cycles Effect of Source and Destination Addresses Effect of BYTE Pin Level Effect of Software Wait Effect of RDY Signal DMA Transfer Cycles DMA Enabled A- 4

12 4.4 DMA Request Channel Priority and DMA Transfer Timing Timers Timer A Timer Mode Event Counter Mode One-Shot Timer Mode PWM Mode (Pulse Width Modulation Mode) Timer B Timer Mode Event Counter Mode Pulse Period and Pulse Width Measurement Modes Three-Phase Motor Control Timer Function Serial Interface UARTi (i = to 2, 5 to 7) Clock Synchronous Serial I/O Mode Clock Asynchronous Serial I/O (UART) Mode Special Mode (I 2 C mode) Special Mode Special Mode 3 (IE mode) Special Mode 4 (SIM Mode) (UART2) SI/O3 and SI/O SI/Oi Operation Timing CLK Polarity Selection Functions for Setting an SOUTi Initial Value Functions for Selecting SOUTi State after Transmission A/D Converter Mode Description One-Shot Mode Repeat Mode Single Sweep Mode Repeat Sweep Mode Repeat Sweep Mode A- 5

13 8.2 Conversion Rate Extended Analog Input Pins Current Consumption Reducing Function External Sensor D/A Converter Summary CRC Operation Programmable I/O Ports Port Pi Direction Register (PDi Register, i = to ) Port Pi Register (Pi Register, i = to ) Pull-up Control Register to Pull-up Control Register 2 (Registers PUR to PUR2) Port Control Register (PCR Register) Flash Memory Version Memory Map Boot Mode User Boot Function Functions to Prevent Flash Memory from Rewriting ROM Code Protect Function ID Code Check Function Forced Erase Function Standard Serial I/O Mode Disable Function CPU Rewrite Mode EW Mode EW Mode Flash Memory Control Register (Registers FMR, FMR, FMR2 and FMR6) Precautions on CPU Rewrite Mode Software Commands Data Protect Function Status Register Full Status Check Standard Serial I/O Mode A- 6

14 22.4. ID Code Check Function Example of Circuit Application in the Standard Serial I/O Mode Parallel I/O Mode ROM Code Protect Function Electrical Characteristics Electrical Characteristics Precautions SFR Register Settings Reset VCC CNVSS Bus PLL Frequency Synthesizer Power Control Protect Interrupt Reading address h SP Setting NMI Interrupt Changing an Interrupt Generate Factor INT Interrupt Rewriting the Interrupt Control Register Watchdog Timer Interrupt DMAC Write to the DMAE Bit in the DMiCON Register (i = to 3) DMAC Channel Priority Timers Timer A Timer B Serial Interface Clock Synchronous Serial I/O UART (Clock Asynchronous Serial I/O) Mode Special Mode (I2C Mode) A- 7

15 24..4 Special Mode 4 (SIM Mode) SI/O3, SI/O A/D Converter Repeat Mode, Repeat Sweep Mode, and Repeat Sweep Mode Programmable I/O Ports Flash Memory Version Functions to Inhibit Rewriting Flash Memory Stop Mode Wait Mode Low Power Consumption Mode, On-Chip Oscillator Low Power Consumption Mode Writing Command and Data Program Command Lock Bit Program Command Operation Speed Instructions Inhibited against Use Interrupts How to Access Writing DMA transfer Programming / Erasing Endurance and Execution Time When Entering to Boot Mode Noise Appendix.Package Dimensions Appendix 2.Difference Between M6C/64 and M6C/62P REGISTER INDEX 382 A- 8

16 SFR Page Reference Address Register Symbol Page h h 2h 3h 4h Processor Mode Register PM 48 5h Processor Mode Register PM 49 6h System Clock Control Register CM 76 7h System Clock Control Register CM 77 8h Chip Select Control Register CSR 55 9h Ah Protect Register PRCR 98 Bh Data Bank Register DBR 67 Ch Oscillation Stop Detection Register CM2 78 Dh Eh Fh h Program 2 Area Control Register PRG2C 5 h 2h Peripheral Clock Select Register PCLKR 79 3h 4h 5h Clock Prescaler Reset Flag CPSRF 42 6h 7h 8h Reset Source Determine Flag RSTFR 46 9h Voltage Detection 2 Circuit Flag Register VCR 38 Ah Voltage Detection Circuit Operation Enable VCR2 Register 38 Bh Chip Select Expansion Control Register CSE 62 Ch PLL Control Register PLC 8 Dh Eh Processor Mode Register 2 PM2 79 Fh Low Voltage Detection Interrupt Register D4INT 39 2h 2h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah Voltage Monitor Circuit Control Register VWC 4 2Bh 2Ch 2Dh 2Eh 2Fh 3h 3h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 4h 4h NOTE:. Blank columns are all reserved space. No access is allowed. Address Register Symbol Page 42h INT7 Interrupt Control Register INT7IC 6 43h INT6 Interrupt Control Register INT6IC 6 44h INT3 Interrupt Control Register INT3IC 6 45h Timer B5 Interrupt Control Register TB5IC 5 46h Timer B4 Interrupt Control Register, UART BUS Collision Detection Interrupt Control Register TB4IC, UBCNIC 5 47h 48h 49h 4Ah Timer B3 Interrupt Control Register, UART BUS Collision Detection Interrupt Control Register SI/O4 Interrupt Control Register, INT5 Interrupt Control Register SI/O3 Interrupt Control Register, INT4 Interrupt Control Register UART2 BUS Collision Detection Interrupt Control Register TB3IC, 5 UBCNIC S4IC, INT5IC 6 S3IC, INT4IC 6 BCNIC 6 4Bh DMA Interrupt Control Register DMIC 5 4Ch DMA Interrupt Control Register DMIC 5 4Dh Key Input Interrupt Control Register KUPIC 5 4Eh A/D Conversion Interrupt Control Register ADIC 5 4Fh UART2 Transmit Interrupt Control Register S2TIC 5 5h UART2 Receive Interrupt Control Register S2RIC 5 5h UART Transmit Interrupt Control Register STIC 5 52h UART Receive Interrupt Control Register SRIC 5 53h UART Transmit Interrupt Control Register STIC 5 54h UART Receive Interrupt Control Register SRIC 5 55h Timer A Interrupt Control Register TAIC 5 56h Timer A Interrupt Control Register TAIC 5 57h Timer A2 Interrupt Control Register TA2IC 5 58h Timer A3 Interrupt Control Register TA3IC 5 59h Timer A4 Interrupt Control Register TA4IC 5 5Ah Timer B Interrupt Control Register TBIC 5 5Bh Timer B Interrupt Control Register TBIC 5 5Ch Timer B2 Interrupt Control Register TB2IC 5 5Dh INT Interrupt Control Register INTIC 6 5Eh INT Interrupt Control Register INTIC 6 5Fh INT2 Interrupt Control Register INT2IC 6 6h 6h 62h 63h 64h 65h 66h 67h 68h 69h DMA2 Interrupt Control Register DM2IC 5 6Ah DMA3 Interrupt Control Register DM3IC 5 6Bh UART5 BUS Collision Detection Interrupt Control U5BCNIC 5 Register 6Ch UART5 Transmit Interrupt Control Register S5TIC 5 6Dh UART5 Receive Interrupt Control Register S5RIC 5 6Eh UART6 BUS Collision Detection Interrupt U6BCNIC Control Register 5 6Fh UART6 Transmit Interrupt Control Register S6TIC 5 7h UART6 Receive Interrupt Control Register S6RIC 5 7h UART7 BUS Collision Detection Interrupt U7BCNIC 5 Control Register 72h UART7 Transmit Interrupt Control Register S7TIC 5 73h UART7 Receive Interrupt Control Register S7RIC 5 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh D8h to D7Fh B -

17 Address Register Symbol Page 8h DMA Source Pointer SAR 29 8h 82h 83h 84h DMA Destination Pointer DAR 29 85h 86h 87h 88h DMA Transfer Counter TCR 29 89h 8Ah 8Bh 8Ch DMA Control Register DMCON 29 8Dh 8Eh 8Fh 9h DMA Source Pointer SAR 29 9h 92h 93h 94h DMA Destination Pointer DAR 29 95h 96h 97h 98h DMA Transfer Counter TCR 99h 9Ah 9Bh 9Ch DMA Control Register DMCON Dh 9Eh 9Fh Ah DMA2 Source Pointer SAR2 29 Ah A2h A3h A4h DMA2 Destination Pointer DAR2 29 A5h A6h A7h A8h DMA2 Transfer Counter TCR2 29 A9h AAh ABh ACh DMA2 Control Register DM2CON 28 ADh AEh AFh Bh DMA3 Source Pointer SAR3 29 Bh B2h B3h B4h DMA3 Destination Pointer DAR3 29 B5h B6h B7h B8h DMA3 Transfer Counter TCR3 29 B9h BAh BBh BCh DMA3 Control Register DM3CON 29 BDh BEh BFh Ch Ch C2h Address Register Symbol Page C3h C4h C5h C6h C7h C8h Timer B Count Source Select Register TBCS 58 C9h Timer B Count Source Select Register TBCS 58 CAh CBh CCh CDh CEh CFh Dh Timer A Count Source Select Register TACS 42 Dh Timer A Count Source Select Register TACS 42 D2h Timer A Count Source Select Register 2 TACS2 43 D3h D4h D5h Timer A Waveform Output Function Select TAPOFS 43 Register D6h D7h D8h D9h DAh DBh DEh DCh DDh DFh Eh Eh E2h E3h E4h E5h E6h E7h E8h Timer B Count Source Select Register 2 TBCS2 58 E9h Timer B Count Source Select Register 3 TBCS3 58 EAh EBh ECh EDh EEh EFh Fh Fh F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh 2h 2h 22h 23h 24h NOTE:. Blank columns are all reserved space. No access is allowed. B - 2

18 Address Register Symbol Page 25h Interrupt Source Select Register 3 IFSR3A 4 26h Interrupt Source Select Register 2 IFSR2A 4 27h Interrupt Source Select Register IFSR 3 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh Address Match Interrupt Enable Register AIER 7 2Fh Address Match Interrupt Enable Register 2 AIER2 7 2h Address Match Interrupt Register RMAD 7 2h 22h 23h 24h Address Match Interrupt Register RMAD 7 25h 26h 27h 28h Address Match Interrupt Register 2 RMAD2 7 29h 2Ah 2Bh 2Ch Address Match Interrupt Register 3 RMAD3 7 2Dh 2Eh 2Fh 22h Flash Memory Control Register FMR h Flash Memory Control Register FMR h Flash Memory Control Register 2 FMR h 224h 225h 226h 227h 228h 229h 22Ah 22Bh 22Ch 22Dh 22Eh 22Fh 23h Flash Memory Control Register 6 FMR h 232h 233h 234h 235h 236h 237h 238h 239h 23Ah 23Bh 23Ch 23Dh 23Eh 23Fh 24h 24h 242h 243h 244h UART Special Mode Register 4 USMR h UART Special Mode Register 3 USMR h UART Special Mode Register 2 USMR h UART Special Mode Register USMR h UART Transmit/Receive Mode Register UMR 8 Address Register Symbol Page 249h UART Bit Rate Register UBRG 8 24Ah UART Transmit Buffer Register UTB 8 24Bh 24Ch UART Transmit/Receive Control Register UC 82 24Dh UART Transmit/Receive Control Register UC 83 24Eh UART Receive Buffer Register URB 8 24Fh 25h UART Transmit/Receive Control Register 2 UCON 84 25h 252h 253h 254h UART Special Mode Register 4 USMR h UART Special Mode Register 3 USMR h UART Special Mode Register 2 USMR h UART Special Mode Register USMR h UART Transmit/Receive Mode Register UMR 8 259h UART Bit Rate Register UBRG 8 25Ah UART Transmit Buffer Register UTB 7 25Bh 25Ch UART Transmit/Receive Control Register UC 8 25Dh UART Transmit/Receive Control Register UC 83 25Eh UART Receive Buffer Register URB 25Fh 26h 26h 262h 263h 264h UART2 Special Mode Register 4 U2SMR h UART2 Special Mode Register 3 U2SMR h UART2 Special Mode Register 2 U2SMR h UART2 Special Mode Register U2SMR h UART2 Transmit/Receive Mode Register U2MR 8 269h UART2 Bit Rate Register U2BRG 8 26Ah UART2 Transmit Buffer Register U2TB 7 26Bh 26Ch UART2 Transmit/Receive Control Register U2C 82 26Dh UART2 Transmit/Receive Control Register U2C 83 26Eh UART2 Receive Buffer Register U2RB 8 26Fh 27h SI/O3 Transmit/Receive Register S3TRR h 272h SI/O3 Control Register S3C h SI/O3 Bit Rate Register S3BRG h SI/O4 Transmit/Receive Register S4TRR h 276h SI/O4 Control Register S4C h SI/O4 Bit Rate Register S4BRG h SI/O34 Control Register 2 S34C h 27Ah 27Bh 27Ch 27Dh 27Eh 27Fh 28h 28h 282h 283h 284h UART5 Special Mode Register 4 U5SMR h UART5 Special Mode Register 3 U5SMR h UART5 Special Mode Register 2 U5SMR h UART5 Special Mode Register U5SMR h UART5 Transmit/Receive Mode Register U5MR 8 289h UART5 Bit Rate Register U5BRG 8 NOTE:. Blank columns are all reserved space. No access is allowed. B - 3

19 Address Register Symbol Page 28Ah UART5 Transmit Buffer Register U5TB 8 28Bh 28Ch UART5 Transmit/Receive Control Register U5C 82 28Dh UART5 Transmit/Receive Control Register U5C 83 28Eh UART5 Receive Buffer Register U5RB 7 28Fh 29h 29h 292h 293h 294h UART6 Special Mode Register 4 U6SMR h UART6 Special Mode Register 3 U6SMR h UART6 Special Mode Register 2 U6SMR h UART6 Special Mode Register U6SMR h UART6 Transmit/Receive Mode Register U6MR 8 299h UART6 Bit Rate Register U6BRG 8 29Ah UART6 Transmit Buffer Register U6TB 8 29Bh 29Ch UART6 Transmit/Receive Control Register U6C 82 29Dh UART6 Transmit/Receive Control Register U6C 83 29Eh UART6 Receive Buffer Register U6RB 8 29Fh 2Ah 2Ah 2A2h 2A3h 2A4h UART7 Special Mode Register 4 U7SMR4 86 2A5h UART7 Special Mode Register 3 U7SMR3 85 2A6h UART7 Special Mode Register 2 U7SMR2 85 2A7h UART7 Special Mode Register U7SMR 84 2A8h UART7 Transmit/Receive Mode Register U7MR 8 2A9h UART7 Bit Rate Register U7BRG 8 2AAh UART7 Transmit Buffer Register U7TB 8 2ABh 2ACh UART7 Transmit/Receive Control Register U7C 82 2ADh UART7 Transmit/Receive Control Register U7C 83 2AEh UART7 Receive Buffer Register U7RB 8 2AFh 2Bh to 2FFh 3h Timer B3,4,5 Count Start Flag TBSR 57 3h 32h Timer A- Register TA 7 33h 34h Timer A2- Register TA2 7 35h 36h Timer A4- Register TA4 7 37h 38h Three-Phase PWM Control Register INVC 68 39h Three-Phase PWM Control Register INVC 69 3Ah Three-Phase Output Buffer Register IDB 7 3Bh Three-Phase Output Buffer Register IDB 7 3Ch Dead Time Timer DTT 7 3Dh Timer B2 Interrupt Generation Frequency Set ICTB2 Counter 7 3Eh 3Fh 3h Timer B3 Register TB3 56 3h 32h Timer B4 Register TB h 34h Timer B5 Register TB h 36h 37h 38h 39h Address Register Symbol Page 3Ah 3Bh Timer B3 Mode Register TB3MR 56 3Ch Timer B4 Mode Register TB4MR 56 3Dh Timer B5 Mode Register TB5MR 56 3Eh 3Fh 32h Count Start Flag TABSR 57 32h 322h One-Shot Start Flag ONSF 4 323h Trigger Select Register TRGSR 4 324h Up/Down Flag UDF 4 325h 326h Timer A Register TA h 328h Timer A Register TA h 32Ah Timer A2 Register TA Bh 32Ch Timer A3 Register TA Dh 32Eh Timer A4 Register TA Fh 33h Timer B Register TB 56 33h 332h Timer B Register TB h 334h Timer B2 Register TB h 336h Timer A Mode Register TAMR h Timer A Mode Register TAMR h Timer A2 Mode Register TA2MR h Timer A3 Mode Register TA3MR 39 33Ah Timer A4 Mode Register TA4MR 39 33Bh Timer B Mode Register TBMR 56 33Ch Timer B Mode Register TBMR 56 33Dh Timer B2 Mode Register TB2MR 56 33Eh Timer B2 Special Mode Register TB2SC 7 33Fh 34h 34h 342h 343h 344h 345h 346h 347h 348h 349h 34Ah 34Bh 34Ch 34Dh 34Eh 34Fh 35h 35h 352h 353h 354h 355h 356h 357h 358h 359h 35Ah 35Bh NOTE:. Blank columns are all reserved space. No access is allowed. B - 4

20 Address Register Symbol Page 35Ch 35Dh 35Eh 35Fh 36h Pull-Up Control Register PUR 26 36h Pull-Up Control Register PUR h Pull-Up Control Register 2 PUR h 364h 365h 366h Port Control Register PCR h 368h 369h 36Ah 36Bh 36Ch 36Dh 36Eh 36Fh 37h 37h 372h 373h 374h 375h 376h 377h 378h 379h 37Ah 37Bh 37Ch Count Source Protection Mode Register CSPR 2 37Dh Watchdog Timer Reset Register WDTR 9 37Eh Watchdog Timer Start Register WDTS 9 37Fh Watchdog Timer Control Register WDC 9 38h 38h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 39h DMA2 Source Select Register DM2SL 25 39h 392h DMA3 Source Select Register DM3SL h 394h 395h 396h 397h 398h DMA Source Select Register DMSL h 39Ah DMA Source Select Register DMSL 25 39Bh 39Ch 39Dh 39Eh 39Fh Address Register Symbol Page 3Ah 3Ah 3A2h 3A3h 3A4h 3A5h 3A6h 3A7h 3A8h 3A9h 3AAh 3ABh 3ACh 3ADh 3AEh 3AFh 3Bh 3Bh 3B2h 3B3h 3B4h 3B5h 3B6h 3B7h 3B8h 3B9h 3BAh 3BBh 3BCh CRC Data Register CRCD 25 3BDh 3BEh CRC Input Register CRCIN 25 3BFh 3Ch A/D Register AD 235 3Ch 3C2h A/D Register AD 235 3C3h 3C4h A/D Register 2 AD C5h 3C6h A/D Register 3 AD C7h 3C8h A/D Register 4 AD C9h 3CAh A/D Register 5 AD CBh 3CCh A/D Register 6 AD CDh 3CEh A/D Register 7 AD CFh 3Dh 3Dh 3D2h 3D3h 3D4h A/D Control Register 2 ADCON D5h 3D6h A/D Control Register ADCON 234 3D7h A/D Control Register ADCON 234 3D8h D/A Register DA 25 3D9h 3DAh D/A Register DA 25 3DBh 3DCh D/A Control Register DACON 25 3DDh 3DEh 3DFh 3Eh Port P Register P 26 3Eh Port P Register P 26 3E2h Port P Direction Register PD 259 3E3h Port P Direction Register PD 259 B - 5 NOTE:. Blank columns are all reserved space. No access is allowed.

21 Address Register Symbol Page 3E4h Port P2 Register P2 26 3E5h Port P3 Register P3 26 3E6h Port P2 Direction Register PD E7h Port P3 Direction Register PD E8h Port P4 Register P4 26 3E9h Port P5 Register P5 26 3EAh Port P4 Direction Register PD EBh Port P5 Direction Register PD ECh Port P6 Register P6 26 3EDh Port P7 Register P7 26 3EEh Port P6 Direction Register PD EFh Port P7 Direction Register PD Fh Port P8 Register P8 26 3Fh Port P9 Register P9 26 3F2h Port P8 Direction Register PD F3h Port P9 Direction Register PD F4h Port P Register P 26 3F5h 3F6h Port P Direction Register PD 259 3F7h 3F8h 3F9h 3FAh 3FBh 3FCh 3FDh 3FEh 3FFh Dh to D7FFh OFS Optional Feature Select Address OFS 272 NOTE:. Blank columns are all reserved space. No access is allowed. B - 6

22 RENESAS MCU. Overview. Features The M6C/64 Group MCUs incorporate the M6C/6 Series CPU core and flash memory, employing sophisticated instructions for a high level of efficiency. With Mbyte of address space (expandable to 4 Mbyte), this MCU is capable of executing instructions at high speed. In addiditon, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the M6C/64 Group supports operating modes that allow additional power control. The MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components... Applications Audio, cameras, television, home appliance, office equipment, communication equipment, portable equipment, industrial equipment, etc. Page of 383

23 . Overview.2 Specifications Tables. and.2 list Specifications Outline. Table. Specifications () Item Function Specification CPU Central processing unit M6C/6 core (multiplier: 6-bit 6-bit 32 bits, multiply and accumulate instruction: bits) Number of basic instructions: 9 Minimum instruction execution time: 4. ns ( f(bclk) = 25 MHz, VCC = VCC2 = 2.7 to 5.5 V) Operating modes: Single-chip, memory expansion, and microprocessor Memory ROM, RAM, See Table.3 Product List. data flash Voltage Voltage detection circuit Low-voltage detection unit Detection Clock Clock generation circuit 4 circuits: Main clock, sub clock, on-chip oscillator (25 khz), PLL frequency synthesize Oscillation stop detection: Main clock oscillation stop detection and reoscillation detection function Frequency divider circuit: Divide ratio selectable from, 2, 4, 8 and 6 Low-power consumption modes: Wait mode, stop mode External Bus Bus and memory expansion Address space: Mbyte Expansion External bus interface: to 3 waits states, chip select 4 outputs, memory area expansion function (up to 4 Mbytes) Bus format: Separate bus or multiplexed bus selectable, data bus width selectable (8 or 6 bits), number of address buses selectable (2, 6, or 2 buses) I/O Ports Programmable I/O ports CMOS I/O ports: 85, selectable pull-up resistor Nch open drain ports: 3 Interrupts Interrupt vectors: 7 External interrupt input: 3 (NMI, INT 8, key input 4) Interrupt priority levels: 7 Watchdog Timer 5 bits (with prescaler) Automatic reset start function selectable DMA DMAC 4 channels, cycle steal mode Trigger sources: 43 Transfer modes: 2 (single transfer, repeat transfer) Timer Timer A 6-bit timer 5 Timer mode, event counter mode, one shot timer mode, pulse width modulation (PWM) mode Event counter two-phase pulse signal processing (two-phase encoder input) 3 channels Timer B 6-bit timer 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Serial Interface Timer functions for threephase motor control UART to UART2, UART5 to UART7 SI/O3, SI/O4 Note:. IEBus is a registered trademark of NEC Electronics Corporation. Three-phase inverter control (timer A, timer A2, timer A4, timer B2), On-chip dead time timer Clock synchronous/asynchronous 6 channels I 2 C-bus, IEBus (), special mode 2, SIM (UART2) Clock synchronization only 2 channels Page 2 of 383

24 . Overview Table.2 Specifications (2) Item Function Specification A/D Converter -bit resolution 26 channels, including sample and hold function, Conversion time:.72 µs D/A Converter 8-bit resolution 2 CRC Calculation Circuit CRC-CCITT (X 6 + X 2 + X 5 + ) compliant Flash Memory Programming and erasure power supply voltage: 2.7 V to 5.5 V Programming and erasure endurance: times Program security: ROM code protect, ID code check Debug Function Functions on-chip debug, on-board flash rewrite function, address match 4 Operation Frequency/Supply Voltage 25 MHz/VCC = VCC2 = 2.7 to 5.5 V Power Consumption 2 ma (25 MHz/VCC = VCC2 = 3 V)TBD 3. µa(vcc = VCC2 = 3 V, in stop mode) Operating Temperature -2 C to 85 C, -4 C to 85 C Package -pin QFP: PRQPJD-B (Previous package code: P6F-A) -pin LQFP: PLQPKB-A (Previous package code: P6Q-A) Page 3 of 383

25 . Overview.3 Product List Table.3 lists product information. Figure. shows part numbers, memory sizes, and packages. Figure.2 shows a Marking Diagram of Flash Memory Version (Top View). Table.3 Part No. Product List (D) : Under development Program ROM ROM Capacity Program ROM 2 Data Flash Note:. Previous package codes are as follows. PRQPJD-B: P6F-A, PLQPKB-A: P6Q-A RAM Capacity Package Code Remarks R5F3646NFA (D) 28 Kbytes 6 Kbytes 4 Kbytes 2 Kbytes PRQPJD-B Operating R5F3646NFB (D) 2 blocks PLQPKB-A temperature R5F364DNFA (D) 256 Kbytes 6 Kbytes 4 Kbytes 6 Kbytes PRQPJD-B -2 C to 85 C R5F364DNFB (D) 2 blocks PLQPKB-A R5F364MNFA (D) 52 Kbytes 6 Kbytes 4 Kbytes 3 Kbytes PRQPJD-B R5F364MNFB (D) 2 blocks PLQPKB-A R5F3646DFA (D) 28 Kbytes 6 Kbytes 4 Kbytes 2 Kbytes PRQPJD-B Operating R5F3646DFB (D) 2 blocks PLQPKB-A temperature R5F364DDFA (D) 256 Kbytes 6 Kbytes 4 Kbytes 6 Kbytes PRQPJD-B -4 C to 85 C R5F364DDFB (D) 2 blocks PLQPKB-A R5F364MDFA (D) 52 Kbytes 6 Kbytes 4 Kbytes 3 Kbytes PRQPJD-B R5F364MDFB (D) 2 blocks PLQPKB-A Part No. R 5 F D FA Package type: FA: Package PRQPJD-B (P6F-A) FB: Package PLQPKB-A (P6Q-A) Property Code N: Operating temperature -2 C to 85 C D: Operating temperature -4 C to 85 C Memory capacity Program ROM / RAM 6: 28 Kbytes / 2 Kbytes D: 256 Kbytes / 6 Kbytes M: 52 Kbytes / 3 Kbytes M6C / 64 Group 6-bit microcomputer Memory type: F: Flash memory Renesas microcomputer Renesas semiconductor Figure. Correspondence of Part No., with Memory Size and Package Page 4 of 383

26 . Overview M 6 C R5F3646DFA XXXXXXX Part No. (See Figure. Correspondence of Part No., with Memory Size and Package) Date code seven digits Figure.2 Marking Diagram of Flash Memory Version (Top View) Page 5 of 383

27 . Overview.4 Block Diagram Figure.3 is a M6C/64 Group Block Diagram Port P Port P Port P2 Port P3 Port P4 Port P5 VCC2 ports Internal peripheral functions Timer (6-bit) Outputs (Timer A): 5 Inputs (Timer B): 6 Three-phase motor control circuit UART or clock synchronous serial I/O (6 channels) Clock synchronous serial I/O (8 bits 2 channels) Clock generation circuits XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator (25 khz) DMAC (4 channels) Watchdog timer (5 bits) CRC calculation circuit (CCITT) (Polynomial X 6 + X 2 + X 5 + ) A/D converter ( bits 26 channels) D/A converter (8 bits 2 channels) M6C/6 Series CPU core RH RL RH RL R2 R3 A A FB SB USP ISP INTB PC FLG Memory ROM () RAM (2) Multiplier VCC ports Port P Port P9 Port P8 Port P Port P6 8 Notes :. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure.3 Block Diagram Page 6 of 383

28 . Overview.5 Pin Assignments Figures.4 and.5 show pin assignments (top view). Tables.4 and.5list Pin Names, for -Pin Package. (3) P_/CTS6/RTS6/D8 P_/CLK6/D9 P_2/RXD6/SCL6/D P_3/TXD6/SDA6/D P_4/D2 P_5/INT3/D3 P_6/INT4/D4 P_7/INT5/D5 P2_/AN2_/A, [A/D], A P2_/AN2_/A, [A/D], [A/D] P2_2/AN2_2/A2, [A2/D2], [A2/D] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_6/AN2_6/A6, [A6/D6], [A6/D5] P2_7/AN2_7/A7, [A7/D7], [A7/D6] VSS P3_/A8 [A8/D7] VCC2 P3_/A9 P3_2/A P3_3/A P3_4/A2 P3_5/A3 P3_6/A4 P3_7/A5 P4_/A6 P4_/A7 P4_2/A8 P4_3/A9 P_7/AN_7/D7 P_6/AN_6/D6 P_5/AN_5/D5 P_4/AN_4/D4 P_3/AN_3/D3 P_2/AN_2/D2 P_/AN_/D P_/AN_/D P_7/AN7/KI3 P_6/AN6/KI2 P_5/AN5/KI P_4/AN4/KI P_3/AN3 P_2/AN2 P_/AN AVSS P_/AN VREF AVCC P9_7/ADTRG/SIN VCC2 ports M6C/64 Group PRQPJD-B (P6F-A) (top view) VCC ports P4_4/CTS7/RTS7/CS P4_5/CLK7/CS P4_6/RXD7/SCL7/CS2 P4_7/TXD7/SDA7/CS3 P5_/WRL/WR P5_/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_/CTS/RTS P6_/CLK P6_2/RXD/SCL P6_3/TXD/SDA P6_4/CTS/RTS/CTS/CLKS P6_5/CLK P6_6/RXD/SCL P6_7/TXD/SDA P9_6/ANEX/SOUT4 P9_5/ANEX/CLK4 P9_4/DA/TB4IN P9_3/DA/TB3IN P9_/TBIN/SIN3 P9_2/TB2IN/SOUT3 P9_/TBIN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC P8_5/NMI/SD () P8_4/INT2/ZP P8_3/INT P8_2/INT P8_/TA4IN/U/CTS5/RTS5 P8_/TA4OUT/U/RXD5/SCL5 P7_7/TA3IN/CLK5 P7_6/TA3OUT/TXD5/SDA5 Notes:. N-channel open-drain output. 2. Check the position of Pin by referring to appendix, Package Dimensions. 3. Symbols in brackets [ ] represent a functional signal as a whole. P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TAIN/V P7_2/CLK2/TAOUT/V P7_/RXD2/SCL2/TAIN/TB5IN () P7_/TXD2/SDA2/TAOUT () Figure.4 Pin Assignment (Top View) Page 7 of 383

29 . Overview (3) P_3/TXD6/SDA6/D P_4/D2 P_5/INT3/D3 P_6/INT4/D4 P_7/INT5/D5 P2_/AN2_/A, [A/D], A P2_/AN2_/A, [A/D], [A/D] P2_2/AN2_2/A2, [A2/D2], [A2/D] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_6/AN2_6/A6, [A6/D6], [A6/D5] P2_7/AN2_7/A7, [A7/D7], [A7/D6] VSS P3_/A8 [A8/D7] VCC2 P3_/A9 P3_2/A P3_3/A P3_4/A2 P3_5/A3 P3_6/A4 P3_7/A5 P4_/A6 P4_/A7 P_2/RXD6/SCL6/D P_/CLK6/D9 P_/CTS6/RTS6/D8 P_7/AN_7/D7 P_6/AN_6/D6 P_5/AN_5/D5 P_4/AN_4/D4 P_3/AN_3/D3 P_2/AN_2/D2 P_/AN_/D P_/AN_/D P_7/AN7/KI3 P_6/AN6/KI2 P_5/AN5/KI P_4/AN4/KI P_3/AN3 P_2/AN2 P_/AN AVSS P_/AN VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX/SOUT4 P9_5/ANEX/CLK VCC2 ports M6C/64 Group PLQPKB-A (P6Q-A) (top view) VCC ports P4_2/A8 P4_3/A9 P4_4/CTS7/RTS7/CS P4_5/CLK7/CS P4_6/RXD7/SCL7/CS2 P4_7/TXD7/SDA7/CS3 P5_/WRL/WR P5_/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_/CTS/RTS P6_/CLK P6_2/RXD/SCL P6_3/TXD/SDA P6_4/CTS/RTS/CTS/CLKS P6_5/CLK P6_6/RXD/SCL P6_7/TXD/SDA P7_/TXD2/SDA2/TAOUT () P7_/RXD2/SCL2/TAIN/TB5IN () P7_2/CLK2/TAOUT/V P9_4/DA/TB4IN P9_3/DA/TB3IN P9_/TBIN/SIN3 P9_2/TB2IN/SOUT3 P9_/TBIN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC P8_5/NMI/SD () P8_4/INT2/ZP P8_3/INT P8_2/INT Notes:. N-channel open-drain output. 2. Check the position of Pin by referring to appendix, Package Dimensions. 3. Symbols in brackets [ ] represent a functional signal as a whole. P8_/TA4IN/U/CTS5/RTS5 P8_/TA4OUT/U/RXD5/SCL5 P7_7/TA3IN/CLK5 P7_6/TA3OUT/TXD5/SDA5 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TAIN/V Figure.5 Pin Assignment (Top View) Page 8 of 383

30 . Overview Table.4 Pin Names for -Pin Package() Pin No. I/O Pin Functions for of Peripheral Modules Control Pin Port FA FB Interrupt Timer Serial interface A/D converter D/A converter Bus Control Pin 99 P9_6 SOUT4 ANEX 2 P9_5 CLK4 ANEX 3 P9_4 TB4IN DA 4 2 P9_3 TB3IN DA 5 3 P9_2 TB2IN SOUT3 6 4 P9_ TBIN SIN3 7 5 P9_ TBIN CLK3 8 6 BYTE 9 7 CNVSS 8 XCIN P8_7 9 XCOUT P8_6 2 RESET 3 XOUT 4 2 VSS 5 3 XIN 6 4 VCC 7 5 P8_5 NMI SD 8 6 P8_4 INT2 ZP 9 7 P8_3 INT 2 8 P8_2 INT 2 9 P8_ TA4IN/U CTS5/RTS P8_ TA4OUT/U RXD5/SCL P7_7 TA3IN CLK P7_6 TA3OUT TXD5/SDA P7_5 TA2IN/W P7_4 TA2OUT/W P7_3 TAIN/V CTS2/RTS P7_2 TAOUT/V CLK P7_ TAIN/TB5IN RXD2/SCL P7_ TAOUT TXD2/SDA P6_7 TXD/SDA 32 3 P6_6 RXD/SCL 33 3 P6_5 CLK P6_4 CTS/RTS/CTS/CLKS P6_3 TXD/SDA P6_2 RXD/SCL P6_ CLK P6_ CTS/RTS P5_7 RDY/CLKOUT 4 38 P5_6 ALE 4 39 P5_5 HOLD 42 4 P5_4 HLDA 43 4 P5_3 BCLK P5_2 RD P5_ WRH/BHE P5_ WRL/WR P4_7 TXD7/SDA7 CS P4_6 RXD7/SCL7 CS P4_5 CLK7 CS 5 48 P4_4 CTS7/RTS7 CS Page 9 of 383

31 . Overview Table.5 Pin Names for -Pin Package(2) Pin No. I/O Pin Functions for of Peripheral Modules Control Port Pin A/D converter FA FB Interrupt Timer Serial interface D/A converter Bus Control Pin 5 49 P4_3 A P4_2 A P4_ A P4_ A P3_7 A P3_6 A P3_5 A P3_4 A P3_3 A 6 58 P3_2 A 6 59 P3_ A VCC P3_ A8, [A8/D7] VSS P2_7 AN2_7 A7, [A7/D7], [A7/D6] P2_6 AN2_6 A6, [A6/D6], [A6/D5] P2_5 INT7 AN2_5 A5, [A5/D5], [A5/D4] P2_4 INT6 AN2_4 A4, [A4/D4], [A4/D3] P2_3 AN2_3 A3, [A3/D3], [A3/D2] 7 68 P2_2 AN2_2 A2, [A2/D2], [A2/D] 7 69 P2_ AN2_ A, [A/D], [A/D] 72 7 P2_ AN2_ A, [A/D], A 73 7 P_7 INT5 D P_6 INT4 D P_5 INT3 D P_4 D P_3 TXD6/SDA6 D P_2 RXD6/SCL6 D P_ CLK6 D P_ CTS6/RTS6 D P_7 AN_7 D P_6 AN_6 D P_5 AN_5 D P_4 AN_4 D P_3 AN_3 D P_2 AN_2 D P_ AN_ D P_ AN_ D P_7 KI3 AN P_6 KI2 AN P_5 KI AN P_4 KI AN P_3 AN P_2 AN P_ AN AVSS P_ AN VREF AVCC 98 P9_7 SIN4 ADTRG Page of 383

32 . Overview.6 Pin Functions Table.6 Pin Functions () Signal Name Pin Name I/O Power Supply Description Power supply input Analog power supply input VCC VCC2 VSS AVCC AVSS I - Apply 2.7 to 5.5 V to pins VCC and VCC2 (VCC =VCC2) and V to the VSS pin () I VCC Apply the power supply for the A/D converter. Connect the AVCC pin to VCC. Connect the AVSS pin to VSS. Reset input RESET I VCC Low active input pin. Driving this pin Low resets the MCU. CNVSS CNVSS I VCC Input pin to switch processor mode. To start up in single-chip mode after a reset, connect the CNVSS pin to VSS via resister. To start up in microprocessor mode, connect the CNVSS pin to VSS. External data bus width select input Bus control pins BYTE I VCC Input pin to select the data bus of the external memory area. The data bus is 6-bit when it is Low and 8-bit when it is High. This pin must be fixed either High or Low. Connect the BYTE pin to VSS in single-chip mode D to D7 I/O VCC2 Inputs or outputs data (D to D7) while accessing an external memory area with separate bus D8 to D5 I/O VCC2 Inputs or outputs data (D8 to D5) while accessing an external memory area with 6-bit separate bus A to A9 O VCC2 Outputs address bits A to A9 A/D to A7/D7 A/D to A8/D7 I/O VCC2 Inputs or outputs data (D to D7) and outputs address bits (A to A7) by timesharing, while accessing an external memory area with 8-bit multiplexed bus I/O VCC2 Inputs or outputs data (D to D7) and outputs address bits (A to A8) by timesharing, while accessing an external memory area with 6-bit multiplexed bus CS to CS3 O VCC2 Outputs chip-select signals CS to CS3 to specify an external memory area WRL/WR WRH/BHE RD O VCC2 Low active output pins. Outputs WRL, WRH, (WR, BHE), RD signals. WRL and WRH can be switched with or WR and BHE can be selected by a program. WRL, WRH and RD selected If the external data bus is 6-bit, data is written to an even address in external memory area when WRL is driven low. Data is written to an odd address when WRH is driven low. Data is read when RD is driven low. WR, BHE and RD are selected Data is written to external memory area when WR is driven low. Data in external memory area is read when RD is driven low. An odd address is accessed when BHE is driven low. Select WR, BHE, and RD for external 8-bit data bus ALE O VCC2 Output ALE signal to latch address. HOLD I VCC2 Low active input pin. The MCU is placed in hold state while the HOLD pin is driven low. HLDA O VCC2 Low active output pin. In a hold state, HLDA outputs a lowlevel signal. RDY I VCC2 Low active input pin. The MCU is placed in wait state while the RDY pin is driven low. Note:. VCC is hereinafter referred to as VCC unless otherwise noted. Page of 383