NB3N1900K. 3.3V 100/133 MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe

Transcription

1 3.3V 00/33 MHz Differential :9 HCSL Clock ZDB/Fanout Buffer for PCIe Description The differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point to point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel QuickPath Interconnect (Intel QPI & UPI), PCIe Gen, Gen2, Gen3, Gen4. The internal PLL is optimized to support 00 MHz and 33 MHz frequency operation. The supports HCSL output levels. Features Fixed Feedback Path for Lowest Input to utput Delay Eight Dedicated E# Pins for Hardware Control of utputs PLL Bypass Configurable for PLL or Fanout peration Selectable PLL Bandwidth Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI SMBus Programmable Configurations 00 MHz and 33 MHz PLL Mode to Meet the Next Generation PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI Phase Jitter 2 Tri Level Addresses Selection (Nine SMBUS Addresses) Cycle to Cycle Jitter: < 50 utput to utput Skew: < 65 Input to utput Delay: Fixed at 0 Input to utput Delay Variation: < 50 Phase Jitter: PCIe Gen3 < rms Phase Jitter: PCIe Gen4 < 0.5 rms Phase Jitter: QPI 9.6GB/s < 0.2 rms QFN 72 pin Package, 0 mm x 0 mm These are Pb Free Devices 72 QFN72 MN SUFFIX CASE 485DK MARKING DIAGRAM* NB3N 900K AWLYYWWG = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb Free Package RDERING INFRMATIN See detailed ordering and shipping information on page 20 of this data sheet. Semiconductor Components Industries, LLC, 207 January, 209 Rev. 6 Publication rder Number: /D

2 E[5:2]# 8 FB_UT FB_UT# CLK_IN CLK_IN# SSC Compatible PLL MUX DIF[8:0] DIF[8:0]# 00M_33M# HBW_BYP_LBW# SA_0 SA_ PWRGD/PWRDN# SDA SCL Control Logic NTE: Even though the feedback is fixed FB_UT and FB_UT# still needs a termination network for the part to function. IREF Figure. Simplified Block Diagram of 2

3 VDDA 54 GNDA 2 53 IREF M_33M# PWRGD/PWRDN# 6 49 GND 7 48 VDDR 8 47 CLK_IN 9 46 CLK_IN# 0 45 SA_0 44 SDA 2 43 SCL 3 42 SA_ 4 4 NC 5 40 NC 6 39 FB_UT# 7 38 FB_UT DIF0 DIF0# VDD DIF DIF# DIF2 DIF2# GND DIF3 DIF3# DIF4 DIF4# VDD DIF5 DIF5# E5# DIF6 DIF6# DIF8# DIF8 DIF7# DIF7 VDD DIF6# DIF6 DIF5# DIF5 GND DIF4# DIF4 DIF3# DIF3 VDD E2# DIF2# DIF2 E# DIF# DIF E0# HBW_BYP_LBW# DIF0# DIF0 E9# DIF9# DIF9 VDD GND E8# DIF8# DIF8 E7# DIF7# DIF7 E6# FB_UT pins loaded the same as the DIF outputs. Figure 2. Pin Configuration (Top View) 3

4 Table. PLL PERATING MDE READBACK TABLE HBW_BYP_LBW# Byte0, bit 7 Byte 0, bit 6 Low (Low BW) 0 0 Mid (Bypass) 0 High (High BW) Table 2. PWER CNNECTINS VDD Pin Number GND Description 2 Analog PLL 8 7 Analog Input 2, 3, 45, 58, 68 26, 44, 63 DIF clocks Table 5. PLL PERATING MDE HBW_BYP_LBW# MDE Low PLL Lo BW Mid Bypass High PLL Hi BW NTE: PLL is FF in Bypass Table 6. MDE TRI LEVEL INPUT THRESHLD Level Voltage Low < 0.8 V Mid.2 < Vin <.8 V High Vin > 2.2 V Table 3. FUNCTINALITY AT PWER UP (PLL MDE) 00M_33M# CLK_IN (MHz) DIF (MHz) CLK_IN CLK_IN Table 4. SMBus ADDRESSING SA_ Pin SA_0 SMBus Address 8 bit (Rd/Wrt bit = 0) 0 0 D8 0 M DA 0 DE M 0 C2 M M C4 M C6 0 CA M CC CE 4

5 Table 7. PIN DESCRIPTIN Pin # Pin Name Pin Type Description VDDA PWR 3.3 V power for the PLL core. 2 GNDA PWR Ground pin for the PLL core. 3 IREF UT 4 00M_33M# IN 5 HBW_BYP_LBW# IN 6 PWRGD/PWRDN# IN 7 GND PWR Ground pin. 8 VDDR PWR This pin establishes the reference for the differential current mode output pairs. It requires a fixed precision resistor to ground. 475 is the standard value for 00 differential impedance. ther impedances require different values. See data sheet. Input to select operating frequency = MHz, 0 = MHz 9 CLK_IN IN 0.7 V Differential true input Trilevel input to select High BW, Bypass or Low BW mode. See PLL perating Mode Table for Details. 0 CLK_IN# IN 0.7 V Differential complementary Input SA_0 IN 2 SDA I/ Data pin of SMBus circuitry, 5V tolerant 3 SCL IN Clock pin of SMBus circuitry, 5V tolerant 4 SA_ IN 5 NC N/A No Connection. 6 NC N/A No Connection. 7 FB_UT# UT 8 FB_UT UT 9 DIF0 UT 0.7 V differential true clock output Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode. 3.3 V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. SMBus address bit. This is a tri level input that works in conjunction with the SA_ to decode of 9 SMBus Addresses. SMBus address bit. This is a tri level input that works in conjunction with the SA_0 to decode of 9 SMBus Addresses. Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization with input clock to eliminate phase error. True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input clock to eliminate phase error. 20 DIF0# UT 0.7 V differential complementary clock output 2 VDD PWR Power supply, nominal 3.3 V 22 DIF UT 0.7 V differential true clock output 23 DIF# UT 0.7 V differential complementary clock output 24 DIF2 UT 0.7 V differential true clock output 25 DIF2# UT 0.7 V differential complementary clock output 26 GND PWR Ground pin. 27 DIF3 UT 0.7 V differential true clock output 28 DIF3# UT 0.7 V differential complementary clock output 29 DIF4 UT 0.7 V differential true clock output 30 DIF4# UT 0.7 V differential complementary clock output 3 VDD PWR Power supply, nominal 3.3 V 32 DIF5 UT 0.7 V differential true clock output 33 DIF5# UT 0.7 V differential complementary clock output 34 E5# IN Active low input for enabling DIF pair 5. = disable outputs, 0 = enable outputs 35 DIF6 UT 0.7 V differential true clock output 36 DIF6# UT 0.7 V differential complementary clock output 37 E6# IN Active low input for enabling DIF pair 6. =disable outputs, 0 = enable outputs 5

6 Table 7. PIN DESCRIPTIN Pin # Pin Name Pin Type 38 DIF7 UT 0.7 V differential true clock output Description 39 DIF7# UT 0.7 V differential complementary clock output 40 E7# IN Active low input for enabling DIF pair 7. = disable outputs, 0 = enable outputs 4 DIF8 UT 0.7 V differential true clock output 42 DIF8# UT 0.7 V differential complementary clock output 43 E8# IN 44 GND PWR Ground pin. Active low input for enabling DIF pair 8. = disable outputs, 0 = enable outputs 45 VDD PWR Power supply, nominal 3.3 V 46 DIF9 UT 0.7 V differential true clock output 47 DIF9# UT 0.7 V differential complementary clock output 48 E9# IN Active low input for enabling DIF pair 9. = disable outputs, 0 = enable outputs 49 DIF0 UT 0.7 V differential true clock output 50 DIF0# UT 0.7 V differential complementary clock output 5 E0# IN Active low input for enabling DIF pair 0. = disable outputs, 0 = enable outputs 52 DIF UT 0.7 V differential true clock output 53 DIF# UT 0.7 V differential complementary clock output 54 E# IN Active low input for enabling DIF pair. = disable outputs, 0 = enable outputs 55 DIF2 UT 0.7 V differential true clock output 56 DIF2# UT 0.7 V differential complementary clock output 57 E2# IN Active low input for enabling DIF pair 2. = disable outputs, 0 = enable outputs 58 VDD PWR Power supply, nominal 3.3 V 59 DIF3 UT 0.7 V differential true clock output 60 DIF3# UT 0.7 V differential complementary clock output 6 DIF4 UT 0.7 V differential true clock output 62 DIF4# UT 0.7 V differential complementary clock output 63 GND PWR Ground pin. 64 DIF5 UT 0.7 V differential true clock output 65 DIF5# UT 0.7 V differential complementary clock output 66 DIF6 UT 0.7 V differential true clock output 67 DIF6# UT 0.7 V differential complementary clock output 68 VDD PWR Power supply, nominal 3.3 V 69 DIF7 UT 0.7 V differential true clock output 70 DIF7# UT 0.7 V differential complementary clock output 7 DIF8 UT 0.7 V differential true clock output 72 DIF8# UT 0.7 V differential complementary clock output 6

7 Table 8. ABSLUTE MAXIMUM RATINGS (Note ) Symbol Parameter Conditions Min Typ Max Unit V DDA 3.3 V Core Supply Voltage (Note 2) 4.6 V V DD 3.3 V Logic Supply Voltage (Note 2) 4.6 V V IL Input Low Voltage GND 0.5 V V IH Input High Voltage Except for SMBus interface V DD V V IHSMB Input High Voltage SMBus clock and data pins 5.5 V T s Storage Temperature C T J Junction Temperature 25 C T c Case Temperature 30 C ESD ESD protection Human Body Model 2000 V JA Thermal Resistance Junction to Ambient Still air 8. C/W JC Thermal Resistance Junction to Case 5.0 C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Guaranteed by design and characterization, not tested in production. 2. peration under these conditions is neither implied nor guaranteed. 7

8 Table 9. ELECTRICAL CHARACTERISTICS INPUT/SUPPLY/CMMN PARAMETERS (V DD = V DDA = 3.3 V ±5%, T A = 0 C to +70 C), See Test Loads for Loading Conditions. Symbol Parameter Conditions Min Typ Max Unit V IH V IL V IH_FS (Note 4) V IL_FS (Note 4) Input High Voltage Input Low Voltage Single ended inputs, except SMBus, low threshold and tri level inputs (Note 3) Single ended inputs, except SMBus, low threshold and tri level inputs (Note 3) 2 GND 0.3 Input High Voltage 0.7 Input Low Voltage GND 0.3 V DD V 0.8 V V DD V 0.35 V I IN F IBYP Input Current Single ended inputs, V IN = GND, V IN = V DD (Note 3) 5 5 A V DD = 3.3 V, Bypass mode (Notes 3, 5 and 6) MHz F IPLL Input Frequency V DD = 3.3 V, MHz PLL mode (Note 5) MHz F IPLL V DD = 3.3 V, MHz PLL mode (Notes 5) MHz L PIN Pin Inductance (Note 3) 7 nh C IN C INDIF_IN Capacitance Logic Inputs, except CLK_IN (Note 3).5 5 pf CLK_IN differential clock inputs (Notes 3 and 7) pf C UT utput pin capacitance (Note 3) 6 pf T STAB f t LATE# t DRVPD Clk Stabilization Input SS Modulation Frequency E# Latency Tdrive_PD# From V DD Power Up and after input clock stabilization or de assertion of PD# to st clock (Notes 3 and 5) Allowable Frequency (Triangular Modulation) (Note 3) DIF start after E# assertion DIF stop after E# de assertion (Note 3) DIF output enable after PD# de assertion (Note 3).8 ms khz 4 2 cycles 300 s t F Tfall Fall time of control inputs (Notes 3 and 5) 5 ns t R Trise Rise time of control inputs (Notes 3 and 5) 5 ns V ILSMB SMBus Input Low Voltage (Note 3) 0.8 V V IHSMB SMBus Input High Voltage (Note 3) 2. V DDSMB V V LSMB SMBus utput Low I PULLUP (Note 3) 0.4 V I PULLUP SMBus Sink V L (Note 3) 4 ma V DDSMB Nominal Bus Voltage 3 V to 5 V ±0% (Note 3) V t RSMB SCL/SDA Rise Time (Max V IL 0.5) to (Min V IH + 0.5) (Note 3) 000 ns t FSMB SCL/SDA Fall Time (Min VIH + 0.5) to (Max V IL 0.5) (Note 3) 300 ns f MAXSMB SMBus perating Frequency Maximum SMBus operating frequency (Notes 3 and 8) 00 khz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by design and characterization, not tested in production M_33M# Frequency Select (FS). 5. Control input must be monotonic from 20% to 80% of input swing. 6. Fmax measured until output violates output duty cycle specifications and output V High, V Low specification. 7. CLK_IN input 8. The differential input clock must be running for the SMBus to be active. 8

9 Table 0. ELECTRICAL CHARACTERISTICS CLCK INPUT PARAMETERS (V DD = V DDA = 3.3 V ±5%, T A = 0 C to +70 C), See Test Loads for Loading Conditions. Symbol Parameter Conditions Min Typ Max Unit V IHDIF Input High Voltage CLK_IN (Note 9) Differential inputs (single ended measurement) mv V ILDIF Input Low Voltage CLK_IN (Note 9) Differential inputs (single ended measurement) V SS mv V CM Input Common Mode Voltage CLK_IN (Note 9) Common Mode Input Voltage mv V SWING Input Amplitude CLK_IN (Note 9) Peak to Peak value mv dv/dt Input Slew Rate CLK_IN (Notes 9 and 0) Measured differentially V/ns I IN Input Leakage Current (Note 9) V IN = V DD, V IN = GND 5 5 A d tin Input Duty Cycle (Note 9) Measurement from differential waveform % J DIFIn Input Jitter Cycle to Cycle (Note 9) Differential Measurement 0 25 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 9. Guaranteed by design and characterization, not tested in production. 0. Slew rate measured through ±75 mv window centered around differential zero. Table. ELECTRICAL CHARACTERISTICS DIF 0.7 V CURRENT MDE DIFFERENTIAL UTPUTS (V DD = V DDA = 3.3 V ±5%, T A = 0 C to +70 C), See Test Loads for Loading Conditions Symbol Parameter Conditions Min Typ Max Unit dv/dt Slew rate (Notes, 2 and 3) Scope averaging on 4 V/ns dv/dt Trf Slew rate matching (Notes, 2 and 4) Rise/Fall Time Matching (Notes, 2 and 8) Slew rate matching, Scope averaging on 20 % Rise/fall matching, Scope averaging off 25 V High Voltage High (Note ) Statistical measurement on single ended signal using oscilloscope math function. V Low Voltage Low (Note ) (Scope averaging on) V max Max Voltage (Note ) Measurement on single ended signal using V min Min Voltage (Note ) Absolute value. (Scope averaging off) 300 V swing Vswing (Notes and 2) Scope averaging off 300 mv V cross_abs V cross Crossing Voltage (abs) (Notes and 5) Crossing Voltage (var) (Notes and 6) 50 Scope averaging off mv Scope averaging off 40 mv Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Guaranteed by design and characterization, not tested in production. I REF = V DD /(3xR REF ). For R REF = 475 (%), I REF = 2.32 ma. I H = 6 x I REF and V H = 0.7 Z = 50 (00 differential impedance). 2. Measured from differential waveform. 3.Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±50 mv window around differential 0 V. 4. Matching applies to rising and falling edge rate of differential waveform. It is measured using a ±75 mv window centered on the average cross point where the clock rising meets clock# falling. The median cross point is used to calculate voltage thresholds that the oscilloscope uses to calculate the slew rate. Measurement taken using a 00 differential impedance 5 trace PCB. 5.Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. 7. Measured from single ended waveform 8. Measured with scope averaging off, using statistics function. Variation is difference between min and max. mv mv 9

10 Table 2. ELECTRICAL CHARACTERISTICS CURRENT CNSUMPTIN (V DD = V DDA = 3.3 V ±5%, T A = 0 C to +70 C), See Test Loads for Loading Conditions Symbol Parameter Conditions Min Typ Max Unit I DD3.3P perating Supply Current (Note 9) All outputs MHz, C L = Full load 550 ma I DD3.3PDZ Powerdown Current (Note 9) All differential pairs tri stated 36 ma Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 9. Guaranteed by design and characterization, not tested in production. Table 3. ELECTRICAL CHARACTERISTICS SKEW AND DIFFERENTIAL JITTER PARAMETERS (V DD = V DDA = 3.3 V ±5%, T A = 0 C to +70 C), See Test Loads for Loading Conditions Symbol Parameter Conditions Min Typ Max Unit t SP_PLL CLK_IN, DIF[x:0] (Notes 20, 2, 23, 24 and 27) Input to utput Skew in PLL mode nominal 25 C, 3.3 V t PD_BYP CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) Input to utput Skew in Bypass mode nominal 25 C, 3.3 V ns t DSP_PLL CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) Input to utput Skew Variation in PLL mode across voltage and temperature 00 t DSP_BYP CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) Input to utput Skew Variation in Bypass mode across voltage and temperature t SKEW_ALL DIF{x:0] (Notes 20, 2, 22 and 27) utput to utput Skew across all outputs (Common to Bypass and PLL mode) 65 j peak hibw j peak lobw PLL Jitter Peaking (Notes 26 and 27) PLL Jitter Peaking (Notes 26 and 27) HBW_BYP_LBW# = db HBW_BYP_LBW# = db pll HIBW PLL Bandwidth (Notes 27 and 28) HBW_BYP_LBW# = 2 4 MHz pll LBW PLL Bandwidth (Notes 27 and 28) HBW_BYP_LBW# = MHz t DC Duty Cycle (Notes 20 and 27) Measured differentially, PLL Mode % t DCD Duty Cycle Distortion (Notes 20 and 29) Measured differentially, Bypass MHz % t jcyc cyc Jitter, Cycle to cycle (Notes 20, 27 and 30) PLL mode 50 Additive Jitter in Bypass Mode 50 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 20.Measured into fixed 2 pf load cap. Input to output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross point to differential cross point. This parameter can be tuned with external feedback path, if present. 22. All Bypass Mode Input to utput specs refer to the timing between an input edge and the specific output edge created by it. 23. This parameter is deterministic for a given device. 24.Measured with scope averaging on to find mean value. CLK_IN slew rate must be matched to DIF output slew rate. 25.t is the period of the input clock. 26. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 27. Guaranteed by design and characterization, not tested in production. 28.Measured at 3 db down or half power point. 29.Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass MHz. 30. Measured from differential waveform. 0

11 Table 4. ELECTRICAL CHARACTERISTICS PHASE JITTER PARAMETERS (V DD = V DDA = 3.3 V ±5%, T A = 0 C to +70 C), See Test Loads for Loading Conditions. Symbol Parameter Conditions (Notes 3 and 36) Min Typ Max Unit t jphpcieg PCIe Gen (Notes 32 and 33) 2 86 (p p) PCIe Gen 2 Lo Band 0 khz < f <.5 MHz (Note 32) t jphpcieg2 PCIe Gen 2 High Band.5 MHz < f < Nyquist (50 MHz) (Note 32).0 3. t jphpcieg3 PCIe Gen 3 (PLL BW of 2 4 MHz, CDR = 0 MHz) (Note 32) 0.29 t jphpcieg4 PCIe Gen 4 Jitter, Phase (PLL BW of 2 4 MHz, CDR = 0 MHz) t jphupi UPI (9.6 Gb/s, 0.4 Gb/s or.2 Gb/s, 00 MHz, 2 UI) QPI & SMI (00.00 MHz or MHz, 4.8 Gb/s, 6.4 Gb/s 2UI) (Note 34) t jphqpi_smi QPI & SMI (00.00 MHz, 8.0 Gb/s, 2UI) (Note 34) QPI & SMI (00.00 MHz, 9.6 Gb/s, 2UI) (Note 34) t jphpcieg PCIe Gen (Notes 32 and 33) 0 (p p) PCIe Gen 2 Lo Band 0 khz < f <.5 MHz (Notes 32 and 35) 0.3 t jphpcieg2 PCIe Gen 2 High Band.5 MHz < f < Nyquist (50 MHz) (Notes 32 and 35) 0.7 PCIe Gen 3 t jphpcieg3 Additive Phase Jitter, Bypass mode (Notes 32 and (PLL BW of 2 4 MHz, CDR = 0 MHz) 35) t jphqpi_smi QPI & SMI (00.00 MHz or MHz, 4.8 Gb/s, 6.4 Gb/s 2UI) (Notes 34 and 35) QPI & SMI (00.00 MHz, 8.0 Gb/s, 2UI) (Notes 34 and 35) QPI & SMI (00.00 MHz, 9.6 Gb/s, 2UI) (Notes 34 and 35) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Applies to all outputs. 32. See for complete specs 33.Sample size of at least 00K cycles. This figures extrapolates to 08 pk M cycles for a BER of Calculated from Intel supplied Clock Jitter Tool v For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter) 2 = (total jitter) 2 - (input jitter) Guaranteed by design and characterization, not tested in production 0.

12 Table 5. CLCK PERIDS DIFFERENTIAL UTPUTS WITH SPREAD SPECTRUM DISABLED SSC FF DIF Center Freq. MHz Measurement Window Clock us 0.s 0.s 0.s us Clock c2c jitter AbsPer Min SSC Short Term Average Min ppm Long Term Average Min 0 ppm Period Nominal + ppm Long Term Average Max +SSC Short Term Average Max +c2c jitter AbsPer Max ns ns Unit Notes 37, 38, 39 37, 38, Guaranteed by design and characterization, not tested in production. 38.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK40B+ accuracy requirements (±00 ppm). The 9ZX290 itself does not contribute to ppm error. 39.Driven by SRC output of main clock, MHz PLL Mode or Bypass mode 40.Driven by CPU output of main clock, MHz PLL Mode or Bypass mode Table 6. CLCK PERIDS DIFFERENTIAL UTPUTS WITH SPREAD SPECTRUM ENABLED SSC N DIF Center Freq. MHz Measurement Window Clock us 0.s 0.s 0.s us Clock c2c jitter AbsPer Min SSC Short Term Average Min ppm Long Term Average Min 0 ppm Period Nominal + ppm Long Term Average Max +SSC Short Term Average Max +c2c jitter AbsPer Max ns ns Unit Notes 4, 42, 43 4, 42, Guaranteed by design and characterization, not tested in production. 42.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK40B+ accuracy requirements (±00 ppm). The 9ZX290 itself does not contribute to ppm error. 43.Driven by SRC output of main clock, MHz PLL Mode or Bypass mode 44.Driven by CPU output of main clock, MHz PLL Mode or Bypass mode Table 7. PWER MANAGEMENT TABLE Inputs Control Bits/Pins utputs PWRGD/PWRDN# CLK_IN/CLK_IN# SMBus EN bit E# Pin DIF(5:2) / DIF(5:2)# ther DIF/ DIF# FB_UT / FB_UT# 0 X X X Hi Z (Note 45) Hi Z (Note 45) Hi Z (Note 45) FF Running PLL State 0 X Hi Z (Note 45) Hi Z (Note 45) Running N 0 Running Running Running N Hi Z (Note 45) Running Running N 45. Due to external pull down resistors, HI Z results in Low/Low on the True/Complement outputs 2

13 0 inches Rs Rs Rp Rp Differential Zo 2pF 2pF HCSL utput Buffer Figure 3. Differential Test Loads Table 8. DIFFERENTIAL UTPUT TERMINATIN TABLE DIF Zo ( ) Iref ( ) Rs ( ) Rp ( ) or 43.2 PWRGD/PWRDN# PWRGD/PWRDN# is a dual function pin. PWRGD is asserted high and de asserted low. De assertion of PWRGD (pulling the signal low) is equivalent to indicating a powerdown condition. PWRGD (assertion) is used by the to sample initial configurations such as frequency select condition and SA selections. After PWRGD has been asserted high for the first time, the pin becomes a PWRDN# (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device to invoke power savings mode. PWRDN# is a completely asynchronous active low input. When entering power savings mode, PWRDN# should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down in a glitch free manner. When PWRDN# is asserted low by two consecutive rising edges of DIF#, all differential outputs are held tri stated on the next DIF# high to low transition. The assertion and de-assertion of PWRDN# is absolutely asynchronous. WARNING: Disabling of the CLK_IN input clock prior to assertion of PWRDN# is an undefined mode and not recommended. peration in this mode may result in glitches, excessive frequency shifting, etc. Table 9. PWRGD/PWRDN# FUNCTINALITY PWRGD/PWRDN# DIF DIF# 0 Tri state Tri state Running Running 3

14 Buffer Power Up State Machine Table 20. BUFFER PWER UP STATE MACHINE State Description V Buffer power off After 3.3 V supply is detected to rise above 3.35 V, the buffer enters State and initiates a 0. ms 0.3 ms delay. 2 Buffer waits for a valid clock on the CLK input and PWRDN# de assertion (or PWRGD assertion low to high) 3 nce the PLL is locked to the CLK_IN input clock, the buffer enters state 3 and enables outputs for normal operation. (Notes 46, 47) 46.The total power up latency from power on to all outputs active must be less than.8 ms (assuming a valid clock is present on CLK_IN input). 47.If power is valid and powerdown is de asserted (PWRGD asserted) but no input clocks are present on the CLK_IN input, DIF clocks must remain disabled. nly after valid input clocks are detected, valid power, PWRDN# de asserted (PWRGD asserted) with the PLL locked/stable and the DIF outputs enabled. No input clock State Delay 0. ms 0.3 ms State 2 Wait for input clock and powerdown de assertion Powerdown Asserted State 0 State 3 Power ff Normal peration Figure 4. Buffer Power Up State Diagram Device Power Up Sequence Follow the power up sequence below for proper device functionality:. PWRGD/PWRDN# pin must be Low. 2. Assign remaining control pins to their required state (00M_33M#, HBW_BYPASS_LBW#, SDA, SCL) 3. Apply power to the device. 4. nce the VDD pin has reached a valid VDDmin level (3.3V 5%), the PWRGD/PWRDN# pin must be asserted High. See Figure 5. Note: If no clock is present on the CLK_IN/CLK_IN# pins when device is powered up, there will be no clock on DIF/DIF# outputs. Figure 5. PWRGD and VDD Relationship Diagram 4

15 GENERAL SMBUS SERIAL INTERFACE INFRMATIN FR THE How to Write: Controller (host) sends a start bit. Controller (host) sends the write address XX (H) Clock(device) will acknowledge Controller (host) sends the beginning byte location = N Clock(device) will acknowledge Controller (host) sends the data byte count = X Clock(device) will acknowledge Controller (host) starts sending Byte N through Byte N + X Clock(device) will acknowledge each byte one at a time Controller (host) sends a Stop bit Table 2. INDEX BLCK WRITE PERATIN Controller (Host) T start bit Slave Address XX (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N P Byte N + X - stop bit X Byte Clock (Device) ACK ACK ACK ACK Note: XX (H) is defined by SMBus address select pins ACK How to Read: Controller (host) will send start bit. Controller (host) sends the write address XX (H) Clock(device) will acknowledge Controller (host) sends the beginning byte location = N Clock(device) will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address YY (H) Clock(device) will acknowledge vclock will send the data byte count = X Clock(device) sends Byte N + X Clock(device) sends Byte 0 through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) sends a Stop bit Table 22. INDEX BLCK READ PERATIN Controller (Host) T start bit Slave Address XX (H) WR WRite Beginning Byte = N RT Repeat start Slave Address YY (H) RD N P ACK ACK ReaD Not acknowledge stop bit Clock (Device) ACK ACK ACK Data Byte Count = X X Byte Note: XX (H) is defined by SMBus address select pins Beginning Byte N Byte N + X - 5

16 Table 23. SMBusTable: PLL MDE, AND FREQUENCY SELECT REGISTER Byte 0 Pin # Name Control Function Type 0 Default Bit 7 5 PLL Mode PLL perating Mode Rd back R See PLL perating Mode Latch Bit 6 5 PLL Mode 0 PLL perating Mode Rd back 0 R Readback Table Latch Bit 5 72/7 DIF_8_En utput Control overrides E# pin RW Hi Z Enable Bit 4 70/69 DIF_7_En utput Control overrides E# pin RW Hi Z Enable Bit 3 67/66 DIF_6_En utput Control overrides E# pin RW Hi Z Enable Bit 2 Reserved 0 Bit Reserved 0 Bit M_33M# Frequency Select Readback R 33 MHz 00 MHz Latch Table 24. SMBusTable: UTPUT CNTRL REGISTER Byte Pin # Name Control Function Type 0 Default Bit 7 39/38 DIF_7_En utput Control overrides E# pin RW Bit 6 35/36 DIF_6_En utput Control overrides E# pin RW Bit 5 32/33 DIF_5_En utput Control overrides E# pin RW Bit 4 29/30 DIF_4_En utput Control overrides E# pin RW Bit 3 27/28 DIF_3_En utput Control overrides E# pin RW Hi Z Enable Bit 2 24/25 DIF_2_En utput Control overrides E# pin RW Bit 22/23 DIF En utput Control overrides E# pin RW Bit 0 9/20 DIF_0_En utput Control overrides E# pin RW Table 25. SMBusTable: UTPUT CNTRL REGISTER Byte 2 Pin # Name Control Function Type 0 Default Bit 7 65/64 DIF_5_En utput Control overrides E# pin RW Bit 6 62/6 DIF_4_En utput Control overrides E# pin RW Bit 5 60/59 DIF_3_En utput Control overrides E# pin RW Bit 4 56/55 DIF_2_En utput Control overrides E# pin RW Hi Z Enable Bit 3 53/52 DIF En utput Control overrides E# pin RW Bit 2 50/49 DIF_0_En utput Control overrides E# pin RW Bit 47/46 DIF_9_En utput Control overrides E# pin RW Bit 0 42/4 DIF_8_En utput Control overrides E# pin RW Table 26. SMBusTable: UTPUT ENABLE PIN STATUS READBACK REGISTER Byte 3 Pin # Name Control Function Type 0 Default Bit 7 57 E_RB2 Real Time readback of E#2 R Real time Bit 6 54 E_RB Real Time readback of E# R Real time Bit 5 5 E_RB0 Real Time readback of E#0 R Real time Bit 4 48 E_RB9 Real Time readback of E#9 R Real time Bit 3 43 E_RB8 Real Time readback of E#8 R E# pin Low E# Pin High Real time Bit 2 40 E_RB7 Real Time readback of E#7 R Real time Bit 37 E_RB6 Real Time readback of E#6 R Real time Bit 0 34 E_RB5 Real Time readback of E#5 R Real time 6

17 Table 27. SMBusTable: RESERVED REGISTER Byte 4 Pin # Name Control Function Type 0 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit Reserved 0 Bit 0 Reserved 0 Table 28. SMBusTable: VENDR & REVISIN ID REGISTER Byte 5 Pin # Name Control Function Type 0 Default Bit 7 RID3 R X Bit 6 RID2 R X REVISIN ID Bit 5 RID R X Bit 4 RID0 R X Bit 3 VID3 R Bit 2 VID2 VENDR ID R Bit VID R Bit 0 VID0 R Table 29. SMBusTable: DEVICE ID Byte 6 Pin # Name Control Function Type 0 Default Bit 7 Device ID 7 (MSB) R Bit 6 Device ID 6 R Bit 5 Device ID 5 R 0 Bit 4 Device ID 4 R Device ID is 20 decimal or Bit 3 Device ID 3 R 78 hex. Bit 2 Device ID 2 R 0 Bit Device ID R Bit 0 Device ID 0 R Table 30. SMBusTable: BYTE CUNT REGISTER Byte 7 Pin # Name Control Function Type 0 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW Default value is 8 hex, so 9 Bit 2 BC2 Writing to this register configures how RW bytes (0 to 8) will be read 0 many bytes will be read back. back by default. Bit BC RW 0 Bit 0 BC0 RW 0 7

18 Table 3. SMBusTable: RESERVED REGISTER Byte 8 Pin # Name Control Function Type 0 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit Reserved 0 Bit 0 Reserved 0 DIF Reference Clock Common Recommendations for Differential Routing Dimension or Value Unit L length, route as non coupled 50 trace (Figure 6) 0.5 max inch L2 length, route as non coupled 50 trace (Figure 6) 0.2 max inch L3 length, route as non coupled 50 trace (Figure 6) 0.2 max inch Rs (Figure 6) 33 Rt (Figure 6) 49.9 Down Device Differential Routing L4 length, route as coupled microstrip 00 differential trace (Figure 6) 2 min to 6 max inch L4 length, route as coupled stripline 00 differential trace (Figure 6).8 min to 4.4 max inch Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 00 differential trace (Figure 7) 0.25 to 4 max inch L4 length, route as coupled stripline 00 differential trace (Figure 7) min to 2.6 max inch L L2 Rs L4 L4 L L2 HCSL utput Buffer Rs Rt Rt PCI Express Down Device REF_CLK Input L3 L3 Figure 6. Down Device Routing 8

19 L L2 Rs L4 L4 L L2 HCSL utput Buffer Rs Rt Rt PCI Express Add in Board REF_CLK Input L3 L3 Figure 7. PCI Express Connector Routing Table 32. ALTERNATIVE TERMINATIN FR LVDS AND THER CMMN DIFFERENTIAL SIGNALS (Figure 8) Vdiff (V) Vpp (V) Vcm (V) R ( ) R2 ( ) R3 ( ) R4 ( ) Note Standard LVDS Ra = Rb = R R2a = R2b = R2 L Ra L2 R3 L4 R4 L4 L L2 Rb HCSL utput Buffer R2a R2b Down Device REF_CLK Input L3 L3 Figure 8. Alternate Termination for LVDS Table 33. CABLE CNNECTED AC CUPLED APPLICATIN (Figure 9) Component Value Note R5a, R5b 8.2k 5% R6a, R6b k 5% Cc Vcm 0. F V 9

20 3.3 V Cc R5a R5b L4 Cc L4 R6a R6b Figure 9. Cable Connected AC Coupled Application PWER FILTERING EXAMPLE Ferrite Bead Power Filtering Recommended ferrite bead filtering equivalent to the following: 600 impedance at 00 MHz, 0. DCR max., 800 ma current rating. V3P3 FB R FERRITE 2.2 C9 F VDDA C7 0. F Place at pin VDD for PLL R2 2.2 C0 F VDDR C8 0. F VDD for Input Receiver C5 0. F F C5 VDD 0. F VDD C 0 F C2 0. F C4 0. F C3 0. F C5 0. F C5 0. F Figure 0. Schematic Example of the Power Filtering Table 34. RDERING INFRMATIN Device Package Shipping MNG MNTXG MNTWG QFN 72 (Pb Free) QFN 72 (Pb Free) QFN 72 (Pb Free) 68 Units / Tray 000 / Tape & Reel 000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. NTE: Pin orientation for TWG Suffix is Quadrant, upper left; Pin orientation for TXG Suffix is Quadrant 2, upper right 20

21 PACKAGE DIMENSINS PIN NE LCATIN NTE C 0.5 C 0.0 C 0.08 C ÉÉÉ ÉÉÉ D TP VIEW DETAIL B SIDE VIEW A B E (A3) A A QFN72 0x0, 0.5P CASE 485DK ISSUE L C SEATING PLANE EXPSED Cu L DETAIL A ALTERNATE CNSTRUCTINS ÉÉ MLD CMPD DETAIL B ALTERNATE CNSTRUCTIN L NTES:. DIMENSINING AND TLERANCING PER ASME Y4.5M, CNTRLLING DIMENSINS: MILLIMETERS. 3. DIMENSIN b APPLIES T PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.25mm FRM THE TERMINAL TIP. 4. CPLANARITY APPLIES T THE EXPSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b D 0.00 BSC D E 0.00 BSC E e 0.50 BSC L L RECMMENDED SLDERING FTPRINT* X 0.63 DETAIL A 9 D M C A B 72X L 0.0 M C A B E2 72 e BTTM VIEW 55 72X b 0.0 M C A B 0.05 M C NTE 3 PKG UTLINE 0.50 PITCH 72X 0.32 DIMENSINS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the N Semiconductor Soldering and Mounting Techniques Reference Manual, SLDERRM/D. Intel is a registered trademark of Intel Corporation. PCIe and PCI SIG are registered trademarks of PCI SIG. N Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba N Semiconductor or its subsidiaries in the United States and/or other countries. N Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of N Semiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. N Semiconductor reserves the right to make changes without further notice to any products herein. N Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does N Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using N Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by N Semiconductor. Typical parameters which may be provided in N Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. N Semiconductor does not convey any license under its patent rights nor the rights of others. N Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use N Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold N Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that N Semiconductor was negligent regarding the design or manufacture of the part. N Semiconductor is an Equal pportunity/affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATIN RDERING INFRMATIN LITERATURE FULFILLMENT: Literature Distribution Center for N Semiconductor P.. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: N Semiconductor Website: rder Literature: For additional information, please contact your local Sales Representative /D