PI6C557-01BQ. PCIe 3.0 Clock Generator with 1 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TQFN) Block Diagram
|
|
|
- Mariah Flowers
- 6 years ago
- Views:
Transcription
1 s Features ÎÎPCIe 3.0 compliant à à Phase jitter ps RMS (High Freq. Typ.) ÎÎLVDS compatible output ÎÎSupply voltage of 3.3V ±10% ÎÎ25MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V Current mode differential pair ÎÎJitter 35ps cycle-to-cycle (typ) ÎÎSpread of -0.5% and no spread ÎÎIndustrial temperature range ÎÎSpread Bypass option available ÎÎSpread selection via external pins ÎÎPackaging: (Pb-free and Green) à à 16-pin TQFN Description The PI6C557-01BQ is a spread spectrum clock generator compliant to PCI Express 3.0 and Ethernet requirements. The device is used for Automotive systems. The PI6C557-01BQ provides one differential (HCSL) or LVDS spread spectrum output. Using Pericom's patented Phase-Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces one pair of differential outputs (HCSL) at 100MHz. It also provides spread selection of -0.5% and no spread. Block Diagram Pin Configuration (16-Pin TQFN) VDD VDD SS1 25 MHz crystal or clock X1/CLK X2 Control Logic Crystal Driver Phase Lock Loop CLK CLK GND X1 X CLK CLK GND VDDA Pulling Capacitors GND R R (IREF) GND SS1 IREF 1
2 Pin Description Pin # Pin Name I/O Type Description 1 GND Power Connect to ground 2 X1 Input Crystal or reference clock in 3 X2 Output Xtal out. Leave unconnected for clock input. 4 - No connect. Must not be connected to GND 5 GND Power Connect to ground 6 SS1 Input Spread select 1. Internall pull up resistor 7 IREF Output 475Ω precision resistor attached to this pin is connected to the internal current reference. 8 - No connect. Must not be connected to GND 9 VDDA Power Connect to 3.3V source 10 GND Power Connect to ground 11 CLK Output HCSL complimentary clock output 12 CLK Output HCSL clock output 13 - No connect. Must not be connected to GND 14 - No connect. Must not be connected to GND 15 VDD Power Connect to 3.3V source for OSC and core 16 - No connect. Must not be connected to GND Table 1: Spread Selection Table SS1 Spread 0 Down -0.5% 1 No Spread 2
3 Application Information Output Structures Decoupling Capacitors Decoupling capacitors of 0.01μF should be connected between each V DD pin and the ground plane and placed as close to the V DD pin as possible. IREF =2.3mA 6*IREF Crystal Use a 25MHz fundamental mode parallel resonant crystal with less than 300PPM of error across temperature. Crystal Capacitors C L = Crystals's load capacitance in pf Crystal Capacitors (pf) = (C L - 8) *2 For example, for a crystal with 16pF load caps, the external effective crystal cap would be 16 pf. (16-8)*2=16. R R =475 Ω See Output Termination Sections Current Source (IREF) Reference Resistor - R R If board target trace impedance is 50Ω, then R R = 475Ω providing an IREF of 2.32 ma. The output current (I OH) is 6*IREF. Output Termination The PCI Express differential clock outputs of the PI6C557-01BQ are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI Express Layout Guidelines section. The PI6C557-01BQ can be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. 3
4 PCI Express Layout Guidelines Common Recommendations for Differential Routing Dimension or Value Unit L1 length, route as non-coupled 50Ω trace. 0.5 max inch L2 length, route as non-coupled 50Ω trace. 0.2 max inch L3 length, route as non-coupled 50Ω trace. 0.2 max inch R S 33 Ω R T 49.9 Ω Differential Routing on a Single PCB Dimension or Value Unit L4 length, route as coupled microstrip 100Ω differential trace. 2 min to 16 max inch L4 length, route as coupled stripline 100Ω differential trace. 1.8 min to 14.4 max inch Differential Routing to a PCI Express connector Dimension or Value Unit L4 length, route as coupled microstrip 100Ω differential trace min to 14 max inch L4 length, route as coupled stripline 100Ω differential trace min to 12.6 max inch PCI Express Device Routing L1 R S L2 L1 L2 L4 L4 R S R T R T PI6C557-01BQ Output Clock L3 L3 PCI-Express Load or Connector Typical PCI Express (HCSL) Waveform 800 mv 0 t OR 250 ps 400 ps t OF 0.52 V V 0.52 V V 4
5 Application Information LVDS Recommendations for Differential Routing Dimension or Value Unit L1 length, route as non-coupled 50Ω trace. 0.5 max inch L2 length, route as non-coupled 50Ω trace. 0.2 max inch RP 100 Ω RQ 100 Ω RT 150 Ω L3 length, route as 100Ω differential trace. L3 length, route as 100Ω differential trace. LVDS Device Routing L1 L3 L1 R Q L3 R P R T R T PI6C557-01BQ Clock Output L2 L2 LVDS Device Load 5
6 Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential V All Inputs and Outputs V to V DD+0.5V Ambient Operating Temperature to +85 C Storage Temperature to +150 C Junction Temperature C Soldering Temperature C ESD Protection (Input) V min (HBM) Note: Stresses greater than those listed under MAXI- MUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Specifications Recommended Operation Conditions Parameter Min. Typ. Max. Unit Ambient Operating Temperature C Power Supply Voltage (measured in respect to GND) V DC Characteristics (V DD = 3.3V ±10%, T A = -40 C to +85 C) Symbol Parameter Conditions Min. Typ. Max. Unit V DD Supply Voltage V V IH Input High Voltage (1) 2.0 V DD +0.3 V V IL Input Low Voltage (1) GND V I IL Input Leakage Current 0 < Vin < V DD With input pull-up and pull-downs Without input pull-up and pull-downs -5 5 µa I DD Operating Supply Current R L = 50Ω, C L = 2pF 95 ma C IN Input 55MHz 7 pf C OUT Output 55MHz 6 pf L PIN Pin Inductance 5 nh R OUT Output Resistance CLK Outputs 3.0 kω Notes: 1. Single edge is monotonic when transitioning through region. 6
7 HCSL Output AC Characteristics (V DD = 3.3V ±10%, T A = -40 C to +85 C) Symbol Parameter Conditions Min. Typ. Max. Unit F IN Input Frequency 25 MHz F OUT Output Frequency 100 MHz V OH Output High Voltage (1,2) 100 MHz HCSL V DD = 3.3V mv V OL Output Low Voltage (1,2) mv V CPA Crossing Point Voltage (1,2) Absolute mv V CN Crossing Point Voltage (1,2,4) Variation over all edges 140 mv J CC Jitter, Cycle-to-Cycle (1,3) ps J RMS JRMS3.0 PCIe 2.0 RMS Jitter PCIe 3.0 RMS Jitter Notes: 1. R L = 50-Ohm with C L = 2 pf 2. Single-ended waveform 3. Differential waveform 4. Measured at the crossing point Thermal Characteristics PCIe 2.0 Test 100MHz Output 3.1 ps PLL 2M & 5M 1st H ps PLL 2M & 4M 1st H ps PLL 2M & 5M 1st H ps PLL 2M & 4M 1st H ps MF Modulation Frequency Spread Spectrum khz t OR Rise Time (1,2) From 0.175V to 0.525V ps t OF Fall Time (1,2) From 0.525V to 0.175V ps T DUTY-CYCLE Duty Cycle (1,3) % t STABLE From power-up to V DD=3.3V From Power-up V DD=3.3V 3.0 ms t SPREAD Setting period after spread change Setting period after spread change 3.0 ms Symbol Parameter Conditions Min. Typ. Max. Unit θ JA Thermal Resistance Junction to Ambient Still air C/W θ JC Thermal Resistance Junction to Case C/W 7
8 Recomended Crystal Specification Pericom recommends: a) FL Q, SMD 3.2x2.5(4P), 25M, CL=20pF, Frequency Tolerance ±15ppm, Stability ±20ppm ( Recommended Crystal Circuit The following diagram shows PI6C557-05Q crystal circuit connection with a parallel crystal. For the C L=20pF parallel crystal, it is suggested to use C1=27 pf, C2=27 pf in general. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillation according to different board layouts. R1=360 ohm is recommended in layout for smaller size crystal drive level adjustment. 25M Crystal (C L = 20pF) C1 27pF Xin Optional 360Ω Xout C2 27pF 8
9 Packaging Mechanical: 16-Pin TQFN (ZH) DATE:12/26/13 DESCRIPTION: 16-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH (ZH16) DOCUMENT CONTROL #: PD-2047 Note: For latest package info, please check: REVISION: E Ordering Information Ordering Code Package Code Package Type Operating Temperature PI6C557-01BQZHIEX ZH Pb-free & Green, 16-pin TQFN Industrial Notes: Thermal characteristics can be found on the company web site at "E" denotes Pb-free and Green Adding an "X" at the end of the ordering code denotes tape and reel packaging 9
PCIe 3.0 Clock Generator with 4 HCSL Outputs. Description OE VDDXD S0 S1 S2 X1 X2 PD OE GNDXD IREF CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3
PCIe 3.0 Clock Generator with 4 HCSL Outputs Features PCIe 3.0 complaint PCIe 3.0 Phase jitter: 0.48ps RMS (High Freq. Typ.) LVDS compatible outputs Supply voltage of 3.3V ±5% 25MHz crystal or clock input
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Description. Features. Block Diagram DATASHEET
DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS Features
DATASHEET 2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS ICS557-08 Description The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) input pairs and
2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features
DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential
OBSOLETE PI6C Low Power Networking Clock Generator. Description. Features. Block Diagram
Features ÎÎ3.3V supply voltage ÎÎ25MHz XTAL or reference clock input ÎÎOutput 4x100MHz HCSL PCIe clock outputs with integrated series termination resistors, spread spectrum capability on all 100MHz PCIe
PI6C Low Power Networking Clock Generator. Description. Features. Block Diagram. 100MHz PCI-Express 0 100MHz PCI-Express 1 100MHz PCI-Express 2
Features ÎÎ25 MHz crystal or clock input ÎÎThree differential 100 MHz PCI-Express clock outputs push-pull termination ÎÎSpread spectrum capability on all 100 MHz PCI-e clock outputs with -0.5% down spread
PI6LC48L0201A 2-Output LVDS Networking Clock Generator
Features ÎÎTwo differential LVDS output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.5MHz, 125MHz, 156.25MHz
Features. Applications
HCSL-Compatible Clock Generator for PCI Express General Description The is the smallest, high performance, lowest power, 2 differential output clock IC available for HCSL timing applications. offers -130dBc
PI6CEQ PCIe Gen2 / Gen3 Buffer. Features. Description. Applications. Block Diagram. Pin Configuration (20-Pin TSSOP & 20-Pin QSOP)
PCIe Gen2 / Gen3 Buffer Features ÎÎPCIe Gen2/ Gen3* compliant clock buffer/zdb * Gen3 performance only available in Commercial temp ÎÎInternal equalization for better signal integrity ÎÎ2 HCSL outputs
PI6C49S1510 Rev J
High Performance Differential Fanout Buffer Features ÎÎ10 differential outputs with 2 banks ÎÎUser configurable output signaling standard for each bank: LVDS or LVPECL or HCSL ÎÎLVCMOS reference output
Description OUT0 1 OUTA1 OUTA1 2 OUTA2 3 OUTA3 OUTA4 OUTB1 6 OUTB2 7 OUTB2 OUTB3 OUTB4. All trademarks are property of their respective owners.
Features Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps Internal feedback allows outputs to be synchronized to the clock input Spread spectrum compatible
T1/E1 CLOCK MULTIPLIER. Features
DATASHEET ICS548-05 Description The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using IDT s patented analog/digital
PI2PCIE2214. PCI Express 2.0, 1-lane, 4:1 Mux/DeMux Switch. Features. Description. Application. Pin Description. Block Diagram.
Features 2 Differential Channel, 4:1 Mux/DeMux PCI Express 2.0 performance, 5.0 Gbps Low Bit-to-Bit Skew, 7ps Max. Low Crosstalk: -23dB@3GHz Low Off Isolation: -23dB@3GHz Operating Range: 1.8V ±10% ESD
SM Features. General Description. Typical Application MHz/312.5MHz and MHz/156.25MHz LVDS Clock Synthesizer.
156.25MHz/312.5MHz and 78.125MHz/156.25MHz LVDS Clock Synthesizer ClockWorks Flex General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise
PI6C GHz 1:4 LVPECL Fanout Buffer with Internal Termination GND Q0+ Q0- REF_IN+ V TH V REF-AC REF_IN- Q1+ Q1- Q2+ Q2- Q3+ Q3- VDD.
Features ÎÎInput Clock Frequency up to 6 GHz Typical ÎÎ4 pairs of differential LVPECL outputs ÎÎLow additive jitter, < 0.05ps (max) ÎÎInput CLK accepts: LVPECL, LVDS, CML, SSTL input level ÎÎOutput to
SM General Description. Features. Block Diagram. ClockWorks TM 125MHz LVDS / 125 MHz HCSL Ultra-Low Jitter Frequency Synthesizer
ClockWorks TM 125MHz LVDS / 125 MHz HCSL Ultra-Low Jitter Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise timing
PI6C20800B. PCI Express 3.0 1:8 HCSL Clock Buffer. Features. Description. Pin Configuration (48-Pin TSSOP)
PCI Express 3.0 1:8 HCSL Clock Buffer Features Î ÎPhase jitter filter for PCIe 3.0 application Î ÎEight Pairs of Differential Clocks Î ÎLow skew < 50ps (PI6C20800B),
ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS548A-03 Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.
PI6C20400A. 1:4 Clock Driver for Intel PCIe Chipsets. Features. Description. Pin Configuration. Block Diagram
Features Phase jitter filter for PCIe 2.0 application Four Pairs of Differential Clocks Low skew < 50ps Low jitter < 50ps cycle-to-cycle < 1 ps additive RMS phase jitter Output Enable for all outputs Outputs
SM Features. General Description. Applications. Block Diagram
ClockWorks Fibre Channel (106.25MHz, 212.5MHz) Ultra-Low Jitter, LVDS Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely
SY89645L. General Description. Features. Block Diagram. Applications. Markets. Precision Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer
Precision Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer General Description The is a 3.3V, fully differential, low skew, 1:4 LVDS fanout buffer that accepts LVTTL or LVCMOS inputs. It is capable
PI6C GND REF_IN+ V TH V REF-AC REF_IN- Q0+ Q0- Q1+ Q1- VDD. 6 GHz / 12 Gbps Clock / Data Fanout Buffer with Internal Termination.
Features ÎÎInput Clock Frequency up to 6 GHz Typical ÎÎMaximum Input Data Rate up to 12 Gbps Typical ÎÎ2 pairs of differential CML outputs ÎÎLow additive jitter, < 0.05ps (max) ÎÎInput accepts: CML, LVDS,
A product Line of Diodes Incorporated. Description OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3#
1:4 Clock Driver for Intel PCIe 3.0 Chipsets Features ÎÎPhase jitter filter for PCIe 3.0 application ÎÎFour Pairs of Differential Clocks ÎÎLow skew < 50ps ÎÎLow jitter < 50ps cycle-to-cycle Î Î< 1 ps additive
PI6C20800S. PCI Express 1:8 HCSL Clock Buffer. Features. Description. Pin Configuration. Block Diagram
Features Phase jitter filter for PCIe application Eight Pairs of Differential Clocks Low skew < 50ps (PI6C20800S),
PI3PCIE V, PCI Express 1-lane, 2:1 Mux/DeMux Switch. Features. Description. Application. Pin Description (Top-side view) Truth Table
3.3V, PCI Express 1-lane, Features 2 Differential Channel, 2:1 Mux/DeMux PCI Express 2.0 Performance, 5.0Gbps Pinout optimized for placement between two PCIe slots Bi-directional operation Low Bit-to-Bit
Not recommended for new designs
Eight Output Differential Buffer for PCI-Express Recommended Application: DB800 Intel Yellow Cover part with PCI-Express support. Output Features: 8-0.7V current-mode differential output pairs Supports
Description. Application. Block Diagram
3.3V PCI Express 3.0 2-Lane Exchange Switch Features ÎÎ8 Differential Channel (2-lane) Exchange ÎÎPCI Express 3.0 performance, 8.0 Gbps ÎÎBi-directional operation ÎÎLow Bit-to-Bit Skew: 10ps (between ±
PI6C182B. Precision 1-10 Clock Buffer. Features. Description. Diagram. Pin Configuration
Features Low noise non-inverting 1-10 buffer Supports frequency up to 140 MHz Supports up to four SDRAM DIMMs Low skew (
Features. Applications
2.5/3.3V 1-to-1 Differential to LVCMOS/LVTTL Translator Precision Edge General Description Micrel s is a 1-to-1, differential-to-lvcmos / LVTTL translator. The differential input is highly flexible and
TF90LVDS047-6CG. Quad LVDS Line Driver with Flow-Through Pinout. Description. Features. Applications. Function Diagram. Ordering Information
Features Companion driver to Quad Extended Common Mode LVDS Receiver TF0LVDS048 DC to 400 Mbps / 200 MHz low noise, low skew, low power operation t 350 ps (max) channel-to-channel skew t 250 ps (max) pulse
Features. o HCSL, LVPECL, or LVDS o Mixed Outputs: LVPECL/HCSL/LVDS. o Ext. Industrial: -40 to 105 C o o. o 30% lower than competing devices
DSC55704 Crystalless Three Output PCIe Clock Generator General Description The DSC55704 is a Crystalless, three output PCI express clock generator meeting Gen1, Gen2, and Gen3 specifications. The clock
CAP+ CAP. Loop Filter
STS-12/STS-3 Multirate Clock and Data Recovery Unit FEATURES Performs clock and data recovery for 622.08 Mbps (STS-12/OC-12/STM-4) or 155.52 Mbps (STS-3/OC-3/STM-1) NRZ data 19.44 MHz reference frequency
Features. Applications
Ultra-Precision 1:8 CML Fanout Buffer with Internal I/O Termination General Description The is a 2.5V/3.3V precision, high-speed, fully differential CML 1:8 fanout buffer. The is optimized to provide eight
Pin Configuration and Selector Guide appear at end of data sheet. Typical Operating Circuits
Rev 2; 4/08 106.25MHz/212.5MHz/425MHz General Description The DS4106, DS4212, and DS4425 ceramic surfacemount crystal oscillators are part of Maxim s DS4-XO series of crystal oscillators. These devices
PI6C :4 Clock Driver for Intel PCI Express Chipsets. Features. Description. Block Diagram. Pin Configuration
Features Four Pairs of Differential Clocks Low skew < 50ps Low jitter < 50ps Output Enable for all outputs Outputs tristate control via SMBus Power Management Control Programmable PLL Bandwidth PLL or
PI3HDMI231-A. 3:1 ActiveEye HDMI TM Switch with Electrical Idle Detect
Features 3 digital video inputs can be switched to a single output Each input can be AC coupled video or DC coupled, while the output will maintain its DC coupled, current-steering, TMDS compliance TMDS
Clock Generator for PowerQUICC and PowerPC Microprocessors and
Freescale Semiconductor Technical Data Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers Clock Generator for PowerQUICC and PowerPC Microprocessors and DATA SHEET Rev 1, 11/2004
MPC9817ENR2. Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers DATA SHEET NRND
Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers MPC9817 DATA SHEET NRND The MPC9817 is a PLL-based clock generator specifically designed for Freescale Semiconductor Microprocessor
Wireless Access Point Server/Storage DIFF1 DIFF2
PCI-EXPRESS GEN 1, GEN 2, AND GEN 3 1:2 FAN-OUT CLOCK BUFFER Features PCI-Express Gen 1, Gen 2, and Gen 3 compliant devices Two low-power PCIe clock outputs Supports Serial-ATA (SATA) at 100 MHz No termination
DSC2033. Low-Jitter Configurable Dual LVDS Oscillator. General Description. Features. Block Diagram. Applications
General Description The series of high performance dual output LVDS oscillators utilize a proven silicon MEMS technology to provide excellent jitter and stability while incorporating additional device
Frequency Generator for Pentium Based Systems
Integrated Circuit Systems, Inc. ICS969C-23 Frequency Generator for Pentium Based Systems General Description The ICS969C-23 is a low-cost frequency generator designed specifically for Pentium-based chip
Features. Applications
3.3V Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination General Description The is a 3.3V, high-speed 2GHz differential low voltage differential swing (LVDS) 1:4 fanout buffer
PI5USB66. USB Charge Controller IC for Single USB Port. Features. Description. Pin Configuration. Applications
Features ÎÎManages communication to allow charging to occur ÎÎProvides multiple modes of charging to ensure all of the following specs can be met: DCP mode per USB BC.0,., &. spec YD/T - 59 charger spec
ILI2511. ILI2511 Single Chip Capacitive Touch Sensor Controller. Specification ILI TECHNOLOGY CORP. Version: V1.4. Date: 2018/7/5
Single Chip Capacitive Touch Sensor Controller Specification Version: V1.4 Date: 2018/7/5 ILI TECHNOLOGY CORP. 8F., No.1, Taiyuan 2 nd St., Zhubei City, Hsinchu County 302, Taiwan (R.O.C.) Tel.886-3-5600099;
3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION
3.3V, 2.0GHz ANY DIFF. -TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ TERNAL TERMATION FEATURES Guaranteed AC performance > 2.0GHz f MAX output toggle > 3.0GHz f MAX input < 800ps t PD (matched-delay
DSC Q0093. General Description. Features. Applications. Block Diagram. Crystal-less Configurable Clock Generator
Crystal-less Configurable Clock Generator General Description The is a four output crystal-less clock generator. It utilizes Microchip's proven PureSilicon MEMS technology to provide excellent jitter and
Control Circuitry 2 M1. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
Crystal-less Configurable Clock Generator General Description The is a programmable, high performance dual LVDS output oscillator utilizing Micrel's proven silicon MEMS technology to provide excellent
ESD Sensitive. Parameters Minimum Typical Maximum Units Notes ppm. Parameters Minimum Typical Maximum Units Notes
Moisture Sensitivity Level (MSL) 1 FEATURES: LVCMOS, LVDS or LVPECL output option +2.5V or +3.3V operation -40 C to +85 C standard operating temperature range Ultra low RMS Jitter: 0.5ps typical, 1.0ps
PART OBSOLETE - USE PI3PCIE3442A
PART OBSOLETE - USE A 3.3V PCI Express 3.0 2-Lane Exchange Switch Features ÎÎ8 Differential Channel (2-lane) Exchange ÎÎPCI Express 3.0 performance, 8.0 Gbps ÎÎBi-directional operation ÎÎLow Bit-to-Bit
ZL40218 Precision 1:8 LVDS Fanout Buffer
Precision 1:8 LVDS Fanout Buffer Data Sheet Features Inputs/Outputs Accepts differential or single-ended input LVPECL, LVDS, CML, HCSL, LVCMOS Eight precision LVDS outputs Operating frequency up to 750
1000 Base-T, ±15kV ESD Protection LAN Switch
19-0841; Rev 0; 6/07 1000 Base-T, ±15kV ESD Protection LAN Switch General Description The meets the needs of high-speed differential switching, including that of Gigabit Ethernet (10/100/1000) Base-T switching
PART OBSOLETE - USE PI3PCIE3242A
PART OBSOLETE - USE A 3.3V PCI Express 3.0 4 Channel 2x2 Exchange Switch Features ÎÎ4 Differential Channel 2x2 Exchange Switch ÎÎPCI Express 3.0 performance, 8.0 Gbps ÎÎBi-directional operation ÎÎLow Bit-to-Bit
I.C. PCLK_IN DE_IN GND CNTL_IN1 RGB_IN0 RGB_IN1 RGB_IN2 RGB_IN3 RGB_IN4 RGB_IN5 RGB_IN6 RGB_IN7 CNTL_IN7 CNTL_IN6 CNTL_IN5 CNTL_IN4 CNTL_IN3 CNTL_IN2
19-3558; Rev 4; 8/09 EVALUATION KIT AVAILABLE 27-Bit, 3MHz-to-35MHz General Description The digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen
SY89610L. General Description. Features. Applications MHz to 694MHz Jitter Attenuator and Low Phase Noise Frequency Synthesizer
77.75MHz to 694MHz Jitter Attenuator and Low Phase Noise Frequency Synthesizer General Description The is a 3.3V, fully differential jitter attenuator and frequency synthesizer that accepts a noise clock
Enhanced 1:2 VGA Mux with Monitor Detection and Priority Port Logic
EVALUATION KIT AVAILABLE MAX14983E General Description The MAX14983E integrates high-bandwidth analog switches, level-translating buffers, and 5V power switches to implement a complete 1: multiplexer for
ZL40223 Precision 2:8 LVDS Fanout Buffer with Glitchfree Input Reference Switching and On-Chip Input Termination Data Sheet
Features Inputs/Outputs Accepts two differential or single-ended inputs LVPECL, LVDS, CML, HCSL, LVCMOS Glitch-free switching of references On-chip input termination and biasing for AC coupled inputs Eight
1000 Base-T, ±15kV ESD Protection LAN Switches
19-0624; Rev 0; 8/06 1000 Base-T, ±15kV ESD Protection LAN Switches General Description The meet the needs of high-speed differential switching. The devices handle the needs of Gigabit Ethernet (10/100/1000)
Applications +5V V CC V S EN SYNCH0, SYNCV0 SDA0, SCL0 RED SYNCH1, SYNCV1 SDA1, SCL1 MAX14895E BLU GND
19-5819; Rev ; 3/11 E V A L U A T I O N K I T A V A I L A B L E MAX14895E General Description The MAX14895E integrates level-translating buffers and features RED, GRN, and BLU (RGB) port protection for
EVALUATION KIT AVAILABLE High-Bandwidth, VGA 2:1 Switch with ±15kV ESD Protection
19-5; Rev ; 1/9 EVALUATION KIT AVAILABLE High-Bandwidth, VGA :1 Switch General Description The integrates high-bandwidth analog switches, level-translating buffers, and level-translating FET switches to
3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with INTERNAL INPUT TERMINATION
3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with TERNAL PUT TERMATION FEATURES Selects among four differential inputs Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput
3.3V CMOS/PECL/LVDS OUTPUT SMD VCXO
FEATURES: CMOS, PECL or LVDS Output Low Integrated rms jitter (1 max. over 12kHz to 20MHz BW) Low Profile, Seam-Sealed Package (5.08 x 7.0 x1.8mm) Wide Frequency Pull Range (±100 ppm min.) Pb RoHS/RoHS
2.5V, 3.2Gbps, DIFFERENTIAL 4:1 LVDS MULTIPLEXER WITH INTERNAL INPUT TERMINATION
2.5V, 3.2Gbps, DIFFERENTIAL 4:1 LVDS MULTIPLEXER WITH TERNAL PUT TERMATION FEATURES Selects among four differential inputs Guaranteed AC performance over temp and voltage: DC-to > 3.2Gbps data rate throughput
TF10CP02 / TF10CP Gbps 2x2 LVDS Crosspoint Switches. Features. Description. Applications. Function Diagram. Ordering Information.
Features DC to 1.5 Gbps low jitter, low skew, low power operation Pin configurable, fully differential, non-blocking architecture eases system design and PCB layout On-chip 100W input termination minimizes
Si52111-B5/B6 PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR. Features. Applications. Description. Functional Block Diagram
PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR Features PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant Gen 3 SRNS Compliant Low power HCSL differential output buffer Supports Serial-ATA
CARDINAL COMPONENTS, INC.
SERIES CJTDAE CJTDAL The Cardinal Cappuccino Crystal Oscillator LVDS/ LVPECL TCXO Features 3.3V supply voltage- configurable 10MHz to 250MHz LVDS and LVPECL outputs- configurable Better than 2Hz tuning
Two Outputs Clock Generator AK8146B
ASAHI KASEI EMD CORPORATION Two Outputs Clock Generator AK8146B Features Pin Selectable External Input - 74.17582MHz - 74.25MHz - 60MHz Clock out Frequencies: - 12.000MHz - 13.5MHz Low Jitter Performance
CARDINAL COMPONENTS, INC.
SERIES CJAL CJAE The Cardinal Cappuccino Crystal Oscillator LVDS/ LVPECL Features 2.5V or 3.3V supply voltageconfigurable 10MHz to 250MHz LVDS and LVPECL outputs- configurable Better than 2Hz tuning resolution
STANDARD SPECIFICATIONS:
Moisture Sensitivity Level MSL 1 FEATURES: APPLICATIONS: Ultra Miniature Pure SiliconTM Clock Oscillator Storage Area Networks (SATA, SAS, Fiber Channel) High Performance MEMS Technology by Discera Passive
1.8V/3.0V Single-PLL Clock Generator
ASAHI KASEI EMD CORPORATION 1.8V/3.0V Single-PLL Clock Generator Features Input Frequency: 36 MHz (1.8V or 3.0V) PLL Output Frequency: 12 MHz (1.8V or 3.0V) REF Output Frequency: 36 MHz or 18 MHz (1.8V
Features RX0+ RX0- RX1+ RX1- RX2+ RX2- RX3+ RX3- RCK+ RCK- PWRDWN
General Description The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second.
Control Circuitry 2 M1. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
DSC2044FE1H0002 Crystalless Configurable Clock Generator General Description The DSC2044FE1H0002 is a programmable, high performance dual HCSL output oscillator utilizing Micrel's proven silicon MEMS technology
Triangular spread spectrum profile for maximum EMI reduction (Si50122-A2) 2.5 V, 3.3 V Power supply. (2.0 x 2.5 mm) down spread outputs
CRYSTAL-LESS PCI-EXPRESS GEN1 DUAL OUTPUT CLOCK GENERATOR Features Crystal-less clock generator with integrated CMEMS PCI-Express Gen 1 compliant Triangular spread spectrum profile for maximum EMI reduction
Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
DSC2311KL2R008 Crystalless Configurable Clock Generator General Description DSC2311KL2R008 is a crystalless clock generator that is factory configurable to simultaneously output two separate frequencies
XRD8775 CMOS 8-Bit High Speed Analog-to-Digital Converter
CMOS 8-Bit High Speed Analog-to-Digital Converter April 2002-4 FEATURES 8-Bit Resolution Up to 20MHz Sampling Rate Internal S/H Function Single Supply: 5V V IN DC Range: 0V to V DD V REF DC Range: 1V to
PERFORMANCE PLASTIC PACKAGE ULTRA MINIATURE PURE SILICON TM CLOCK OSCILLATOR
STANDARD SPECIFICATIONS: Moisture Sensitivity Level MSL 1 APPLICATIONS: FEATURES: Ultra Miniature Pure Silicon TM Clock Oscillator High Performance MEMS Technology by Discera Low Power Consumption for
Pentium Processor Compatible Clock Synthesizer/Driver for ALI Aladdin Chipset
1CY 225 7 fax id: 3517 Features Multiple clock outputs to meet requirements of ALI Aladdin chipset Six CPU clocks @ 66.66 MHz, 60 MHz, and 50 MHz, pin selectable Six PCI clocks (CPUCLK/2) Two Ref. clocks
Low Power Multiclock Generator with XO AK8137A
Low Power Multiclock Generator with XO AK8137A Features 25MHz Crystal Input One 25MHz-Reference Output Selectable Clock out Frequencies: - 100, 133, 166, 200MHz - 96MHz - 100MHz - 25MHz Low Jitter Performance
YB1300S Switched Capacitor Boost Converter 5V/4.5V
Description The YB1300S is a switched capacitor DC/DC boost converter that produces a regulated 5V output. The input voltage range is from 2.7V to 5.0V that makes the YB1300S ideally for a single cell
1.8V/3.0V Single-PLL Clock Generator AK8150C
AK8150C 1.8V/3.0V Single-PLL Clock Generator AK8150C Features Input Frequency: 38 MHz (1.8V or 3.0V) PLL Output Frequency: 12 MHz (1.8V or 3.0V) REF Output Frequency: 38 MHz or 19 MHz (1.8V or 3.0V) Low
XRD87L85 Low-Voltage CMOS 8-Bit High-Speed Analog-to-Digital Converter
Low-Voltage CMOS 8-Bit High-Speed Analog-to-Digital Converter April 2002-1 FEATURES 8-Bit Resolution Up to 10 MHz Sampling Rate Internal S/H Function Single Supply: 3.3V VIN DC Range: 0V to V DD VREF DC
DATA SHEET. Features. General Description. Block Diagram
LVCMOS Clock Generator ICS870919I DATA SHEET General Description The ICS870919I is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew
PERFORMANCE PLASTIC PACKAGE ULTRA MINIATURE PURE SILICON TM CLOCK OSCILLATOR ASEMP
Moisture Sensitivity Level MSL 1 APPLICATIONS: FEATURES: Ultra Miniature Pure Silicon TM Clock Oscillator High Performance MEMS Technology by Discera Low Power Consumption for high speed communication
100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs
Features Mixed 2.5V and 3.3V operation Complete clock solution for Pentium II, and other similar processor-based motherboards Two CPU clocks at 2.5V up to 100 MHz Six synchronous PCI clocks, one free-running
VDD = V, TA = -40 C to +85 C, outputs terminated with 100 Ohms between Q and /Q.³
Ultra-Low Jitter 200MHz LVDS XO ClockWorks FUSION General Description The is an ultra-low phase jitter XO with LVDS output optimized for high line rate applications. Features 200MHz LVDS Typical phase
MAX14653/MAX14654/ MAX14655/MAX High-Current Overvoltage Protectors with Adjustable OVLO
EVALUATION KIT AVAILABLE MAX14653/MAX14654/ General Description The MAX14653/MAX14654/ overvoltage protection devices feature a low 38mΩ (typ) R ON internal FET and protect low-voltage systems against
PI3VDP411LS. Digital Video Level Shifter from AC Coupled Digital Video Input to a DVI/HDMI Transmitter. Features. Description
Features ÎÎConverts low-swing AC coupled differential input to HDMI rev 1.3 compliant open-drain current steering Rx terminated differential output ÎÎHDMI level shifting operation up to 2.5Gbps per lane
PI5USB1468 PI5USB1468A
Features ÎÎManages communication to allow charging to occur ÎÎProvides multiple modes of charging to ensure all of the following specs can be met: DCP, CDP, and SDP per BC.0,.,. spec DCP per YD/T-59 spec
FIN1101 LVDS Single Port High Speed Repeater
FIN1101 LVDS Single Port High Speed Repeater General Description This single port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. It accepts
133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support
133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support Features Mixed 2.5V and 3.3V Operation Compliant to Intel CK133 (CY2210-3) & CK133W (CY2210-2) synthesizer and driver specification
CLEARCLOCK POWER OPTIMIZED 0.12ps 5x7mm XO
FEATURES APPLICATIONS 0.125ps typ jitter (150fs MAX f > 200MHz, 25 C Highest in-class frequency range from 50 to 2100MHz Excellent spurious suppresion 70mA MAX I DD (LVDS, any V DD Lowest in-class power
Overvoltage-Protection Controllers with a Low RON Internal FET MAX4970/MAX4971/MAX4972
19-4139; Rev 1; 8/08 Overvoltage-Protection Controllers General Description The family of overvoltage protection devices features a low 40mΩ (typ) R ON internal FET and protect low-voltage systems against
FIN1102 LVDS 2 Port High Speed Repeater
LVDS 2 Port High Speed Repeater General Description This 2 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The FIN1102 accepts and
CKSET V CC _VCO FIL SDO+ MAX3952 SCLKO+ SCLKO- PRBSEN LOCK GND TTL
19-2405; Rev 0; 4/02 10Gbps 16:1 Serializer General Description The 16:1 serializer is optimized for 10.3Gbps and 9.95Gbps Ethernet applications. A serial clock output is provided for retiming the data
PI5USB268. USB Host Charge Controller IC for Dual USB Ports. Features. Description. Pin Configuration, 20QE (Top View) Applications
s Features ÎÎManages communication to allow charging to occur from 2 USB ports ÎÎProvides multiple modes of charging to ensure all of the following specs can be met: BC.0,., &.2 spec YD/T - 59 Chinese
Ultra-Low Phase Jitter LVDS SMD Clock Oscillator
Ultra-Low Phase Jitter LDS SMD Clock Oscillator ESD Sensitive Moisture Sensitivity Level MSL 3 FEATURES: 50MHz LDS Typical phase noise: 121fs (Integration range: 1.875MHz-20MHz) ±50ppm total frequency
ILI2312. ILI2312 Single Chip Capacitive Touch Sensor Controller. Specification ILI TECHNOLOGY CORP. Version: V1.03.
Single Chip Capacitive Touch Sensor Controller Specification Version: V1.03 Date: 2015/11/17 ILI TECHNOLOGY CORP. 8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302, Taiwan, R.O.C. Tel.886-3-5600099;
Features MIC2551A VBUS R S. 1.5k D+ D GND VM D SPD SUS GND. Typical Application Circuit
MIC2551 USB Transceiver General Description The MIC2551 is a single chip transceiver that complies with the physical layer specifications of the Universal Serial Bus (USB) 2.0. It supports both full speed
Chrontel CH7304 Single LVDS Transmitter
Chrontel Chrontel Single LVDS Transmitter Features 1.0 General Description Single LVDS transmitter Supports pixel rate up to 165M pixels/sec Supports up to UXGA resolution (1600 x 100) LVDS low jitter
Features. Applications
6GHz, 1:4 CML Fanout Buffer/Translator with Internal I/O Termination General Description The is a 2.5V/3.3V precision, high-speed, fully differential 1:4 CML fanout buffer. Optimized to provide four identical
DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater
DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater General Description The DS90LV804 is a four channel 800 Mbps LVDS buffer/ repeater. In many large systems, signals are distributed across cables and signal