NB3W1900L. 3.3 V 100/133 MHz Differential 1:19 HCSL-Compatible Push Pull Clock ZDB/Fanout Buffer for PCIe

Transcription

1 3.3 V 00/33 MHz Differential :9 HCSL-Compatible Push Pull Clock ZDB/Fanout Buffer for PCIe Description The NB3W900L differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point-to-point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel QuickPath Interconnect (Intel QPI), PCIe Gen/Gen2/Gen3.The NB3W900L internal PLL is optimized to support 00 MHz and 33 MHz frequency operation. The NB3W900L is developed with the low-power NMS Push-Pull buffer type. Features 9 Low Power Differential Clock utput 0.7V utput-to-utput Skew Performance: < 85 ps Cycle-to-Cycle Jitter (PLL Mode): < 50ps Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant) Input-to-utput Delay Variation: < 50 ps Fixed-Feedback for Lowest Input-to-utput Delay Variation Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI 00 MHz and 33 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter Individual E Control via SMBus Low-Power NMS Push-Pull HCSL Compatible utputs PLL Configurable for PLL Mode or Bypass Mode (Fanout peration) SMBus Address Configurable to Allow Multiple Buffers in a Single Control Network Programmable PLL Bandwidth Two Tri-level Addresses Selection (Nine SMBus Addresses) QFN 72-pin Package, 0 mm 0 mm These are Pb-Free Devices A WL YY WW G 72 QFN72 MN SUFFIX CASE 485DK MARKING DIAGRAM NB3W 900L AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package RDERING INFRMATIN See detailed ordering and shipping information on page 7 of this data sheet. Semiconductor Components Industries, LLC, 204 ctober, 204 Rev. 0 Publication rder Number: NB3W900L/D

2 FBUT_NC FBUT_NC# CLK_IN CLK_IN# SSC Compatible PLL MUX DIF[8:0] DIF[8:0]# 00M_33M# HBW_BYP_LBW# SA_0 SA_ PWRGD/PWRDN# SDA SCL Control Logic Figure. Simplified Block Diagram VDDA A 00M_33M# HBW_BYP_LBW# PWRGD/PWRDN# VDDR CLK_IN CLK_IN# SA_ DIF2# DIF2 VDDI DIF# DIF DIF0# DIF0 VDD SDA 44 DIF9# SCL 2 43 DIF9 SA_ 3 42 DIF8# FBUT_NC# 4 4 DIF8 FBUT_NC 5 40 VDDI 6 39 DIF DIF7# DIF0# DIF7 DIF DIF# VDDI DIF2 DIF2# DIF3 DIF3# VDD DIF4 DIF4# DIF5 DIF5# VDDI DIF6 DIF6# DIF8# DIF8 VDDI DIF7# DIF7 DIF6# DIF6 VDD DIF5# DIF5 DIF4# DIF4 VDDI DIF3# DIF3 NB3W900L Figure 2. Pin Configuration (Top View) 2

3 Table. PWER DWN PIN TABLE PWRGD/PWRDN# Inputs Control Bits utputs CLK_IN / CLK_IN# SMBus EN Bit DIFx / DIFx# FBUT_NC / FBUT_NC# PLL Stage 0 X X Low/Low Low/Low FF Running 0 Low/Low Running N Running Running N Table 2. PWER CNNECTINS Pin Number VDD VDDI VDDR Description 7 2 Analog Input 6 Analog PLL 28, 45, 64 2, 33, 40, 52, 57, 69 6, 22, 27, 34, 39, 46, 5, 58, 63, 70 DIF clocks Table 3. TRI-LEVEL INPUT THRESHLDS Level Voltage Low < 0.8 V Mid.2 < Vin <.8 V High Vin > 2.2 V Table 4. FUNCTINALITY AT PWER-UP (PLL Mode) CLK_IN DIFx 00M_33M# MHz MHz CLK_IN CLK_IN Table 5. PLL PERATING MDE HBW_BYP_LBW# MDE Low PLL Lo BW Mid Bypass High PLL Hi BW NTE: PLL is FF in Bypass Table 6. MDE TRI LEVEL INPUT THRESHLD Level Voltage Low < 0.8 V Mid.2 < Vin <.8 V High Vin > 2.2 V 3

4 Table 7. NB3W900L PIN DESCRIPTINS Pin Number Pin Name Type Description VDDA PWR 3.3 V Power Supply for PLL core. 2 A Ground for PLL core. 3 00M_33M# IN Input to select operating frequency. See functionality table for definition. 4 HBW_BYP_LBW# IN Tri-level input to select High BW, Bypass or low BW mode. See PLL operating mode table for definition. 5 PWRGD/PWRDN# IN Notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. Low enters power down mode. 6 Ground pin 7 VDDR PWR 3.3 V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. 8 CLK_IN IN 0.7 V differential true input 9 CLK_IN# IN 0.7 V differential complementary input 0 SA_0 IN SMBus address bit. This is a tri-level input that works in conjunction with the SA_ to decode of 9 SMBus addresses. SDA I/ Data pin of SMBus circuitry, 5 V tolerant 2 SCL IN Clock pin of SMBus circuitry, 5 V tolerant 3 SA_ IN SMBus address bit. This is a tri-level input that works in conjunction with the SA_0 to decode of 9 SMBus addresses. 4 FBUT_NC# UT Complementary half of differential feedback output. This pin should NT be connected to anything outside the chip. It exists to provide delay path matching to get 0 ps propagation delay. 5 FBUT_NC UT True half of differential feedback output. This pin should NT be connected to anything outside the chip. It exists to provide delay path matching to get 0 propagation delay. 6 Ground pin 7 DIF0 UT 0.7 V differential true clock output 8 DIF0# UT 0.7 V differential complementary clock output 9 DIF UT 0.7 V differential true clock output 20 DIF# UT 0.7 V differential complementary clock output 2 VDDI PWR Power supply for differential outputs 22 Ground pin 23 DIF2 UT 0.7 V differential true clock output 24 DIF2# UT 0.7 V differential complementary clock output 25 DIF3 UT 0.7 V differential true clock output 26 DIF3# UT 0.7 V differential complementary clock output 27 Ground pin 28 VDD PWR Power supply nominal 3.3 V 29 DIF4 UT 0.7 V differential true clock output 30 DIF4# UT 0.7 V differential complementary clock output 3 DIF5 UT 0.7 V differential true clock output 32 DIF5# UT 0.7 V differential complementary clock output 33 VDDI PWR Power supply for differential outputs 34 Ground pin 35 DIF6 UT 0.7 V differential true clock output. All VDD, VDDR, VDDI,VDDA and pins must be externally connected to a power supply for proper operation. 4

5 Table 7. NB3W900L PIN DESCRIPTINS (continued) Pin Number Pin Name Type Description 36 DIF6# UT 0.7 V differential complementary clock output 37 DIF7 UT 0.7 V differential true clock output 38 DIF7# UT 0.7 V differential complementary clock output 39 Ground pin 40 VDDI PWR Power supply for differential outputs 4 DIF8 UT 0.7 V differential true clock output 42 DIF8# UT 0.7 V differential complementary clock output 43 DIF9 UT 0.7 V differential true clock output 44 DIF9# UT 0.7 V differential complementary clock output 45 VDD PWR Power supply nominal 3.3 V 46 Ground pin 47 DIF0 UT 0.7 V differential true clock output 48 DIF0# UT 0.7 V differential complementary clock output 49 DIF UT 0.7 V differential true clock output 50 DIF# UT 0.7 V differential complementary clock output 5 Ground pin 52 VDDI PWR Power supply for differential outputs 53 DIF2 UT 0.7 V differential true clock output 54 DIF2# UT 0.7 V differential complementary clock output 55 DIF3 UT 0.7 V differential true clock output 56 DIF3# UT 0.7 V differential complementary clock output 57 VDDI PWR Power supply for differential outputs 58 Ground pin 59 DIF4 UT 0.7 V differential true clock output 60 DIF4# UT 0.7 V differential complementary clock output 6 DIF5 UT 0.7 V differential true clock output 62 DIF5# UT 0.7 V differential complementary clock output 63 Ground pin 64 VDD PWR Power supply nominal 3.3 V 65 DIF6 UT 0.7 V differential true clock output 66 DIF6# UT 0.7 V differential complementary clock output 67 DIF7 UT 0.7 V differential true clock output 68 DIF7# UT 0.7 V differential complementary clock output 69 VDDI PWR Power supply for differential outputs 70 Ground pin 7 DIF8 UT 0.7 V differential true clock output 72 DIF8# UT 0.7 V differential complementary clock output EP Exposed Pad Thermal The Exposed Pad (EP) on the QFN-72 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to on the PC board.. All VDD, VDDR, VDDI,VDDA and pins must be externally connected to a power supply for proper operation. 5

6 Table 8. ABSLUTE MAXIMUM RATINGS (Note 2) Symbol Parameter Conditions Min Typ Max Unit V DD / V DDA / V DDR 3.3 V Core Supply Voltage (Note 3) 4.6 V V DD / V DDI 3.3 V Logic and utput Supply Voltage (Note 3) 4.6 V V IH Input High Voltage Except for SMBus Interface V DD V V IH VIHSMB SMBus Clock and Data Pins 5.5 V V IL Input Low Voltage 0.5 V Ts Storage Temperature C T J Junction Temperature 25 C ESD prot. ESD Protection (Human Body) Human Body Model 2000 V JA Thermal Resistance Junction to Ambient Still air 8. C/W JC Thermal Resistance Junction to Case 5.0 C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Guaranteed by design and characterization, not tested in production. 3. peration under these conditions is neither implied nor guaranteed. Table 9. ELECTRICAL CHARACTERISTICS CLCK INPUT PARAMETERS (T A =0 C 70 C; Supply Voltage V DD /V DDA = 3.3 V ±5%, V DDI =.05 to 3.3 V ±5%. See Test Loads for Loading Conditions) (Note 4) Symbol Parameter Conditions Min Typ Max Unit V IHDIF Input High Voltage CLK_IN Differential Inputs (single-ended measurement) V ILDIF Input Low Voltage CLK_IN Differential Inputs (single-ended measurement) mv V SS mv V CM Input Common Mode Voltage CLK_IN (not spec d) Common Mode Input Voltage mv V SWING Input Amplitude CLK_IN not spec d Peak to Peak Value mv dv/dt Input Slew Rate CLK_IN (Note 5) Measured Differentially V/ns I IN Input Leakage Current V IN = V DD, V IN = 5 5 A d tin Input Duty Cycle Measurement from Differential Waveform % J DIFIn Input Jitter Cycle to Cycle Differential Measurement 0 25 ps Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Guaranteed by design and characterization, not tested in production. 5. Slew rate measured through ±75 mv window centered around differential zero Table 0. ELECTRICAL CHARACTERISTICS INPUT/SUPPLY/CMMN UTPUT PARAMETERS (T A =0 C 70 C; Supply Voltage V DD /V DDA = 3.3 V ±5%, V DDI =.05 V to 3.3 V ±5%. See Test Loads for Loading Conditions) (Note 6) Symbol Parameter Conditions Min Typ Max Unit V IH Input High Voltage Single-ended inputs, except SMBus, low threshold and tri-level inputs V IL Input Low Voltage Single-ended inputs, except SMBus, low threshold and tri level inputs 2 V DD V V I IN Input Current Single-ended inputs, V IN =, V IN = V DD 5 5 A V IH_FS Input High Voltage (Note 7) 0.7 V DD V V IL_FS Input Low Voltage (Note 7) V 6

7 Table 0. ELECTRICAL CHARACTERISTICS INPUT/SUPPLY/CMMN UTPUT PARAMETERS (continued) (T A =0 C 70 C; Supply Voltage V DD /V DDA = 3.3 V ±5%, V DDI =.05 V to 3.3 V ±5%. See Test Loads for Loading Conditions) (Note 6) Symbol Parameter Conditions F ibyp Input Frequency V DD = 3.3 V, Bypass mode (Note 8) MHz F ipll V DD = 3.3 V, MHz PLL mode (Note 8) MHz F ipll V DD = 3.3 V, MHz PLL mode (Note 8) MHz L pin Pin Inductance 7 nh C IN Capacitance Logic Inputs, except CLK_IN.5 5 pf C INCLK_IN CLK_IN differential clock inputs (Note 0) pf C UT utput pin capacitance 6 pf T STAB Clk Stabilization (Note 8) From V DD Power-Up and after input clock stabilization or de-assertion of PD# to st clock f MDIN Input SS Modulation Frequency Allowable Frequency (Triangular Modulation) t LATE# E# Latency DIF start after E# assertion DIF stop after E# de-assertion t DRVPD Tdrive_PD# (Note 9) DIF output enable after PD# de-assertion Min Typ Max Unit ms khz 4 2 clocks 300 s t F Tfall (Note 8) Fall time of control inputs 5 ns t R Trise (Note 8) Rise time of control inputs 5 ns V ILSMB SMBus Input Low Voltage 0.8 V V IHSMB SMBus Input High Voltage 2. V DDSMB V V LSMB SMBus utput Low I PULLUP 0.4 V I PULLUP SMBus Sink V L 4 ma V DDSMB Nominal Bus Voltage 3 V to 5 V ±0% V t RSMB SCL/SDA Rise Time (Max VIL 0.5) to (Min VIH + 0.5) 000 ns t FSMB SCL/SDA Fall Time (Min VIH + 0.5) to (Max VIL 0.5) 300 ns f MAXSMB SMBus perating Frequency (Note ) Maximum SMBus operating frequency 00 khz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Guaranteed by design and characterization, not tested in production M_33M# Frequency Select (FS). 8. Control input must be monotonic from 20% to 80% of input swing. 9. Time from de-assertion until outputs are > 200 mv 0.CLK_IN input. The differential input clock must be running for the SMBus to be active 7

8 Table. ELECTRICAL CHARACTERISTICS DIF 0.7 V LW PWER DIFFERENTIAL UTPUTS (T A =0 C 70 C; Supply Voltage V DD /V DDA = 3.3 V ±5%, V DDI =.05 V to 3.3 V ±5%. See Test Loads for Loading Conditions) (Note 2) Symbol Parameter Conditions Min Typ Max Unit dv/dt Slew Rate (Notes 3, 4) Scope averaging on 4 V/ns dv/dt Slew Rate Matching (Notes 3, 5) Slew rate matching, Scope averaging on 20 % V High Voltage High Statistical measurement on single-ended mv signal using oscilloscope math function. V Low Voltage Low (Scope averaging on) V max Max Voltage Measurement on single ended signal using V min Min Voltage Absolute value. (Scope averaging off) mv V swing Vswing (Note 3) Scope averaging off 300 mv V cross_abs Crossing Voltage (abs) (Note 6) Scope averaging off mv V cross Crossing Voltage (var) (Note 7) Scope averaging off 40 mv Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2.Guaranteed by design and characterization, not tested in production. C L = 2 pf with R S = 33 for Zo = 50 (00 differential trace impedance). 3.Measured from differential waveform 4.Slew rate is measured through the V swing voltage range centered around differential 0 V. This results in a ±50 mv window around differential 0 V. 5. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mv window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 6.V cross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 7.The total variation of all V cross measurements in any particular system. Note that this is a subset of V cross_min/max (V cross absolute) allowed. The intent is to limit V cross induced modulation by setting V cross to be smaller than V cross absolute. 8

9 Table 2. ELECTRICAL CHARACTERISTICS CURRENT CNSUMPTIN (T A =0 C 70 C; Supply Voltage V DD /V DDA = 3.3 V ±5%, V DDI =.05 V to 3.3 V ±5%. See Test Loads for Loading Conditions) (Note 8) Symbol Parameter Conditions Min Typ Max Unit I DDVDD perating Supply Current All MHz, C L = 2 pf; Zo = ma I DDVDDA/R All MHz, C L = 2 pf; Zo = ma I DDVDDI All MHz, C L = 2 pf; Zo = ma I DDVDDPD Powerdown Current (Note 9) All differential pairs low/low 4 ma I DDVDDA/RPD All differential pairs low/low 5 ma I DDVDDIPD All differential pairs low/low 0.2 ma Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. Guaranteed by design and characterization, not tested in production. 9. With input clock running. Stopping the input clock will result in lower numbers. Table 3. ELECTRICAL CHARACTERISTICS SKEW AND DIFFERENTIAL JITTER PARAMETERS (T A =0 C 70 C; Supply Voltage V DD /V DDA = 3.3 V ±5%, V DDI =.05 to 3.3 V ±5%. See Test Loads for Loading Conditions) Symbol Parameter Conditions Min Typ Max Unit t SP_PLL CLK_IN, DIF[x:0] Input-to-utput Skew in PLL mode nominal ps (Notes 20, 2, 23, 24 and 27) 25 C, 3.3 V t PD_BYP t DSP_PLL t DSP_BYP t DTE t DSSTE t SKEW_ALL j peak-hibw j peak-lobw CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) CLK_IN, DIF[x:0] (Notes 20, 2, 22, 24 and 27) DIF[x:0] (Notes 20, 2, 22 and 27) PLL Jitter Peaking (Notes 26 and 27) PLL Jitter Peaking (Notes 26 and 27) Input-to-utput Skew in Bypass mode nominal 25 C, 3.3 V Input-to-utput Skew Variation in PLL mode across voltage and temperature Input-to-utput Skew Variation in Bypass mode across voltage and temperature Random Differential Tracking error between two NB3W900L devices in Hi BW Mode Random Differential Spread Spectrum Tracking error between two NB3W900L devices in Hi BW Mode. utput-to-utput Skew across all outputs (Common to Bypass and PLL mode) ns 00 ps ps 5 ps (rms) 75 ps 85 ps HBW_BYP_LBW# = db HBW_BYP_LBW# = db pll HIBW PLL Bandwidth (Notes 27 and 28) HBW_BYP_LBW# = 2 4 MHz pll LBW PLL Bandwidth (Notes 27 and 28) HBW_BYP_LBW# = MHz t DC Duty Cycle (Note 20) Measured differentially, PLL Mode % t DCD t jcyc-cyc Duty Cycle Distortion (Notes 20 and 29) Jitter, Cycle-to-Cycle (Notes 20 and 30) Measured differentially, Bypass MHz % PLL mode 50 ps Additive Jitter in Bypass Mode 50 ps Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 20.Measured into fixed 2 pf load cap. Input to output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. 22. All Bypass Mode Input-to-utput specs refer to the timing between an input edge and the specific output edge created by it. 23. This parameter is deterministic for a given device 24. Measured with scope averaging on to find mean value. 25.t is the period of the input clock 26. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 27. Guaranteed by design and characterization, not tested in production. 28.Measured at 3 db down or half power point. 29.Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 30. Measured from differential waveform 9

10 Table 4. ELECTRICAL CHARACTERISTICS PHASE JITTER PARAMETERS (T A =0 C 70 C; Supply Voltage V DD /V DDA = 3.3 V ±5%, V DDI =.05 V to 3.3 V ±5%. See Test Loads for Loading Conditions) (Note 3) Symbol Parameter Conditions Min Typ Max Unit t jphpcieg Phase Jitter, PLL Mode PCIe Gen (Notes 32 and 33) 86 ps (p p) t jphpcieg2 PCIe Gen 2 Lo Band 0 khz < f <.5 MHz (Note 32) 3 ps (rms) PCIe Gen 2 High Band.5 MHz < f < Nyquist (50 MHz) (Note 32) t jphpcieg3 PCIe Gen 3 (PLL BW of 2 4 MHz, CDR = 0 MHz) (Notes 32, 33 and 34) 3. ps (rms) ps (rms) t jphqpi_smi QPI & SMI (00.00 MHz or MHz, 4.8 Gb/s, 6.4 Gb/s 2UI) (Note 35) 0.5 ps (rms) t jphpcieg t jphpcieg2 Additive Phase Jitter, Bypass Mode QPI & SMI (00.00 MHz, 8.0 Gb/s, 2UI) (Note 35) 0.3 ps (rms) QPI & SMI (00.00 MHz, 9.6 Gb/s, 2UI) (Note 35) 0.2 ps (rms) PCIe Gen (Notes 32 and 33) 0 ps (p p) PCIe Gen 2 Lo Band 0 khz < f <.5 MHz (Notes 32 and 36) 0.3 ps (rms) PCIe Gen 2 High Band.5 MHz < f < Nyquist (50 MHz) (Notes 32 and 36) t jphpcieg3 PCIe Gen 3 (PLL BW of 2 4 MHz, CDR = 0 MHz) (Notes 32, 34 and 36) 0.7 ps (rms) 0.3 ps (rms) t jphqpi_smi QPI & SMI (00.00 MHz or MHz, 4.8 Gb/s, 6.4 Gb/s 2UI) (Notes 35 and 36) QPI & SMI (00.00 MHz, 8.0 Gb/s, 2UI) (Notes 35 and 36) QPI & SMI (00.00 MHz, 9.6 Gb/s, 2UI) (Notes 35 and 36) 0.3 ps (rms) 0. ps (rms) 0. ps (rms) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Applies to all outputs. 32. See for complete specs 33.Sample size of at least 00k cycles. This figures extrapolates to 08 ps M cycles for a BER of Subject to final ratification by PCI SIG. 35. Calculated from Intel-supplied Clock Jitter Tool v For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter) 2 = (total jittter) 2 (input jitter) 2 0

11 Table 5. CLCK PERIDS-DIFFERENTIAL UTPUTS WITH SPREAD SPECTRUM DISABLED SSC FF Center Freq. MHz Measurement Window Clock s 0. s 0.s 0.s s Clock c 2c jitter AbsPer Min SSC Short Term Average Min ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long Term Average Max +SSC Short Term Average Max +c2c jitter Abs Per Max DIF ns 37, 38, ns 37, 38, Guaranteed by design and characterization, not tested in production. 38.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK40B+ accuracy requirements (±00 ppm). The NB3W900L it self does not contribute to ppm error. 39.Driven by SRC out put of main clock, MHz PLL Mode or Bypass mode. 40.Driven by CPU out put of main clock, MHz PLL Mode or Bypass mode. Unit Notes Table 6. CLCK PERIDS-DIFFERENTIAL UTPUTS WITH SPREAD SPECTRUM ENABLED SSC N Center Freq. MHz Measurement Window Clock s 0.s 0.s 0.s s Clock c2c jitter AbsPer Min SSC Short Term Average Min ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long Term Average Max +SSC Short Term Average Max +c2c jitter AbsPer Max DIF ns 4, 42, 43 Unit Notes ns 4, 42, Guaranteed by design and characterization, not tested in production. 42.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/ CK40B+ accuracy requirements (±00 ppm). The NB3W900L it self does not contribute to ppm error. 43.Driven by SRC out put of main clock, MHz PLL Mode or Bypass mode. 44.Driven by CPU out put of main clock, MHz PLL Mode or Bypass mode. TEST LADS Rs Differential Zo, 0 inches 2pF 2pF Rs LP HCSL Differential utput Figure 3. NB3W900L Differential Test Loads Table 7. DIFFERENTIAL UTPUT TERMINATINS DIF Zo ( ) Rs ( )

12 GENERAL SMBus SERIAL INTERFACE INFRMATIN How to Write Controller (host) sends a start bit Controller (host) sends the write address Clock (device) will acknowledge Controller (host) sends the beginning byte location = N Clock (device) will acknowledge Controller (host) sends the byte count = X Clock (device) will acknowledge Controller (host) starts sending Byte N through Byte N+X Clock (device) will acknowledge each byte one at a time Controller (host) sends a Stop bit Table 8. INDEX BLCK WRITE PERATIN T WR Controller (Host) start bit Slave Address WRite Beginning Byte = N Data Byte Count = X Beginning Byte N X Byte Clock (Device) Controller (host) sends the beginning byte location = N Clock (device) will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Clock (device) will acknowledge Clock (device) will send the data byte count = X Clock (device) sends Byte N + X Clock (device) sends Byte 0 through Byte X (if X (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Table 9. INDEX BLCK READ PERATIN Controller (Host) T WR start bit Slave Address WRite Beginning Byte = N RT RD Repeat start Slave Address ReaD Clock (Device) X Byte Data Byte Count = X Beginning Byte N P Byte N + X stop bit How to Read Controller (host) will send a start bit Controller (host) sends the write address Clock (device) will acknowledge N P Not acknowledge stop bit Byte N + X 2

13 Table 20. SMBus ADDRESSING SA_ and SA_0 SMBus 8-bit Address (Rd/Wrt bit = 0) 00 D8 0M DA 0 DE M0 C2 MM C4 M C6 0 CA M CC CE Table 2. SMBus Table: PLL MDE, AND FREQUENCY SELECT REGISTER Byte 0 Pin # Name Control Function Type 0 Default Bit 7 4 PLL Mode PLL perating Mode Rd back R See PLL perating Mode Latch Bit 6 4 PLL Mode 0 PLL perating Mode Rd back 0 R Readback Table Latch Bit 5 72/7 DIF_8_En utput Control overrides E# pin RW Low/Low Enable Bit 4 68/67 DIF_7_En utput Control overrides E# pin RW Low/Low Enable Bit 3 66/65 DIF_6_En utput Control overrides E# pin RW Low/Low Enable Bit 2 Reserved 0 Bit Reserved 0 Bit M_33M# Frequency Select Readback R 33 MHz 00 MHz Latch Table 22. SMBus TABLE: UTPUT CNTRL REGISTER Byte Pin # Name Control Function Type 0 Default Bit 7 38/37 DIF_7_En utput Control overrides E# pin RW Bit 6 35/36 DIF_6_En utput Control overrides E# pin RW Bit 5 3/32 DIF_5_En utput Control overrides E# pin RW Bit 4 29/30 DIF_4_En utput Control overrides E# pin RW Bit 3 25/26 DIF_3_En utput Control overrides E# pin RW Low/Low Enable Bit 2 23/24 DIF_2_En utput Control overrides E# pin RW Bit 9/20 DIF En utput Control overrides E# pin RW Bit 0 7/8 DIF_0_En utput Control overrides E# pin RW Table 23. SMBus TABLE: UTPUT CNTRL REGISTER Byte 2 Pin # Name Control Function Type 0 Default Bit 7 62/6 DIF_5_En utput Control overrides E# pin RW Bit 6 60/59 DIF_4_En utput Control overrides E# pin RW Bit 5 56/55 DIF_3_En utput Control overrides E# pin RW Bit 4 54/53 DIF_2_En utput Control overrides E# pin RW Bit 3 50/49 DIF En utput Control overrides E# pin RW Low/Low Enable Bit 2 48/47 DIF_0_En utput Control overrides E# pin RW Bit 44/43 DIF_9_En utput Control overrides E# pin RW Bit 0 42/4 DIF_8_En utput Control overrides E# pin RW 3

14 Table 24. SMBus TABLE: RESERVED REGISTER Byte 3 Pin # Name Control Function Type 0 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit Reserved 0 Bit 0 Reserved 0 Table 25. SMBus TABLE: RESERVED REGISTER Byte 4 Pin # Name Control Function Type 0 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit Reserved 0 Bit 0 Reserved 0 Table 26. SMBus TABLE: VENDR & REVISIN ID REGISTER Byte 5 Pin # Name Control Function Type 0 Default Bit 7 RID3 R X Bit 6 RID2 REVISIN ID R X Bit 5 RID R X Bit 4 RID0 R X Bit 3 VID3 R Bit 2 VID2 VENDR ID R Bit VID R Bit 0 VID0 R Table 27. SMBus TABLE: DEVICE ID Byte 6 Pin # Name Control Function Type 0 Default Bit 7 Device ID 7 (MSB) R Bit 6 Device ID 6 R Bit 5 Device ID 5 R 0 Bit 4 Device ID 4 R Device ID is 30 decimal or Bit 3 Device ID 3 R 82 hex. Bit 2 Device ID 2 R 0 Bit Device ID R Bit 0 Device ID 0 R 4

15 Table 28. SMBus TABLE: BYTE CUNT REGISTER Byte 7 Pin # Name Control Function Type 0 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW Default value is 8 hex, so 9 Bit 2 BC2 Writing to this register configures how RW bytes (0 to 8) will be read 0 many bytes will be read back. back by default. Bit BC RW 0 Bit 0 BC0 RW 0 Table 29. SMBus TABLE: RESERVED REGISTER Byte 8 Pin # Name Control Function Type 0 Default Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit Reserved 0 Bit 0 Reserved 0 Table 30. DIF REFERENCE CLCK Common R Recommendations for Differential Routing Dimension or Value Unit L length, route as non-coupled 50 trace (see Figure 4) 0.5 max inch L2 length, route as non-coupled 50 trace (see Figure 4) 0.2 max inch L3 length, route as non-coupled 50 trace (see Figure 4) 0.2 max inch Rs (00 differential traces) (see Figure 4) 33 Rs (85 differential traces) (see Figure 4) 27 Down Device Differential Routing L4 length, route as coupled micro strip 00 differential trace (see Figure 4) 2 min to 6 max inch L4 length, route as coupled strip line 00 differential trace (see Figure 4).8 min to 4.4 max inch Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 00 differential trace (see Figure 5) 0.25 to 4 max inch L4 length, route as coupled stripline 00 differential trace (see Figure 5) min to 2.6 max inch 5

16 L L2 Rs L4 L4 L L2 Rs LP HCSL Differential utput PCI Express Down Device REF_CLK Input Figure 4. Down Device Routing L L2 Rs L4 L4 L L2 LP HCSL Differential utput Rs Figure 5. PCI Express Connector Routing PCI Express Add in Board REF_CLK Input Table 3. CABLE CNNECTED AC CUPLED APPLICATIN (Figure 6) Component Value Note R5a, R5b 8.2k 5% R6a, R6b k 5% Cc Vcm 0. F V 3.3 Volts Cc R5a R5b L4 Cc L4 R6a R6b Figure 6. 6

17 PWER FILTERING EXAMPLE Ferrite Bead Power Filtering Recommended ferrite bead filtering equivalent to the following: 600 Q impedance at MHz, 0. Q DCR max., 400 ma current rating. V3P3 FB R FERRITE 2.2 C9 F VDDA C7 0. F Place at pin VDD for PLL R2 2.2 C0 F VDDR C8 0. F VDD for Input Receiver C5 0. F F C5 VDD_DIF 0. F VDDI C 0 F C2 0. F C4 0. F C3 0. F C5 0. F C5 0. F Figure 7. Schematic Example of the NB3W900L Power Filtering Table 32. RDERING INFRMATIN NB3W900LMNG NB3W900LMNTXG Device Package Shipping QFN 72 (Pb Free) QFN 72 (Pb Free) 68 Units / Tray,000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 7

18 PAGE DIMENSINS QFN72 0x0, 0.5P CASE 485DK ISSUE PIN NE LCATIN NTE C 0.5 C 0.0 C 0.08 C DETAIL A ÉÉÉ 9 D TP VIEW DETAIL B SIDE VIEW D2 36 (A3) A A B E 72X L A 0.0 M C A B L C SEATING PLANE EXPSED Cu 0.0 M C A B L DETAIL A ALTERNATE CNSTRUCTINS ÉÉ MLD CMPD DETAIL B ALTERNATE CNSTRUCTIN L NTES:. DIMENSINING AND TLERANCING PER ASME Y4.5M, CNTRLLING DIMENSINS: MILLIMETERS. 3. DIMENSIN b APPLIES T PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.25mm FRM THE TERMINAL TIP. 4. CPLANARITY APPLIES T THE EXPSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b D 0.00 BSC D E 0.00 BSC E e 0.50 BSC L L RECMMENDED SLDERING FTPRINT X 0.63 E e BTTM VIEW 55 72X b 0.0 M C A B 0.05 M C NTE 3 PKG UTLINE 0.50 PITCH 72X 0.32 DIMENSINS: MILLIMETERS Intel is a registered trademark of Intel Corporation. PCIe and PCI SIG are registered trademarks of PCI SIG. N Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal pportunity/affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATIN RDERING INFRMATIN LITERATURE FULFILLMENT: Literature Distribution Center for N Semiconductor P.. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: N Semiconductor Website: rder Literature: For additional information, please contact your local Sales Representative NB3W900L/D