LM75. PIN CONFIGURATION (Top View) ORDERING INFORMATION

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1 The is a serially programmable temperature sensor that notifies the host controller when ambient temperature exceeds a user programmed setpoint. Hysteresis is also programmable. The INT/CMPTR output is programmable as either a simple comparator for thermostat operation or as a temperature event interrupt. Communication with the is accomplished via a two wire bus that is compatible with industry standard protocols. This permits reading the current temperature, programming the setpoint and hysteresis, and configuring the device. The powers up in Comparator Mode with a default setpoint of 80 C with 5 C hysteresis. Defaults allow independent operation as a stand alone thermostat. A shutdown command may be sent via the 2 wire bus to activate the low power stand mode. Address selection inputs allow up to eight s to share the same 2 wire bus for multi zone monitoring. All registers can be read the host and the INT/CMPTR output s polarity is user programmable. Both polled and interrupt driven systems are easily accommodated. Small physical size, low installed cost, and ease of use make the an ideal choice for implementing sophisticated system management schemes. Features Temperature Sensing: 0.5 C Accuracy (Typ.) Operates from: 55 C to +125 C Operating Range: 2.7 V 5.5 V Programmable Trip Point and Hysteresis with Power up Defaults Standard 2 Wire Serial Interface Thermal Event Alarm Output Functions as Interrupt or Comparator / Thermostat Output Up to 8 s May Share the Same Bus Shutdown Mode for Low Stand Power Consumption 5.0 V Tolerant I/O at V DD = 3.0 V Low Power 250 µa (Typ.) Operating, 1.0 µa (Typ.) Shutdown Mode Typical Applications Thermal Protection for High Performance CPUs Solid State Thermometer Fire/Heat Alarms Thermal Management in Electronic Systems: Computers Telecom Racks Power Supplies / UPS Copiers / Office Electronics Consumer Electronics / Amplifiers Process Control SDA 1 SCL 2 INT/CMPTR 3 GND 4 Micro8 DM SUFFIX CASE TBD PIN CONFIGURATION (Top View) 8 V DD 7 A0 6 A1 5 A2 ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 10 of this data sheet. Semiconductor Components Industries, LLC, 2000 September, 2000 Rev. 1 1 Publication Order Number: /D

2 FUNCTIONAL BLOCK DIAGRAM V DD Temp Sensor 9 Bit A/D Converter Control Logic INT/ CMPTR Register Set Configuration Temperature SDA SCL A 0 A 1 A 2 Two Wire Serial Port Interface TIMING DIAGRAM t SC SCL t H (START) t SU (STOP) SDA Data In t DSU SDA Data Out t DH PIN DESCRIPTION Pin No. Symbol Description ÁÁÁÁ 1 ÁÁÁÁÁÁ SDA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bidirectional Serial Data ÁÁÁÁ 2 ÁÁÁÁÁÁ SCL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Serial Data Clock Input ÁÁÁÁ 3 ÁÁÁÁÁÁ INT/CMPTR ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt or Comparator Output ÁÁÁÁ 4 ÁÁÁÁÁÁ GND ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System Ground ÁÁÁÁ 5 ÁÁÁÁÁÁ A 2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Select Pin (MSB) ÁÁÁÁ 6 ÁÁÁÁÁÁ A 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Select Pin ÁÁÁÁ 7 ÁÁÁÁÁÁ A 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Address Select Pin (LSB) ÁÁÁÁ 8 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Supply Input V DD 2

3 ABSOLUTE MAXIMUM RATINGS* Parameter Value Unit Supply Voltage (V DD ) 6.0 V ESD Susceptibility (Note 3.) 1000 V Input Voltage, On Pins: A0, A1, A2 SDA, SCL, INT/CMPTR (GND 0.3) to (V CC + 0.3) (GND 0.3) to 5.5 Operating Temperature Range (T J ) 55 to +125 C Storage Temperature Range (T STG ) 65 to +150 C Lead Temperature Range (Soldering, 10 sec) +300 C Thermal Resistance (Junction to Ambient) 250 C/W * Maximum Ratings are those values beyond which damage to the device may occur. ELECTRICAL CHARACTERISTICS (Specifications Measured Over Operating Temperature Range, V DD = V, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Power Supply Power Supply Voltage V DD V Operating Current Serial Port Inactive (T A = T J = 25 C) Serial Port Active I DD V ma Stand Supply Current Shutdown Mode, Serial Port Inactive (T A = T J = 25 C) INT/CMPTR Output I DD1 1 µa Sink Current: INT/CMPTR, SDA Outputs (Note 1.) I OL 1 4 ma INT/CMPTR Response Time User Programmable t TRIP 1 6 t CONV Output Low Voltage I OL = 4.0 ma Temp to Bits Converter V OL 0.8 V Temperature Accuracy (Note 2.) V DD = 3.3 V: DM 33R2 V DD = 5.0 V: DM 50R2 55 C TA +125 C 25 C TA 100 C T ±3 ±0.5 ±3 C C Conversion Time t CONV 55 msec TEMP Default Value Power Up T HYST Default Value Power Up T SET(PU) 80 C T HYST(PU) 75 C 1. Output current should be minimized for best temperature accuracy. Power dissipation within the will cause self heating and temperature drift. 2. All part types of the will operate properly over the wider power supply range of 2.7 V to 5.5 V. Each part type is tested and specified for rated accuracy at its nominal supply voltage. As V DD varies from the nominal value, accuracy will degrade 1 C/V of V DD change. 3. Human body model, 100 pf discharged through a 1.5 k resistor. 3

4 Characteristic Symbol Min Typ Max Unit 2 Wire Serial Bus Interface Logic Input High V IH V DD x 0.7 V Logic Input Low V IL V DD x 0.3 V Logic Output Low V OL V I OL = 3 ma 0.4 Input Capacitance SDA, SCL C IN 15 pf I/O Leakage (T A = T J = 25 C) I LEAK ±100 pa SDA Output Low Current I OL(SDA) 6 ma SERIAL PORT TIMING: C L = 80 pf, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Serial Port Frequency f SC khz Low Clock Period t LOW 1250 nsec High Clock Period t HIGH 1250 nsec SCL and SDA Rise Time t R 250 nsec SCL and SDA Fall Time t F 250 nsec Condition Setup Time (for repeated Condition) t SU(START) 1250 nsec SCL Clock Period t SC 2.5 µsec Condition Hold Time t H(START) 100 nsec Data in Setup Time to SCL High t DSU 100 nsec Data in Hold Time after SCL Low t DH 0 nsec Condition Setup Time t SU(STOP) 100 nsec Bus Free Time Prior to New Transition t IDLE 1250 nsec 4

5 DETAILED OPERATING DESCRIPTION A typical hardware connection is shown in Figure 1. A Address 0 (Set as Desired) A 1 A 2 Two Wire Interface SDA SCL Serial Data (SDA) V DD 4 C Bypass Figure 1. Typical Application 3 INT/CMPTR Bidirectional. Serial data is transferred in both directions using this pin. Serial Clock (SCL) Input. Clocks data into and out of the. INT/CMPTR Open Collector, Programmable Polarity. In Comparator Mode, unconditionally driven active any time temperature exceeds the value programmed into the T SET register. INT/CMPTR will become inactive when temperature subsequently falls below the T HYST setting. (See Register Set and Programmer s Model.) In Interrupt Mode, INT/CMPTR is made active TEMP exceeding T SET ; it is unconditionally reset to its inactive state reading any register via the 2 wire bus. If and when temperature falls below T HYST, INT/CMPTR is again driven active. Reading any register will clear the T HYST interrupt. In Interrupt Mode, the INT/CMPTR output is unconditionally reset upon entering Shutdown Mode. If programmed as an active low output, it can be wire ORed with any number of other open collector devices. Most systems will require a pull up resistor for this configuration. Note that current sourced from the pull up resistor causes power dissipation and may cause internal heating of the. To avoid affecting the accuracy of ambient temperature readings, the pull up resistor should be made as large as possible. INT/CMPTR s output polarity may be programmed writing to the INT/CMPTR POLARITY bit in the CONFIG register. The default is active low. Address (A2, A1, A0) Inputs. Sets the three least significant bits of the 8 bit address. A match between the s address and the address specified in the serial bit stream must be made to initiate communication with the. Many protocol compatible devices with other addresses may share the same 2 wire bus. Slave Address The four most significant bits of the (A6, A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the to respond with an nowledge (indicating the is on the bus and ready to accept data). The Slave Address is represented : Slave Address A2 A1 A0 MSB LSB Comparator/Interrupt Modes INT/CMPTR behaves differently depending on whether the is in Comparator Mode or Interrupt Mode. Comparator Mode is designed for simple thermostatic operation. INT/CMPTR will go active anytime TEMP exceeds T SET. When in Comparator Mode, INT/CMPTR will remain active until TEMP falls below T HYST, whereupon it will reset to its inactive state. The state of INT/CMPTR is maintained in shutdown mode when the is in comparator mode. In Interrupt Mode, INT/CMPTR will remain active indefinitely, even if TEMP falls below T HYST, until any register is read via the 2 wire bus. Interrupt Mode is better suited to interrupt driven microprocessor based systems. The INT/CMPTR output may be wire OR ed with other interrupt sources in such systems. Note that a pull up resistor is necessary on this pin since it is an open drain output. Entering Shutdown Mode will unconditionally reset INT/CMPTR when in Interrupt Mode. SHUTDOWN MODE When the appropriate bit is set in the configuration register (CONFIG) the enters its low power shutdown mode (I DD = 1.0 µa, typical) and the temperature to digital conversion process is halted. The s bus interface remains active and TEMP, T SET, and T HYST may be read from and written to. Transitions on SDA or SCL due to external bus activity may increase the stand power consumption. If the is in Interrupt Mode, the state of INT/CMPTR will be RESET upon entering shutdown mode. Fault Queue To lessen the probability of spurious activation of INT/CMPTR the may be programmed to filter out transient events. This is done programming the desired value into the Fault Queue. Logic inside the will prevent the device from triggering INT/CMPTR unless the programmed number of sequential temperature to digital conversions yield the same qualitative result. In other words, the value reported in TEMP must remain above T SET or below T HYST for the consecutive number of cycles 5

6 programmed in the Fault Queue. Up to a six cycle filter may be selected. See Register Set and Programmer s Model. Serial Port Operation The Serial Clock input (SCL) and bidirectional data port (SDA) form a 2 wire bidirectional serial port for programming and interrogating the. The following conventions are used in this bus scheme: Serial Bus Conventions Term Transmitter Receiver Slave ACK NOT Busy Data Valid Explanation The device sending data to the bus. The device receiving data from the bus. The device which controls the bus: initiating transfers (START), generating the clock, and terminating transfers (STOP). The device addressed the master. A unique condition signaling the beginning of a transfer indicated SDA falling (High Low) while SCL is high. A unique condition signaling the end of a transfer indicated SDA rising (Low High) while SCL is high. A Receiver acknowledges the receipt of each te with this unique condition. The Receiver drives SDA low during SCL high of the ACK clock pulse. The provides the clock pulse for the ACK cycle. When the bus is idle, both SDA & SCL will remain high. The state of SDA must remain stable during the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See and conditions) All transfers take place under control of a host, usually a CPU or microcontroller, acting as the, which provides the clock signal for all transfers. The always operates as a Slave. This serial protocol is illustrated in Figure 2. All data transfers have two phases; and all tes are transferred MSB first. Accesses are initiated a start condition (START), followed a device address te and one or more data tes. The device address te includes a Read/Write selection bit. Each access must be terminated a Condition (STOP). A convention called nowledge (ACK) confirms receipt of each te. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for and Conditions). Condition (START) The continuously monitors the SDA and SCL lines for a start condition (a HIGH to LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met. (See Timing Diagram) Immediately following the Condition, the host must next transmit the address te to the. The four most significant bits of the (A6, A5, A4, A3) are fixed to 1001(B). The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the to respond with an nowledge (indicating the is on the bus and ready to accept data). The eighth bit in the is a Read Write Bit. This bit is a 1 for a read operation or 0 for a write operation. nowledge (ACK) nowledge (ACK) provides a positive handshake between the host and the. The host releases SDA after transmitting eight bits then generates a ninth clock cycle to allow the to pull the SDA line LOW to acknowledge that it successfully received the previous eight bits of data or address. Data Byte After a successful ACK of the address te, the host must next transmit the data te to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data te into the. Condition (STOP) Communications must be terminated a stop condition (a LOW to HIGH transition of SDA while SCL is HIGH). The Condition must be communicated the transmitter to the. (See Timing Diagram) Power Supply To minimize temperature measurement error, the DM 33 is factory calibrated at a supply voltage of 3.3 V ±5% and the DM 50 is factory calibrated at a supply voltage of 5.0 V ±5%. Either device is fully operational over the power supply voltage range of 2.7 V to 5.5 V, but with a lower measurement accuracy. The typical value of this power supply related error is ±2 C. 6

7 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Most Significant Data Byte Least Significant Data Byte (a) Typical 2 Byte Read From Preset Pointer Location Such as Temp, T OS, T HYST No Cond A2 A1 A0 R/W Pointer Byte 9 1 D1 D Repeat A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Most Significant Data Byte Least Significant Data Byte No Cond (b) Typical Pointer Set Followed Immediate Read for 2 Byte Register Such as Temp, T OS, T HYST A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 Data Byte No Cond (c) Typical 1 Byte Read From Configuration Register With Preset Pointer A2 A1 A0 R/W D0 1 0 Pointer Byte Repeat 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 (d) Typical Pointer Set Followed Immediate Read from Configuration Register Data Byte No Cond A2 A1 A0 R/W D1 D D4 D3 D2 D1 D0 (e) Configuration Register Write Pointer Byte Configuration Byte Cond A2 A1 A0 R/W (f) T OS and T HYST Write Pointer Byte D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Most Significant Data Byte Least Significant Data Byte Cond Figure 2. Serial Port Operation 7

8 REGISTER SET AND PROGRAMMER S MODEL Register (POINT), 8 bits, Write only Pointer Register (POINT) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Must Be Set To Zero Pointer Register Selection via the Pointer Register: D1 D0 Register Selection 0 0 TEMP 0 1 CONFIG 1 0 T HYST 1 1 T SET Configuration Register (CONFIG), 8 bits, Read/Write Configuration Register (CONFIG) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Must Be Set To Zero Fault Queue INT/ CMPTR. POLAR- ITY COMP/ INT. Shut Down D0: Shutdown: 0 = Normal Operation 1 = Shutdown Mode D1: CMPTR/INT: 0 = Comparator Mode 1 = Interrupt Mode D2: INT/CMPTR POLARITY: 0 = Active Low 1 = Active High D3 D4: Fault Queue: Number of sequential temperature to digital conversions with the same result before the INT/CMPTR output is updated: D4 D3 Number of Conversions (Power up default)

9 Temperature (TEMP) Register, 16 bits, Read only The binary value in this register represents ambient temperature following a conversion cycle. Temperature Register (TEMP) D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X Temperature Setpoint (T SET ) and Hysteresis (T HYST ) Register, 16 bits, Read Write: Temperature Setpoint Register (T SET ) D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X Hysteresis Register (T HYST ) D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X X X X In the TEMP, T SET, and T HYST registers, each unit value represents one half degree (Celsius). The value is in 2 s complement binary format such that a reading of b corresponds to 0 C. Examples of this temperature to binary value relationship are shown in the following table. Temperature to Digital Value Conversion Temperature Binary Value HEX Value +125 C FA +25 C C C C FF 25 C CE 40 C B0 55 C The s register set is summarized below Name Description Width Read Write Notes TEMP Ambient Temperature 16 X 2 s Complement Format T SET Temperature Setpoint 16 X X 2 s Complement Format T HYST Temperature Hysteresis 16 X X 2 s Complement Format POINT Register Pointer 8 X X CONFIG Configuration Register 8 X X 9

10 TAPE AND REEL INFORMATION Component Taping Orientation for Micro8 Devices USER DIRECTION OF FEED PIN 1 Standard Reel Component Orientation for R2 Suffix Device (Mark Right Side Up) Tape & Reel Specifications Table Package Tape Width (W) Pitch (P) Part Per Full Reel Diameter Micro 8 12 mm 4 mm inches ORDERING INFORMATION Device Supply Voltage (V DD ) Package Shipping DM 33R2 3.3 V Micro Tape/Reel DM 50R2 5.0 V Micro Tape/Reel MARKING DIAGRAMS DM 33 DM

11 PACKAGE DIMENSIONS Micro8 PLASTIC PACKAGE CASE TBD PIN (3.10).197 (5.00).114 (2.90).187 (4.80).026 (0.65) TYP..122 (3.10).114 (2.90).043 (1.10) MAX. 6 MAX..008 (0.20).005 (0.13).016 (0.40).010 (0.25).006 (0.15).002 (0.05).028 (0.70).016 (0.40) Dimensions: inches (mm) 11

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