COST PERFORMANCE ASPECTS OF CCD FAST AUXILIARY MEMORY

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1 COST PERFORMANCE ASPECTS OF CCD FAST AUXILIARY MEMORY Dileep P, Bhondarkor Texas Instruments Inorporated Dallas, Texas ABSTRACT Charge oupled devies (CCD's) hove been mentioned as potential fast auxiliary memories in multiprogrammed omputer systems with virtual memory. Delining MOS RAM osts will tend to allow omputer designers to put more random aess memory in their systems. However, due to program loality only a portion of the memory is atively used. If CCD's ost R (> 1) times less than RAM's, the size of the random aess main memory on be redued and a CCD paging store on be provided as a bak up. Ative program segments an now be brought into the RAM as and when needed. Often the question has been raised in industry as to what value of R is needed to justify this appliation of CCD's. A queueing network analysis is presented in this paper. The model developed is used to establish a riterion for ost-effetiveness. A relationship is derived between RAM/CCD ost ratio Rand the page exeption harateristis of the program environment. A rough rule of thumb is suggested. It states that ost-effetiveness is ahieved provided the page miss ratio is less than o, where o is the ratio of the proessor yle time to CCD blok read time. This riterion is applied to known miss ratio harateristis to obtain a ritial value of R ranging from 1.2 to 2.0 foro :::: and respetively. This indiates that a projeted ost ratio of two to four an make fast auxiliary CCD memories attrative for blok read times ranging from 200 to 500 miroseonds. INTRODUCTION Several memory tehnologies with diverse ostperformane harateristis have emerged as potential storage media in digital omputers. At the high performane end of the produt spetrum, ore memory, MOS and bipolar random-aessmemory provide a medium for ative program storage. Cheaper baking store is or soon will be available with magneti disks, harge oupled devies (CCD) eletron beam addressable memories (EBAM), and magneti bubble domain devies (MBD). Due to the signifiant prie and performane differene between primary and seondary memory tehnology, omputer designers have used multi-level storage hierarhies where the objetive is to keep the urrent information in the fastest devies and the rest of the information in 435

2 Table 1 Cost-Performane of Competing Tehnologies (Cira 1978} Aess Time Typial Serial Blok Tehnology to First Bit Size (Bits) MBD 0,5-1.5 ms Maximum Serial Parallelism of Cost/Bit Transfer Rate Data Transfer Path (~) khz ,1 CCD 0,1-l.Oms MHz up to 8 or MOS RAM 200 ns 1 2 MHz , EBAM 30 II' MHz FHD Slow 17 ms Med 8 ms Fast 4 ms MHz 1 0, MHz 1-2 0, MHz the slower and less exp~nsive devies. The individual ost and performane harateristis and the user environment (program behavior) wi II affet the optimal memory system design. This paper presents an overviewofthe ost-performane harateristis of some of the tehnologies and identifies the omputing environment best suited to them. Moving head disks (MHD) are generally too slow for ative program auxiliary storage. They are a seondary memory to store inative program segments or files. Fixed heod disks or head per trak drums have been used as fast auxiliary memory between primary and seondary memory. COMPETING TECHNOLOGIES The different tehnologies an be funtionally lassified into Random Aess and Blok Aess Memories. In RAM 1 s, eah bit of storage is indi- vidually aessible; in BAM 1 s, the smallest aessible unit is a serial stream of bits. Table 1 summarizes the typial ost-performane harateristis of memory systems using various tehnologies [ f. 1]. Some of the non-quantitative features of these tehnologies are disussed below. The traditional BAM market is served by magneti disks while ore memories are most ommonly used as RAM's. Magneti Bubble Memories Magneti Bubbles* provide non-volatile blok aess storage, ompeting diretly with fixed-head disks. If the projeted ost estimates are met, MBD's should virtually apture all the market for small apaity(< 10M bits}, low aess time FHD's. They also pose a serious threat to the medium per- *This paper is onerned only with large bubbles (511 in diameter), 436

3 formane FHD's beause they offer greatly improved performane at omparable pries. The market for large FHD's (>loom bits) with relatively slow aess times will not be signifiantly affeted as they have a prie advantage of a fator of two or three over MBD's. An important feature of MBD's is their modular expansibility. Users will be able to upgrade relatively easily the apaity of their storage to meet inreasing requirements. Their non-volatility gives them an edge over CCD's. However, in fast auxiliary memory appliations, volatility ould be tolerated due to the existene of bakup storage in the form of a moving head disk. Note that a three-level hierarhy is not neessary for MBD's and FHD's in small omputer systems. The.stopability and asynhronous operation of MBD's an be exploited in future omputer arhitetures. Charge Coupled Devies CCD memory has the best potential far very high speed operation. Most urrent omputers are not designed to handle fast peripheral devies, and novel arhitetural ideas are needed to exploit their high performane, Future super omputers (a Ia IBM 360/195, Texas Instruments ASC, and CDC 7600) ould take advantage of this tehnology. The best appliation area is in small apaity and/ or high performane storage. CCD's are easy to interfae and an be made modularly expandable. Their ost per bit will be approximately two to four times less than the prevailing MOS RAM ost [ 2]. In onjuntion with a RAM buffer, CCD's an be used to provide ost-effetive fast auxiliary memory in omputers where a large low-ost virtual address spae is desired at an aompanying small degradation in overall omputer speed. The pervasiveness of this market will depend strongly on the prie ratio of CCD's to RAM's. CCD's an also be used very effetively as an intermediate level storag~ between fast RAM's and slow, inexpensive moving-head disks. Fixed-Head Disks Fixed head disks an be broadly lassified into three ategories: low apaity/high performane, high apaity/low performane, and medium. The high performane disks usually provide multiple heads per trak to redue the aess time. Inrease in transfer rate an be ahieved by using more than one read/write head in parallel. The average FHD has only one head per trak and aesses a single trak at any given time by eletronially seleting a read/write head. The prie inrease assoiated with multiple heads per trak and parallel transfer is signifiant and restrits the apaity to less than 20 megabits. Advanes in integrated head assemblies ould drive the ost of FHD's down, These disks should eventually be displaed by a less expensive tehnology I ike magneti bubbles or high density MOS RAM's. The high apoity, low performane FHD's will be replaed by MBD's in appliations where higher performane at a omparable ost is needed. The modularity of MBD's will also affet the market, If the projeted 20 millient prie/bit is ahieved for MBD's, the medium FHD market will be seriously threatened. CCD's offer ompetition at the high performane end if volatility an be tolerated. 437

4 Eletron Beam Addressable Memories Eletron Beom Addressable Memories (EBAM) are a potential andidate for high apaity fast auxiliary memory. The storage medium is apable of retaining data for over a month in the absene of power. In order to ahieve a low ost/bit storage apaity has to be in the viinity of 100 million bits. This would restrit the appliability of this tehnology. to appliations requiring large apaity, low aess time and high data rates. Random Aess Memories Core is being slowly replaed by semiondutor random aess memory. Though MOS has little speed advantage over ore, delining osts of LSI memories will make MOS RAM pries omparable to ore pries. For this reason ore memories will not be onsidered in this paper. The single transistor per ell MOS RAM has the best potential for high density random aess main memory. Delining RAM osts will affet the market for the serial aess memories. As RAM osts go down omputer designers will tend to put more RAM in their systems, thereby reduing the need for fast, expensive serial aess memories. The total system ostperformane may well be better served by an inexpensive medium performane seondary storage. SYSTEM PERFORMANCE with a two-level hierarhy will be presented. Multiprogramming refers to allowing the entral proessor (CPU} to swith from task to task in order to ahieve good utilization of all resoures. Typially, a given task is allowed to exeute until it requires information from the bakup storage or any 1/0 peripheral. While information is being transferred from seondary storage to primary memory, the CPU performs a task swith and starts exeution of another task whih referenes only the primary memory. The degree of multiprogramming is the number of jobs, tasks or proesses atively using the main memory resoures of the omputer system. A disussion of the optimal degree of multiprogramming and its effet on system performane is beyond the sope of this study. As mentioned earlier, delining RAM osts will tend to inrease the size of main memory. However, due to program loality [ f. 3] only a portion of main memory is atively used. The availability of low ost paging devies may offer a ost-effetive alternative to the system designer. A smaller main memory an be used in onjuntion with a paging store or fast auxiliary memory (FAM} to ahieve the same performane as the ase in whih the entire program resides in main memory. Criteria for ost-effetiveness are explored in this setion. This setion desribes a methodology for evaluating the effet of various memory hierarhy alternatives on the overall system performane measured in terms of the instrution exeution rate. A simple model of a multi programmed omputer system Consider a multi programmed omputer system C. In this system the entire program is loaded into main memory from a peripheral devie like movinghead disk or tape unit. A program is exeuted until interrupted by the ourrene of an 1/0 438

5 I/0 QUEUE... QUEUE... CPU CPU Figure 1 Queueing model of a multiprogrammed omputer systern request to a peripheral devie or program termination. Figure 1 shows a queueing model of suh a system. This analysis assumes the servie times of the CPU and 1/0 servers to be distributed exponentially with mean 1/A and 1/~-t The CPU utilization, U where u M 1-p M+l 1 -p, is given by [ f, 4], respetively,* p = and M is the degree of multi-!' programming, M is assumed to be equal to 8 for this analysis, The average exeution interval is given by 1 -=I X A t u where t is the average time interval between suu essive memory aesses, and, I is the number of memory referenes between 1/0 requests. Figure 2 FAM Queueing model of a paged multiprogrammed omputer An alternate system design 1 C 1 1 that uses paging 1 an be modeled by the queueing network is shown in Figure 2, The ost per bit of main memory is R (> l ) times the ost per bit of the paging store or fast auxiliary memory. In this system exeution is terminated by an additional event alled page fault. The main memory in this system is smaller than the program size. Only a fration, f 1 of the program resides in main memory. A page fault ours when the program referenes a page not urrently in the resident set. Page faults ore haraterized by the probability of their ourrene-- sometimes also referred to as miss ratio, a The average number of memory referenes between page faults is (1-a)/a. The rate, 0 1 *This assumption ~s widely used in the analysis of the performane of omputer systems, It simplifies the mathematis involved while providing useful insight into the dynamis of the queueing.phenomena, at whih the CPU aesses the paging store is given by 6 - CY - l- 0' X -~- U 439

6 Thus, in Figure 2, ost ratio of the main memory to paging store is X ' A + 6 I 1 R* = 1-f* P 1 =Probability {Exeution terminated due to page fault} = B /x ' P 2 =Probability ( Exeution terminated for other 1/0 } = x/x' The servie rote, y, of the paging devie is equal to 1/T, where T is the sum of the lateny and transfer times. General expressions for the equilibrium distribution of jobs in suh networks have been obtained by Gordon and Newell [ 5] The use of these expressions gives the utilization, U',ofsystemC'as where U' M... L (x'-y') i=1 M+1.. L(x'-y') i=1 x =.1.. and y II ' y Note that this simplified analysis does not inlude the ost of implementing a memory management sheme for the paging ativity. Thus, the ost advantage has to be greater than that mentioned above in order to justify the added omplexity. The value of R* an be alulated from known miss ratio harateristis of program environments. The value of a* is a funtion of U, the utiliza tion of the unpaged system, and the produt y t u, denoted by a Figure 3 is a plot of U' against <> for a = and U varying from 0.5 to 0.9. Similar urves an be plotted for other values of a Based on these urves an approximate rule of thumb an be stated that the ritial miss ratio, a*, is almost equal to the value of a for less than 10% degradation in performane. The orresponding value of f* is a funtion of program behavior. Note that when a page fault ours it may be neessary to restore a urrently resident page into the paging devie before a new page is brought into main memory. In this analysis, suh a page fault will be onsidered equivalent to two page faults. Also, by definition, when a approahes zero the.8 u = 0.8 u = 0.7 M =8 (J = page fault rate 6 goes to zero. Let a* be the miss ratio for whih U' is within 5% of U Let the orresponding frational size of the resident set be f* ( < 1 ) Then, the system C 1 has the some ost as system C, if the per bit ~.2 u Miss Ratio Figure 3. Performane of a Paged System

7 Table 2. Critial Miss Ratio Table 3. Minimum Cost Ratio for Cost-Effetiveness Critial Miss Ratio a* u a =.005 a=,002 a =.001 u Minimum Cost Ratio R* a =.005 a =.002 a= , ,0020 0, , , , , CCD memories ore expeted to be between a fator of two to four times less expensive than equivalent MOS RAM's [ 2]. Let us assume that the memory management sheme is implemented in hardware at a ost of 10% of the original memory ost. If R is equal to 2 then ost-effetiveness is ahieved for environments where f* < 0.65 Table 2 shows the value of a* that must be ahieved at the above mentioned value off*. 2 ;i! 0.1 ~ ~.01 Program Size = 256K bytes Page Size = 1 K byte Size of Resident Buffer (K bytes) Figure 4. Mattson's Miss Ratio Charateristi For a given program environment this analysis an be used to predit the minimum ost ratio R* required for ost effetiveness. Figure 4 shows the miss ratio harateristis of Mattson [ 6]. Table 3 shows the minimum value of R for various system onfigurations. One again, a 10% ost is attributed to memory mapping; i.e., R*=l/(0.9-f*), Sine the ritial ost ratio ranges from 1.2 to 5.0, CCD's are likely to be attrative paging devies if the projeted ost ratios of two to four are ahieved for a> For typial values oft equal to 0.5 and 1 miroseond, this orresu ponds to a blok read time of 250 to 500 miroseonds. For CCD register lengths of 1 K bit this an be ahieved with data rates near 5 MHz Further performane improvements an be obtained by maintaining some of the frequently used files suh as system tables and diretories, ompilers, and utility programs in a fast aess devie suh a as CCD's. This redues the request frequeny to the file system whih is usually a moving-head disk with aess times ranging fro~ 30 to 100 milliseonds. Thus, theccd now ats as a buffer between the CPU and the file system, Table 4 shows the 441

8 Tobie 4 Performane Improvement due to Buffering of Systems Software q CPU Utilization " o.o , , , , q = Probability of finding system software in CCD buffer improvement in utilization due to the CCD buffer when the buffer satisfies a fration q of all requests to the file system. This improvement is insensitive to the aess time of the buffer provided it is at least a fator of 10 better. The two approahes outlined in this setion an be ombined to inrease the effetive size of the main memory. Any performane degradation due to paging an be ompensated by the improvement due to permanent residene of ertain systems software on the fast paging devie. CONCLUDING REMARKS The analysis presented in this paper makes many simplifying assumptions in order to derive some general results. There are many page alloation strategies for multiprogramming systems with virtual memory [ 7], These strategies are used effetively to obtain the most effiient use of system resoures [ 8], Some of the issues involved are optimal page size, optimal degree of multipro- gronuning, time sliing, dynami memory alloation, page replaement strategies, and sheduling. These problems on be analyzed for more speifi system arhitetures. A ost ratio of two to four for blok read times of 200 to 500 miroseonds is likely to result in lower memory system ost using a fast auxiliary memory. The amount saved depends on the size of the memory. The ultimate attrativeness of that ost saving depends on its magnitude relative to the overa II system ost, REFERENCES 1. R,R, Martin and H,D, Frankel: Eletroni Disks in the s, Computer, February 1975, PP J.E. Cornes ond W.F. Kosonoky: Charge Coupled Devies for Computer Memories, Proeedings AFIPS NCC, May 1974, Vol. 43-,- PP 833, 3. P,J, Denning: The Working Set Model for Program Behavior, CACM, Vol. 11, No, 5, May 1968, pp F.S. Hillier and G.J. Lieberman: Introdution to Operations Researh, Holden-Day, San Franiso, W.J. Gordon ond G.F. Newell: Closed Queueing Systems with Exponential Servers, Operations Researh, Vol, 15, No.2, April 1967, pp , 6, R.L. Mattson: Evaluation of Multilevel Memories, IEEE Transations on Magnetis, Vol. MAG-7, No, 4, Deember pp D. D. Chamberlin et al: An Analysis of Page Alloation for Multi programmed Systems with Virtual Memory 1 IBM Journal of Researh & Development 1 Yo I. 17, No, 5, September 1973, PP , 8. Y. Bard: Chara:;terization of Program Paging in a Time Shared Environment, IBM Journal of Researh & Development, Vol, 17, No, 5, September 1973, pp, , 442