This fact makes it difficult to evaluate the cost function to be minimized

Transcription

1 RSOURC LLOCTION N SSINMNT In the resoure alloation step the amount of resoures required to exeute the different types of proesses is determined. We will refer to the time interval during whih a proess is exeuted as the lifetime of the proess. Note that storing a value in memory is a (storage) proess. The amount of resoures an be minimized by letting proesses that do not overlap in time share resoures. The number and type of resoures an be determined from the operation shedule and orresponding lifetime table for the signal values. SP lgorithm Partitionig into o-operating proesses Sheduling Resoure lloation Resoure ssignment rhiteture esign Logi esign VLSI esign Clique Partitioning The resoure alloation problem an be solved by using different types of graphs to determine whether two proesses of the same type may, or may not, share a resoure. The onnetivity graph whih is also alled a ompatibility graph is obtained by onneting two verties with an edge if the lifetimes of the orresponding proesses do not overlap. This implies that the proesses may share a resoure. e d a b a b d e Shedule with five operations (proesses) Connetivity graph Usually, the largest number of onurrent proesses determines the number of resoures required. In fat, both the resoure alloation and assignment steps are usually simple one-to-one mappings where eah proess an be bounded to a free resoure. However, as shown in xample., more resoures than there are onurrent proesses are required in some ases. This fat makes it diffiult to evaluate the ost funtion to be minimized by the sheduling. In order to determine whih proesses an share resoures, we partition the onnetivity graph into a number of liques. lique is defined as a fully onneted subgraph that has an edge between all pairs of verties. Thus, the proesses orresponding to the verties in a lique may share the same resoure. Now, we hoose the liques so that they ompletely over the onnetivity graph i.e., so that every vertex belongs to one, and only one, lique. Hene, eah lique will orrespond to a set of proesses that may share a resoure and the number of liques used to over the onnetivity graph determines the number of resoures. a b a b P P P P d e d e P t.

2 RSOURC SSINMNT The resoure assignment step involves seletion of a partiular resoure from a pool of resoures to exeute a ertain proess. Ideally this assignment should be made at the same time as the sheduling, but this is not done in pratie. eause of the omplexity of the problem, it is instead divided into separate sheduling, alloation, and assignment steps. The problem of assigning a lass of proesses to a orresponding set of resoures an be formulated as a sheduling problem where proesses with ompatible lifetimes are assigned to the same resoure. xample. F C C F 9 Proesses 9 Sorted proesses The Left-dge lgorithm The left-edge algorithm is a heuristi list-sheduling method.. Sort the proesses into a list aording to their starting times. egin the list with the proess having the longest lifetime if the shedule is yli. Proesses with the same starting time are sorted with the longest lifetime first. Let i =.. ssign the first proess in the list to a free resoure i, determine its finishing time, and remove it from the list.. Searh the list for the first proess that has a) a starting time equal to, or later than, the finishing time for the previously assigned proess; and b) a finishing time that is no later than the starting time for the first proess seleted in step.. If the searh in step fails then if there are proesses left in the list then let i i + and repeat from step else Stop endif; assign the proess to resoure i, determine its finishing time, remove it from the list, and repeat from step. endif. F C R R R F R H C H 9 9 Resoure assignment Sorted proesses * No gain in this ase!

3 INTRPOLTOR, CONT. We will determine a suitable operation shedule, and perform resoure alloation and assignment, for the interpolator. We assume that the Ps have two pipeline stages. This means that the outputs of an adaptor an not be used diretly as inputs to an adjaent adaptor, sine the signal values are inside the pipeline. n operation an be exeuted in eah time slot, but the result will be first available after two time slots. Using the preedene relations we get the SP shedule. 9 9 T P CP 9 9 T Sample Stage Stage Stage Stage T Sample 9 In this ase it is enough to perform the sheduling over only one sample interval, sine the ritial loops ontain only one delay element. The exeution time for a bit-serial P is W d + lok yles, where W d is the data word length. The lateny is (W d + ) = time units, beause of the pipelining. We estimate that W d = bits are required and that the minimum lok frequeny for the Ps is at least MHz. The minimum number of Ps is W d + N a ( )N op f sample = = f CL We hoose to use four Ps to perform the adaptor operations. Hene, T sample = TP. Final Proessor ssignment P P P P 9 9 T Sample Skewed exeution of the Ps

4 Memory ssignment The onstraints on memory alloation and assignment an be derived from the P shedule. The memory P transations an be extrated from the P shedule and the preedene form. z z z z z z z z z z z z z z 9 9 z z z N N N N N N N N N 9 N N There are four transations (two inputs and outputs, eah requiring one read and one write operation) taking plae in eah T P time slot. The memory shedule will therefore be over = T M time slots, where T M is the time required for a memory read or a write operation. We have hosen to use two memories, sine the adaptors have two inputs and two outputs. We will use a modified version of the lique partitioning tehnique desribed above to assign the variables to the memories. Instead of drawing a line between proesses that may share resoures, we will draw a line between verties (memory variables) that an not be stored in the same memory or are aessed at the same time instanes. The reason for this is that the number of branhes in the graph otherwise beomes unmanageably large. The resulting graph is alled an exlusion graph. a a a b a b b a b b a b 9a 9b a b a b a b a b a b a b y(m+) a b a b a b a b 9a 9b y(m+) a b a b a b y(m) a b y(m+) memory write memory read negate the value b a a b b a a b b a a b b a b a b a b a 9b 9a b a b a b a b a 9b 9a b a b a b a b a b a b a This graph must now be partitioned into two liques (two memories) by drawing a line that separates all onneted verties. This proedure separates variables that must be stored in different memories.

5 b a a b b a a b b a a b b a b a b a b a 9b 9a b a b a b a b a 9b 9a b a b a b a b a b a b a Memory Cell lloation and ssignment b a a 9a b a a a a a a b a a 9a a a a b a a 9a a a a a 9a a a b a a a b a a memory write memory read negate the value