User Guide for the Pericom PI7C8150 Reference board By Glenn Sanders

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1 Introduction The Pericom PI7C80 PCI-to-PCI bridge evaluation board demonstrates the bridge and allows testing of key features either before or during design / layout stages. The PI7C80 PCI bridge complies with PCI Local Bus specification 2.2, as well as PCI bridge specification.. User Guide for the Pericom PI7C80 Reference board By Glenn Sanders Signal bpcce Application Note Notes "off" Enables bus/power clock control function (BPCCE is high) * 2 cfg "" selects Bridge is MHz capable p_men s_men * reserved * arbctrl 7 Not used Reference board can be used in either or MHz motherboard slot. "" sets Secondary bus is MHz capable (S_MEN is high) Reserved, this switch must be "on" "" Internal arbiter is selected No effect in either position ) standard and one straddle mount PCI connector. 2) Pin on the golden PCI edge connector faces left when looking down on the component (bridge IC). ) Secondary bus Vio select :.V or V ) Headers for sampling signals on the primary PCI bus ) GNT# and REQ# selection jumpers for the first slots ) Auxiliary power connector 7) External arbiter socket 8) Switches to set bus speed, control clocks, and some miscfunctions Photo of 80 reference board This board comes already configured to support: a) Primary PCI voltage (p_vio) can be either.v or V keying. b) Secondary PCI voltage is set to.v at J2 c) or MHz primary (ie MEN is high) d) MHz secondary if all cards on the secondary bus are MHz capable (ie secondary bus MEN is high) e) internal arbiter and internal clock source are enabled no need to connect external power in most applications; the host PCI bus generally can power all secondary bus slots.

2 and (*) important switch settings at a glance: ) SW there is no SW 2) SW pin must be set to ON (turns on secondary bus feedback clock signal). ) Normally - are off. These turn off unused secondary bus clocks. s for Jumpers J not connecte d normally, the reference board draws all power from the motherboar d J2 jumper 2-. V secondary bus VIO J jump 2-0, -2, 7- assigns REQ# to slot 2, REQ# to slot, REQ#2 to slot 0 J jump 2-0, -2, 7- assigns GNT# to slot 2, GNT# to slot, GNT#2 to slot 0 J J not connecte d not connecte d J7 jumper -2 edge connector on primary bus supplies p_vio Before Powering the Board Using the switch, choose the speed setting for the secondary bus based upon the input primary bus speed: / / secondary / 2-2 CONFIG 2- MEN pri 2- MEN sec (Note: When primary bus is Mhz, regardless of how the bridge reference board is configured the bridge will be dynamically set to Mhz primary and Mhz secondary, with S_MEN driven low by the bridge.) Also, in the case of the motherboard having V keying and Mhz at the slot connector where our card will plug in, you may choose to shift J7 jumper down by one pin to cover the center pin and J. Where the Mhz PCI slot is keyed for.v, this jumper does not need to be moved. b) Seat the board into a PCI slot on the main system board. Looking from the front of the motherboard, the small lip on our reference board points to the back of the motherboard and the component side with the PI7C80 bridge chip is on the left hand side. Normally you won t need to connect power to the reference board through header J, unless you are cascading bridges. Otherwise the motherboard PCI connector is adequate to powering the board with a few add-in cards. c) Connect any PCI cards desired on the secondary PCI bus. For all PCI connectors on our reference board, when looking down onto the bridge IC, pin is on the left side of the board. Notice that the external arbiter socket on the front and the auxiliary power connector on the back are closest to PCI connector pin. This also applies to the top mounted straddle connector. Putting in any cards backwards will short V to ground through the PCI connector. Also each PCI connector has A, B, A2, B2 at the corners of each slot, as a reminder where pin is on each connector. At this point, the Pericom PI7C80 reference board is ready for you to use. 2

3 J U Pericom 80 bridge U2 Philips/Signetics N7F-D U not stuffed U Philips/Signetics N7F-D U PIB27-W Mux/Demux bus switch U7 socket for optional external arbiter U U7 U U2 SW J J J JP U J2 J J7 speed, options selection SW secondary clock control J auxiliary power J2 secondary bus Vio select J Grant# selection for slots.. J Req# selection for slots.. J not used J forces.v on primary Vio J7 primary Vio follows motherboard TABLES: a) Tables on the front remind shipping defaults for, SW. b) The back side of the board has a silkscreened table of test points T..T and TP9.., TP. c) Right side of board has JP,, list Switch listing SW: (does not exist) Signal Descri-ptio n bpcce "off" Enables bus/power clock control function (BPCCE is high) "on" puts a low at this signal. (This influences turning off PCI clocks under ACPI power management.) 2 cfg O f "" selects Bridge is Mhz capable. p_men When "" the bridge is set to Mhz on both primary and buses. secondary s_men "" sets P_MEN high. Mhz motherboard slot. Reference board can be used in either or reserve d O n "" sets Secondary bus is Mhz capable (S_MEN is high ) arbctrl 7 Not used "" forces Mhz (S_MEN low) No effect in either positio n secondary bus even if primary bus is Mhz.

4 SW 2 off sclock; off sclock; off sclock; off sclock7; off sclock8; O n F eedback clock is enabled. Turning this switch off hangs the secondary bus. Normally, at power on, the 2 components U2 and U report which secondary PCI connectors have the PRSNTx_ and PRSNTx_2 pins pulled low, implying there is a device at that location and it s power requirements. Switching through on simply forces the unused clocks on. The Feedback clock MUST be turned on, if our bridge is generating the secondary bus clock outputs. Jumper block listing J External Power Connector. left to right [ground, ground, ground, +.V, +.V, +V] This does NOT need to be connected in order to use the bridge. Pin is +V, pins - GND J2 Vio Select -2.V (left) -2 V (right) This sets Vio for the secondary bus. The PCI bridge will drive control signals to this voltage on the secondary bus. This should already be configured for you. J Grant Assignments to secondary PCI bus connector slots, 2, and. The ordinary PCI connectors have GNT# (and REQ#) assigned by jumpers. Notice that to the left of these are stenciled brackets; you may select only ONE of the possible jumper positions within a pair of brackets [ ] Thus, on our reference board, for the slot closest to the bridge, (which is mounted on the back of the board) {Gnt0 OR Gnt2 OR Gnt } jump one only of these choices we can monitor the grant signal for this slot at TP. For the next slot up {Gnt OR Gnt OR Gnt} jump only of the choices Monitor at TP J Req assignments These must match the positions chosen in J.! From bottom slot to top, {Req0 or Req2 or Req} monitor at TP {Req or Req or Req} monitor at TP {Req or Req7} monitor at TP fixed at Req8 top slot monitor at TP2 J Not used. J.V pin J allows a method to force the bridge to use.v signalling for communicating with a Mhz motherboard without disturbing the motherboard s Vio, which is only useful when an older motherboard has a Mhz PCI bus keyed for V. (This signal is NOT bused into the motherboard Vio.) J7 P_Vio select The topmost pin at J7 is P_Vio from the motherboard and the center pin goes to our bridge. Primary bus test points JP,, : These allow a logic analyzer or oscilloscope to monitor signals on the path between the 80 and primary bus. There are rows of header pins each, labeled JP, next, next : JP GNT AD0 AD27 AD2 AD22 AD9 AD REQ AD29 AD2 CBE AD2 AD8 CBE2 AD AD28 AD2 AD2 AD20 AD7 FRAM IRDY TRDY Devsl For the third slot up {Gnt OR Gnt7} jump only of the two choices Monitor at TP0 JP STOP LOCK SERR AD AD2 AD9 AD7 AD AD PAR AD AD CBE0 AD AD AD0 PERR CBE AD AD0 AD8 AD AD2 Idsel Top slot is fixed at Gnt8. Monitor at TP9 (A copy of this table is present on the right hand side of the component side of the reference board.)

5 Test points description: These allow convenient sampling of signals by logic analyzer or oscilloscope: T Primary TRST GPIO TP ground TP Gnt to 2 nd slot T2 Primary TCK GPIO TP2 ground TP2 Req to th (top) slot T Primary TMS GPIO TP ground TP Req to rd slot T INTA# TP ground TP Gnt to st (bottom) slot T Primary TDO GPIO TP ground TP Req to 2 nd slot T Primary TDI GPIO TP ground TP Req to st (bottom) slot T7 INTB# TP7 ground T8 Primary clock input TP8 ground T9 INTC# TP9 Gnt to top ( th ) slot T0 INTD# TP0 Gnt to rd slot T Primary Reset# OPTIONAL External Arbiter: For internal arbiter, - is CLOSED. This is the default. For external arbiter, a number of changes are made to the board:. Remove the 0 Ohm resistors at R, R, R7, R8 2. Stuff 0 Ohm resistors into R2, R22, R2, R2, R27, R28. Verify that J-8 (assigning REQ#0 to secondary bus slot 0) is open.. Instead, put the jumper at J-7.. Verify that J-8 (assigning GNT#0 to secondary bus slot 0) is open.. Instead, put the jumper at J Finally, stuff socket U with an appropriately programmed Xilinx XC972 CPLD (availability of code TBD) Pericom Semiconductor Corporation 280 Bering Drive San Jose, CA Fax (08) -00