PCI Development Backplane

Transcription

1 PCI Development Backplane User s Guide October Order Number: -00

2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel s website at Copyright Intel Corporation, *Third-party brands and names are the property of their respective owners. **ARM and StrongARM are trademarks of Advanced RISC Machines, Ltd. PCI Development Backplane User s Guide

3 Contents Introduction...-. Purpose...-. Audience...-. Manual Organization...-. Conventions Caution Note Numbering Signal Notation...-. Associated Documents...-. StrongARM and PCI...-. Key Features...- Installation...-. Delivered Items...-. Preparation...-. Fitting the Board...-. Connection of Power Supplies...- General Description...-. Overview...-. Signal Lines General Interrupts Reset...-. Arbitration...-. System Clocks...-. System Slot Compatibility Issues...- Configuration...-. Backplane Variants EBSA-BPL-V EBSA-BPL-V...-. Configuration Options Etchlinks...-. Configuring the Backplane Power Provision ID Select Arbiter Arbiter Source Lock Arbiter Algorithm Clock Frequency...-. Quick Reference Configuration Tables...- A Technical Data... A- A. Electrical Data... A- PCI Development Backplane User s Guide iii

4 A. Mechanical Data... A- A. Construction... A- A. Test Points... A- B Layout and Circuit Diagrams... B- B. Movable Keys... B- C Bill of Materials... C- Figures Tables - The in an SA-0 System Backplane Block Diagram Backplane Dimensions Backplane Layout Backplane Block Diagram Backplane Implementation of PCI bus Example of Etchlink Etchlink and Header Locations Power Connector Details...- B- Backplane Arrangement in a PC/AT Chassis... B- B- Jumper and Connector Locations... B- B- Circuit Diagram: System Slot... B- B- Circuit Diagram: Slot... B- B- Circuit Diagram: Slot... B- B- Circuit Diagram: Slot... B- B- Circuit Diagram: Slot... B- B- Circuit Details: Arbitration and System Clock Logic... B- B- Circuit Details: Power Connectors... B-0 C- Bill of Materials... C- - Interrupt Line Connections System Slot Arbiter: PCI Pinout (Request) System Slot Arbiter: PCI Pinout (Grant) Power Connector Combinations IDSEL Configuration Selection of Arbiter Source Selection of Clock Frequency...- iv PCI Development Backplane User s Guide

5 Introduction. Purpose This manual describes the features, installation and configuration of Intel s custom PCI development backplane. The backplane allows a wide variety of StrongARM** (and mixed processor) topologies to be tested. Specifically, it will allow verification and evaluation of all PCI I/O support component and future PCI related StrongARM product line developments as system masters and intelligent devices in desktop/server environments.. Audience The manual is intended for use by researchers, designers and developers who wish to experiment with or develop a variety of StrongARM-based system architectures using PCI as the primary interconnect mechanism.. Manual Organization Chapter, Introduction, introduces the PCI development backplane and identifies its key features. Chapter, Installation, provides general information on installation and connection of power. Chapter, General Description, provides an overview of the backplane, explains the implementation of signals and identifies compatibility issues. Chapter, Configuration, identifies and describes the configurable options and provides tables of jumper settings. Appendix A, Technical Data, provides electrical and mechanical information about the backplane. Appendix B, Layout and Circuit Diagrams, provides layout and circuit diagrams for completeness and to explain configuration options. Appendix C, Bill of Materials, provides a combined bill of materials for the EBSA-BPL-V and EBSA-BPL-V Development Backplanes. PCI Development Backplane User s Guide -

6 Introduction. Conventions This section defines product-specific terminology, abbreviations, and other conventions used throughout this manual... Caution Cautions indicate potential damage to equipment or loss of data... Note Notes emphasize particularly important information... Numbering All numbers are decimal or hexadecimal unless otherwise indicated. The prefix 0x indicates a hexadecimal number. For example, is decimal, but 0x and 0xA are hexadecimal. Otherwise, the base is indicated by a subscript; for example, 00 is a binary number... Signal Notation In the circuit diagrams provided in Appendix B, active negative signals are indicated by a bar or overline; for example, FRAME. Active positive signals have no bar. Multiple signals are indicated by a colon and square brackets. For example AD[:0] refers to address and data lines,,,,,, and 0. In text, active negative signals are suffixed by a # character. For example, IRDY#. Active positive signals have no suffix. This is consistent with the signal naming convention used in the PCI Local Bus specification.. Associated Documents The following associated documents may be required or helpful when using this manual: PCI Local Bus Specification, Revision.. Cypress CY0 datasheet (available from Cypress application notes (Crystal Oscillator Topics, Jitter in PLL-based Systems, Layout and Termination Techniques). (all available from Intel AP- application note; Pentium Pro Processor Power Distribution Guidelines (available from under Pentium Pro processors). This application note describes the VRM module. Semtech MP0 VRM Module Specification (available from - PCI Development Backplane User s Guide

7 Introduction. StrongARM and PCI The Core Logic Controller is part of Intel s provision of PCI I/O support for the StrongARM product family. Specifically, it is a support device for the SA-0 StrongARM microprocessor, integrating an SDRAM memory controller, PCI bus, DMA engine, UART (data leads only), timers, interrupt control, boot ROM/Flash and low speed (X-bus) I/O in a single device. The chip supports an optional system arbiter, which shares pins with the X-bus control signals making it an either/or option. Figure - shows a diagram of the and SA-0 in a Host Bridge application. Figure -. The in an SA-0 System The s PCI interface can be statically configured in one of two modes: As a device (configuration space enabled peripheral) on PCI As the system master (Host Bridge) An evaluation board (EBSA-) supporting both modes is available. It can also operate standalone where PCI is not required.this manual describes Intel s custom PCI backplane (Figure -), which complements the EBSA- offering. The backplane allows a wide variety of StrongARM (and mixed processor) topologies to be tested. Specifically, it will allow verification and evaluation of the and future PCI related StrongARM product line developments as system masters and intelligent devices in desktop/server environments. Figure -. Backplane Block Diagram aa00 -bit PCI slot -bit PCI slot -bit PCI slot -bit PCI slot -bit PCI system slot Clocks Arbiter -bit PCI bus PCI Development Backplane User s Guide -

8 Introduction. Key Features The backplane provides the following: Support for all features on the EBSA- module. An environment for verification, evaluation and benchmarking of StrongARM PCI support with the widest possible range of PCI peripherals. For this reason, the standard PCI I/O form factor adopted by the PC industry is used. The ability to use industry standard enclosures and PSUs. An environment suitable for testing all of Intel s current and future (standard form-factor assumed) PCI peripheral cards from the PPB, multimedia and communications business units with the StrongARM processor family. Of particular importance is interworking with the PCI bridge evaluation boards, allowing a wide variety of bridged bus topologies to be investigated and/or verified. -bit support (for future-proofing of the design). Two variants; EBSA-BPL-V complying with the V PCI signalling environment, and EBSA-BPL-V with the. V PCI signalling environment. Backplane provision of the PCI system clock and PCI arbitration. Optional support of PICMG-style arbitration from the system slot. Several link options have been provided to support different system configurations (see Section..).. PICMG = PCI Industrial Computer Manufacturers Group. Please see their website ( for more details. - PCI Development Backplane User s Guide

9 Installation. Delivered Items You should have received: This manual. Either backplane EBSA-BPL-V ( V signal levels) or EBSA-BPL-V (. V signal levels). A Voltage Reference Module (VRM). This may be separate, or it may be factory-fitted in connector J. With regard to installation, both boards are identical and will be installed in the same manner. You will also need: Either a PC/AT chassis, or standoffs for mounting the PCB Either an AT-style PSU with +. V output provision, or a standard AT-style PSU (+ V, + V and - V only) Caution: If your PSU has a +. V output that you wish to use, be sure to remove the VRM from the backplane BEFORE connecting power.. Preparation The backplane offers several configuration options for selection by the user. The most likely of these have been preselected as defaults by links fabricated in the etch (etchlinks). It is expected that these will be used by the great majority of developers. Alternatives to the default options can be chosen by cutting the etchlinks and fitting header links as appropriate. As not all combinations of options may be fail-safe the user should read Chapter, Configuration, before modifying the board or applying power. Caution: The backplane is a multilayer board. Take care not to damage etch or lower layers when cutting etchlinks. For more information, see Section.... The -V and DC_OK pins are not connected on the backplane. PCI Development Backplane User s Guide -

10 Installation. Fitting the Board Caution: Observe proper antistatic precautions when handling the board. The board can be fitted in any standard PC/AT enclosure. Alternatively, it can be installed on pillars on the workbench. Board dimensions are shown in Figure -. Figure -. Backplane Dimensions." (.mm) Bulkhead edge.0" (.mm) +.V connector +V, +V and -V connector Socket for +.V Voltage Regulator Module aa00. Connection of Power Supplies The board can be powered by either of two methods. Use either one, but NOT both. PC power supply with provision for + V, ± V and +. V connected to J and J. Standard PC/AT supply with + V and ± V connected to J, and a +. V Voltage Reference Module (VRM) fitted in J. Note: Note: J and J are standard PC motherboard power connectors. On J, the - V and PWRGD pins are not connected. The current required by an EBSA- with MB of SDRAM is typically 00 ma. This may be insufficient to reliably start some power supplies (PSUs). If you experience this problem, try increasing the load on the PSU by: adding cards to the backplane configuration attaching a disk to the PSU attaching a suitable load resistor ( to 0 Ω, rated at 0W) to the + V line of an available disk power harness. This should only be attempted by an appropriately qualified person.. Both backplanes are fitted with a connector to accept the supplied Voltage Reference Module (VRM). Backplane circuitry configures the installed VRM to. V. - PCI Development Backplane User s Guide

11 General Description. Overview The backplane (Figure -) is supplied in two versions; one for V and one for. V signalling environments. The differences are: The PCI connector keying The voltage applied to the power plane Figure -. Backplane Layout Power LEDs +.V connector +V, +V and -V connector Arbiter Socket for +.V Voltage Regulator Module PCI slots aa00 Both boards are compliant with the standard PC/AT outline and are drilled with common mounting holes allowing it to be fitted in generic eight-slot desktop or deskside enclosures. Five full-length -bit PCI slots are provided. Depending upon the backplane model purchased, the PCI slots will support either V or. V cards. Both will support universal cards. An onboard clock synthesizer provides separate PCI clocks for the five PCI slots and an onboard arbiter. PCI Development Backplane User s Guide -

12 General Description A block diagram of the backplane is shown in Figure -. Figure -. Backplane Block Diagram aa00 -bit PCI slot -bit PCI slot -bit PCI slot -bit PCI slot -bit PCI system slot Clocks Arbiter -bit PCI bus. Signal Lines.. General This section describes the implementation of signal lines provided on the backplane. The backplane provides all PCI signals except for JTAG boundary scan. The backplane implementation of the PCI bus is shown in Figure -. Figure -. Backplane Implementation of PCI bus Address and Data AD :00 C/BE :0# PAR FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL# SERR# PERR# AD : C/BE :# PAR REQ# ACK# LOCK# INTA# INTB# INTC# INTD# -bit Address and Data Extension REQ# GNT# SBO# SDONE# CLK# RST# aa00 - PCI Development Backplane User s Guide

13 General Description All signal lines are bussed as parallel traces between all slots with the following exceptions: The interrupt lines. The request/grant arbitration lines. DEVSEL to the PCI I/O slots (J-J). DEVSEL does not apply to the system slot. PCI clocks. PRSNT bits. These are ac coupled to 0 V on each of the I/O slots as additional ac grounds. MEN is tied to 0 V. The system is designed for MHz operation only. Pull-up resistors are provided on the following signals: SBO# and SDONE# REQ# and ACK# FRAME#, IRDY#, TDY#, STOP#, LOCK#, and DEVSEL# PERR# and SERR# INTA#, INTB#, INTC# and INTD# All arbiter request lines All -bit address and data extension lines DEVSEL may be optionally coupled via links and a resistor to a choice of AD lines as follows: PCI I/O slot - AD or AD (default AD via an etchlink) PCI I/O slot - AD or AD0 (default AD via an etchlink) PCI I/O slot - AD or AD (default AD via an etchlink) PCI I/O slot - AD or AD (default AD via an etchlink) See also the note on line numbering in Section..... Interrupts Interrupt connections are ORed in such a sequence that any add-in I/O board using INTA# can be uniquely recognized by the system. The interrupt lines are interconnected as shown in Table -. Table -. Interrupt Line Connections pina pinb pina pinb System slot INTA# INTB# INTC# INTD# I/O slot INTB# INTC# INTD# INTA# I/O slot INTC# INTD# INTA# INTB# I/O slot INTD# INTA# INTB# INTC# I/O slot INTA# INTB# INTC# INTD# PCI Development Backplane User s Guide -

14 General Description.. Reset RESET# must be provided by the system bridge device. No provision is made on the backplane for an external reset of the PCI. The arbiter will be reset asynchronously using this signal.. Arbitration Bus arbitration can be controlled by the backplane or from the system slot. The arbiter algorithm is compliant with the PCI Local Bus Specification, Revision.. For flexibility, this is implemented via a socketed PLD (Programmable Logic Device). The backplane arbiter fitted is based on an Altera Max 000* series device in a -pin PLCC package. The following signals are routed to and from all slots to the arbiter: A unique REQ# line for each slot with an external pullup A unique GNT# to each slot RESET# FRAME# and IRDY# to identify the bus idle condition LOCK# to identify resource lock cycles In addition, the following backplane control inputs and monitoring outputs are provided: A bank of programmable CONTROL bits ( per slot) defaulted high via pull-up resistors. These static control bits can be used as part of a -level priority or masking algorithm for the arbiter, assuming algorithm support. The algorithm shipped as standard does not use these inputs. An ARB_ENABLE# signal, which can be used to tri-state all outputs when an arbiter is provided by the system slot. A LOCK_ENABLE signal to allow the arbiter to optionally lock the bus on LOCK# cycles. This allows systems to switch between bus locked and resource locked configurations assuming the correct device support (hardware and/or software). Arbiter state monitoring outputs PCIARB[:0] are brought out to a header for ease of connection to a logic analyzer etc.. System Clocks System clocks are provided by a Cypress CY0SC- clock synthesizer/driver and a. MHz crystal. The CY0SC- has link options for MHz,. MHz, 0 MHz and MHz support. This device provides six PCI clocks with low jitter, slew limiting, and maximum skew of <0 ps in a -pin SOIC package. All other clock outputs are unused. There are no provisions for MHz clocking.. Default - via an etchlink. - PCI Development Backplane User s Guide

15 General Description. System Slot Compatibility Issues Modules using the backplane arbiter must satisfy the following criteria: Provide CONFIG cycles to configure the four I/O slots Support the INT[A-D]# pins as inputs from the I/O slots as described in Table - Provide PCI reset (RST#) for the system In addition, modules providing PCI arbitration must use the system slot in the backplane and route the arbitration signals according to Table - and Table -. Table -. System Slot Arbiter: PCI Pinout (Request) Arbitrated slot REQ I/O slot B REQ# (SYSCPU_REQ0) I/O slot 0B) Reserved (REQ) I/O slot A Reserved (REQ) I/O slot B PRSNT# (REQ) Note: Table -. In the above table the first name is the name as specified in the PCI standard, the bracketed name is the signal name on the backplane. System Slot Arbiter: PCI Pinout (Grant) Arbitrated slot GNT I/O slot A GNT# (SYSCPU_GNT0) I/O slot A Reserved (GNT) I/O slot A IDSEL (GNT) I/O slot B PRSNT# (GNT) Note: In the above table the first name is the name as specified in the PCI standard, the bracketed name is the signal name on the backplane. Arbitration for the bus by the system slot module must occur within the card itself. Note: The sharing of the grant pin and IDSEL can cause problems in systems that issue PCI configuration cycles in I/O slots. It is becoming common practice for intelligent I/O to interrogate the bus in this manner. System designs that use this backplane, and want to use system slot arbitration, must NOT tie the arbiter grant and IDSEL lines together on the module. It will not be possible for an I/O slot to interrogate the system slot with configuration cycles. PCI Development Backplane User s Guide -

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17 Configuration. Backplane Variants Two variants with different PCI signalling voltages are available. Variant EBSA-BPL-V provides V signalling; variant EBSA-BPL-V provides. V signalling. The choice of backplane purchased affects two features: PCI connector polarization voltage level Note: PCI signalling voltage is a factory set option. It is not user configurable... EBSA-BPL-V On this backplane: The PCI connectors are keyed at pin positions / and 0/. Soldered links W and W are fitted; W and W are not... EBSA-BPL-V On this backplane: The PCI connectors are keyed at pin positions / and /. Soldered links W and W are fitted; W and W are not.. Configuration Options Several backplane configuration options are available. These are related to: Provision of a +. V DC supply ID Select standard Arbiter source Clock frequency The last three of these options are selected by etchlinks (see the following section) or header links. PCI Development Backplane User s Guide -

18 Configuration.. Etchlinks Etchlinks (links formed in the etch during fabrication) are used for selection of common defaults, with headers provided for jumper selection of other options. The etchlinks can be cut and jumpers fitted for verification modes, for example, switching between backplane and system-slot-based PCI arbitration. Figure - shows a general example. Figure -. Example of Etchlink Etchlink Link default Signal Header Other link option aa00 Etchlinks are all on layer with plenty of trace clearance to allow them to be cut without risk of accidentally damaging other inner layer traces. The available options will now be described. Refer to Figure - for component layout and to Appendix B for circuit diagrams. A set of quick reference configuration tables is provided at the end of this chapter. Caution: Figure -. If you use header links to select your options, make sure the associated etchlinks have been cut. Etchlink and Header Locations - PCI Development Backplane User s Guide

19 Configuration. Configuring the Backplane This section details the etchlinks to cut, and the jumpers to fit, for the desired method of operation... Power Provision Two mutually exclusive methods of power connection are available: PC/AT PSU to J and a. V Voltage Regulator Module (VRM) on J PC/AT PSU with standard and. V outputs. Standard to J and. V to J Caution: J and J are weakly keyed. Take care to use the correct connector; the keying mechanism can be easily overridden. Layouts, pinouts and PSU sleeve colors are shown in Figure -. Note: The current required by an EBSA- with MB of SDRAM is typically 00 ma. This may be insufficient to reliably start some power supplies (PSUs). If you experience this problem, try increasing the load on the PSU by: adding cards to the backplane configuration attaching a disk to the PSU attaching a suitable load resistor ( to 0 Ω, rated at 0 W) to the + V line of an available disk power harness. This should only be attempted by an appropriately qualified person. Figure -. Power Connector Details Corner of PCB J J Orange - (nc) PWR GD GND Red - +V GND Black Yellow - +V GND Blue - -V +.V GND +.V Black - GND GND +.V +.V Brown GND +.V White - (nc) -V +.V +V 0 GND Red - +V GND Black +V GND aa0. Industry standard connector supplying + V and ±V (the - V and PWRGD pins are not connected). PCI Development Backplane User s Guide -

20 Configuration.. ID Select On the PCI bus, AD: are normally used for IDSEL#. However, the PICMG standard specifies AD:. Provision for both is made on the board. By default, AD: are etchlinked to IDSEL#. If the etchlinks are cut for any reason, this same selection can be made by jumpering - on J to J. For the PICMG standard, cut etchlinks EL to EL, and install jumpers on J to J, position -. Note: The PICMG standard specifies decrementing address line numbering with incrementing slot numbers. This is the convention adopted in the backplane labelling; however, it can be very confusing for those unaware of the issue when developing PCI configuration code... Arbiter The onboard arbiter allows the backplane to provide arbitration for the PCI bus.... Arbiter Source... Lock Bus arbitration can be controlled from either the backplane arbiter (default) or the system slot. Etchlinks on system-slot GNT# (EL), system-slot REQ# (EL) and ARB_ENABLE# (EL) select the backplane arbiter. If the etchlinks are cut for any reason, this same selection can be made by jumpering - on J, J0 and J. To use a system slot arbiter, cut etchlinks EL- and fit jumpers on - of J, J0 and J. All three links (slot 0 grant routing, slot 0 request routing, and arbiter enable) need to be changed in unison. LOCK_ENABLE is a control signal for the arbiter. It is pulled high by default.... Arbiter Algorithm For developers who may wish to use their own arbitration algorithms, five optional control inputs (CNTRL 0 to ) are made available for grounding on J. All are pulled high by default... Clock Frequency S0 and S are the PCI clock speed select lines for the CY0 clock synthesizer. Both have pullups. Options are MHz,. MHz, 0 MHz and MHz. Etchlink EL grounds S (CLK_SEL ), defaulting the bus clock to MHz. If EL is cut, MHz is selected by a jumper on header J, CLK_SEL. To select MHz, cut the etchlink and fit jumpers on headers J, CLK_SEL_0 and. For. MHz, simply cut the etchlink. For 0 MHz, cut the etchlink and fit a jumper on header J, CLK_SEL 0.. PICMG = PCI Industrial Computer Manufacturers Group. Please see their website ( for more details. - PCI Development Backplane User s Guide

21 Configuration. Quick Reference Configuration Tables The following tables summarize the configurable options provided on the backplane. See Section. for a more detailed description. Caution: Table -. ID select lines, arbiter source and clock frequency defaults are set by etchlinks. Do not use header links unless the associated etchlinks have been cut. Table - to Table - assume that the associated etchlinks have been cut. Power Connector Combinations PSU type Connect to J Connect to J VRM on J PC/AT YES NO YES PC/AT with +.V provision YES YES NO Table -. IDSEL Configuration Hdr Link in Position - Hdr Link in Position - J AD AD * J AD0 AD * J AD AD * J AD AD * * Default - via EL,, and Table -. Selection of Arbiter Source Arbiter J (ARB_ENABLE) J0 (REQ 0/) J (GNT 0/) Backplane * Link position - Link position - Link position - System Link position - Link position - Link position - * Default - via EL, and Table -. Selection of Clock Frequency Frequency CLK_SEL 0 CLK_SEL MHz IN IN. MHz OUT OUT 0 MHz IN OUT MHz * OUT IN * Default - via EL PCI Development Backplane User s Guide -

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23 Technical Data A A. Electrical Data The backplane complies with the PCI Local Bus Specification, Revision.x, thereby making the design as flexible as possible: The larger connectors provide a -bit PCI environment. V or. V signalling versions available, with a signal plane to provide the appropriate voltage to the connector pins, the active logic, and associated pullups. Programmable backplane arbiter provided on socket U. This is implemented in an Altera MAX 000* device operating at V but with separate I/O power pins that can operate at V or V. Low skew, slew limited system clocks to all slots and the backplane arbiter. The system clock generator is based on a Cypress CY0- clock synthesizer/driver which provides six compliant PCI clock pins. The CY0 can operate from V or. V. + V, + V and - V supplies from an industry standard PC/AT PSU are connected via J. PowerOK and - V from the power supply are not used. +. V can either be supplied on industry standard connector J from a power supply unit, or it can be converted down from + V by a. V Voltage Reference Module (VRM) connected to J. These two options are mutually exclusive. A warning to this effect is silk-screened onto the board. A. Mechanical Data The board is mechanically compliant with standard PC/AT outline (smaller size, using a subset of the mounting holes), allowing it to be fitted to generic -slot desktop or deskside enclosures. Five full-length -bit PCI slots are supported (no motherboard component restrictions). The PCI connectors support V,. V or mixed voltage cards according to the backplane variant purchased. The five slots occupy an -slot AT card enclosure (reading from right to left as viewed from the rear of the enclosure) as follows: slot 0 - empty - no connector slot - empty - no connector slot - system slot slot - PCI I/O slot slot - PCI I/O slot slot - PCI I/O slot slot - empty - no connector slot - PCI I/O slot This maximizes access to the component side of the system and one I/O slot for logic analyzer attachment, probing, daughtercards, etc. Note: Due to the height of components, the EBSA- PCI Development Board occupies two slots of an AT motherboard. On the backplane, space is provided to the left of the system-slots and I/O-slots to allow the EBSA- to be installed in either of these positions without sacrificing one of the other slots. PCI Development Backplane User s Guide A-

24 Technical Data A. Construction The backplane is an -layer board with the following layer makeup: Component side - pads, etchlinks and dispersion etch only - power plane Signal layer +. V plane GND plane Signal layer + V power plane Solder side - pads only A. Test Points For ease of connection to power and ground planes, a range of through-plated holes to take 0.0 inch (0. mm) square-posts, is provided for the construction of test points. These are not shown on the schematics but are silk-screened on the etch. The following test point positions are provided: GND TP to GND TP TP to TP TP V TP A- PCI Development Backplane User s Guide

25 Layout and Circuit Diagrams B This appendix contains layout and circuit details of the PCI backplane. Figure B-. Backplane Arrangement in a PC/AT Chassis PCI Development Backplane User s Guide B-

26 Layout and Circuit Diagrams Figure B-. Jumper and Connector Locations B- PCI Development Backplane User s Guide

27 Layout and Circuit Diagrams B. Movable Keys In Figures B- through Figure B-, the. V key, which is referenced as.v Key, and the V key, referenced as V Key, allows the module to be configured for either.v or V enviroments, but not both. The. V key is located between pins 0 and 0 on side, and pins and on side. The V key is located between pins and on side, and and on side. PCI Development Backplane User s Guide B-

28 Layout and Circuit Diagrams Figure B-. Circuit Diagram: System Slot R0.K R.K R.K U U U R.K C0 C 0.UF C C 0.UF R.K C 0.UF C C 0.UF C 0.UF C 0.UF R.K R.K +.V R.K - CBE[:0] CBE CBE CBE CBE REQ REQ GNT PCICLK0 SYSCPU_REQ0 AD AD AD AD AD AD AD AD CBE CBE CBE0 CBE IRDY DEVSEL LOCK PERR SERR AD AD AD0 AD AD AD AD AD ACK V -, -V B A J , +V +.V GNT - RESET REQ GNT - FRAME - TRDY - STOP - SDONE - SBO - PAR - REQ - INTD INTC - - INTB INTA - SYSCPU_GNT0 AD0 AD AD AD AD AD0 AD AD AD AD AD AD AD AD AD AD0 - AD[:0] GNT[:] - REQ[:] - V Key Key.V Key SYSTEM SLOT ARBITER: Cut etchlinks and *ALL* links - BACKPLANE ARBITER: Etchlinks and/or *ALL* headers - CUT LINKS AND USE HEADERS FOR PICMG-STYLE ARBITRATION FROM SYSTEM SLOT ETCHLINKS PROVIDE DEFAULT CONNECTIONS FOR BACKPLANE ARBITRATION System Slot: -Bit PCI PLEASE NOTE INTD INTC INTB INTA SERR PERR ACK REQ AD AD AD AD PAR AD AD0 AD R.K GNT SYSCPU_GNT0 GNT0 REQ SYSCPU_REQ0 REQ0 AD AD AD AD R0.K R.K R.K R.K R.K R.K R.K R.K AD AD 0 AD AD0 AD EL ETCHLINK EL ETCHLINK EL ETCHLINK AD 0 0 AD AD AD AD AD AD J J A0-0 zz00 DEVSEL LOCK STOP IRDY TRDY FRAME SBO SDONE AD AD AD AD AD0 AD AD AD AD ARB_ENABLE J0 B- PCI Development Backplane User s Guide

29 PCI Development Backplane User s Guide B- Layout and Circuit Diagrams Figure B-. Circuit Diagram: Slot A0-0 R R IDSEL AD AD AD AD AD0 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD0 AD AD AD AD AD AD AD AD0 AD AD AD0 AD AD AD AD AD AD AD0 AD AD AD0 AD AD AD AD0 AD AD AD AD AD AD AD AD[:0] AD -V AD U C 0.UF C 0.UF C 0.UF C 0.UF C U C 0.UF C +.V 0.UF C U C AD SERR PERR IRDY LOCK DEVSEL PAR STOP TRDY SBO SDONE GNT 0.UF C 0.UF C PCICLK REQ +V REQ J PAR INTD INTB ACK RESET FRAME INTA +.V INTC +.V ETCHLINK EL B A J CBE0 CBE CBE CBE CBE CBE CBE CBE CBE[:0] zz00 -Bit PCI IO Slot.V Key V Key Key

30 B- PCI Development Backplane User s Guide Layout and Circuit Diagrams Figure B-. Circuit Diagram: Slot A0-0 R R IDSEL U C 0.UF C +.V 0.UF C U C 0.UF C 0.UF C 0.UF C 0.UF C U C0 REQ SBO TRDY SDONE PAR FRAME GNT AD AD AD AD AD AD[:0] AD AD AD AD AD AD0 AD AD AD AD0 AD AD AD0 AD AD AD AD AD AD AD0 AD AD AD AD0 AD AD AD AD AD AD AD AD0 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD0 AD AD SERR PERR LOCK DEVSEL IRDY ACK PAR J INTA STOP RESET +V REQ PCICLK 0.UF C 0.UF C AD0 -V INTC AD INTB INTD +.V +.V ETCHLINK EL B A J CBE[:0] CBE CBE CBE CBE CBE CBE CBE CBE0 zz00 -Bit PCI to SLOT.V Key V Key Key

31 PCI Development Backplane User s Guide B- Layout and Circuit Diagrams Figure B-. Circuit Diagram: Slot A0-0 R R IDSEL AD J U C 0.UF C 0.UF C 0.UF C 0.UF C U C 0.UF C +.V 0.UF C0 U C REQ SBO TRDY SDONE PAR FRAME GNT AD AD AD AD AD AD[:0] AD AD AD AD AD AD0 AD AD AD AD0 AD AD AD0 AD AD AD AD AD AD AD0 AD AD AD AD0 AD AD AD AD AD AD AD AD0 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD0 AD AD SERR PERR LOCK DEVSEL IRDY ACK PAR INTB STOP RESET +V REQ PCICLK 0.UF C 0.UF C AD INTD INTC +.V INTA +.V -V ETCHLINK EL B A J CBE[:0] CBE CBE CBE CBE CBE CBE CBE CBE0 zz00-b -Bit PCI IO Slot.V Key V Key Key

32 B- PCI Development Backplane User s Guide Layout and Circuit Diagrams Figure B-. Circuit Diagram: Slot A0-0.K R.K R CBE CBE.K R.K R.K R.K R.K R.K R.K R.K R.K R CBE.K R.K R R R0 IDSEL U C0 0.UF C +.V 0.UF C U C 0.UF C 0.UF C 0.UF C 0.UF C U C AD REQ SBO TRDY SDONE PAR FRAME GNT AD AD AD AD AD AD[:0] AD AD AD AD AD AD0 AD AD AD AD0 AD AD AD0 AD AD AD AD AD AD AD0 AD AD AD AD0 AD AD AD AD AD AD AD AD0 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD0 AD AD SERR PERR LOCK DEVSEL IRDY ACK PAR J INTC STOP RESET +V REQ PCICLK 0.UF C0 0.UF C AD INTB INTD +.V INTA +.V -V ETCHLINK EL B A J.K R.K R.K R.K R.K R.K R.K R0.K R.K R.K R.K R.K R.K R AD0 AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD.K R.K R.K R0.K R.K R.K R.K R.K R AD AD AD AD AD0 AD AD AD AD AD0 AD AD AD AD AD AD.K R.K R CBE.K R0 PAR CBE[:0] CBE CBE CBE CBE CBE CBE CBE CBE0 zz00 -Bit PCI IO Slot.V Key V Key Key

33 Layout and Circuit Diagrams Figure B-. Circuit Details: Arbitration and System Clock Logic ;,,,0, GND;,,, U DEVICE=CY0SC- R.K CLKSEL CLKSEL0 CLK_ENABLE OE PCICLK R R ARBCLK PCICLK S0 PCICLK R S R PCICLK PCICLK PCICLK R R PCICLK PCICLK0 R R PCICLK CPUCLK 0 CPUCLK R R PCICLK CPUCLK CPUCLK0 R R PCICLK0 REF REF0 CLKB CLKA XTAL_IN XTALIN XTALOUT XTAL_OUT CY0 NC XTAL_SM.MHZ CLOAD - MAY NOT BE FITTED C 0PF XTAL_IN P N XTAL_OUT X NC C 0.UF C 0.UF C 0.UF C 0.UF C0 0.UF C 0.UF Clock trace decoupling REQ0 REQ REQ REQ REQ LOCK IRDY FRAME LOCK_ENABLE ARB_ENABLE RESET ARBCLK ETCHLINK EL J HEADX CNTRL0 CNTRL CNTRL CNTRL CNTRL zz00.k CNTRL0 CNTRL CNTRL CNTRL CNTRL LOCK_ENABLE CLKSEL0 CLKSEL REQ0 REQ REQ REQ REQ 0 RNET RPK0A E RSVD RSVD RSVD 0 RSVD RSVD RSVD RSVD 0 RSVD BPARB RSVD RSVD0 RSVD RSVD RSVD RSVD RSVD 0 RSVD CTRL0 CTRL CTRL 0 CTRL RSVD0 OE CTRL RSVD RSVD RSVD RSVD0 RSVD RSVD RSVD RSVD ARB_SM ARB_SM ARB_SM0 0 REQ0 REQ REQ REQ REQ LOCK IRDY FRAME LOCK_ENABLE ARB_ENABLE RESET PCICLK PCIARB PCIARB PCIARB0 GNT0 0 GNT GNT GNT GNT TEST GNT0 GNT GNT GNT GNT J U BPARB SOCKETTED ;, ;,,,,, GND;,,,,,,, Altera MAXk (BPARB) decoupling C0 0UF C 0.UF C 0.UF C 0.UF C 0.UF C 0.UF C 0.UF C 0.UF CY0 decoupling C 0UF C 0.UF C 0.UF C 0.UF C 0.UF C 0.UF C 0.UF PCI Development Backplane User s Guide B-

34 VID 00 Layout and Circuit Diagrams Figure B-. Circuit Details: Power Connectors 0.UF 0.UF R 0.UF 0.UF R R -V +V C U -V +V C0 U C +.V C U C.K R K.K R C U 0 C C C A D A C D A C D A C D Backplane voltage LED's WARNING - NC PIN HAS -V FROM PSU WARNING - NC PIN HAS DC_OK FROM PSU Standard Power Connector 0 J P P U C U C +.V.K R 00 UP Voltage Reference Module for.v 0 00 VID R VID0 NC_PRORES +V J.V Power Connector A0 A A A A A A A A A A0 A A A A A A A A A J B0 B B B B B B B B B B0 B B B B B B B B B NC_PWRGD VID OUTEN NC_PRORES +.V.K R.K R0 WIRELINK W WIRELINK W +.V +V = V WHEN FITTED ***WARNING*** FIT V *OR* V LINKS WIRELINK W WIRELINK W = V WHEN FITTED voltage selection zz00 R B-0 PCI Development Backplane User s Guide

35 Bill of Materials C A combined bill of materials (Figure C-) for the EBSA BPL V and EBSA BPL V Development Backplanes is given on the next page. PCI Development Backplane User s Guide C-

36 Bill of Materials Figure C-. Bill of Materials A0-0 C- PCI Development Backplane User s Guide

37

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