Intel MHz PCI Bridge

Transcription

1 Intel MHz PCI Bridge Product Features PCI Bus Interfaces PCI Local Bus Specification, Revision 2.3 compliant PCI-to-PCI Bridge Architecture Specification, Revision 1.1 compliant PCI Bus Power Management Interface Specification, Revision 1.1 compliant PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant Masquerade Mode Message Signal Interrupt (MSI) support External SROM support Vital Products Data (VPD) support Subsystem ID/Subsystem Vendor ID ECR support Compact PCI Hot Swap Specification, Revision 2.1 Support HW Support for Compact PCI (cpci) Redundant System Slot configured platforms 64-bit Initiator/Target Capable 64-bit addressing Datasheet Asynchronous cflocking in PCI mode Secondary Bus Arbitration Internal Arbiter Supports nine agents in addition to VerrazanoX Internal Arbitration can be disabled Optimized for PCI-X R1.0a mode Bus parking on bridge or last master Improved Buffer Architecture 8K Byte Data Buffers in each direction Improved level of Concurrency Up to nine outstanding transactions on each bus Scalability/Flexibility PCI R2.3 32/64-bit 33/66 MHz, 3.3 V 5VTolerant PCI-X R1.0a 32/64-bit 66/100/133 MHz, 3.3 V JTAG Interface GPIO Interface Allows simple software-controlled signaling protocols Order Number: January 2004

2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel MHz PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel's website at Intel, Intel logo, and Intel XScale are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2004, Intel Corporation 2 Datasheet

3 Contents Contents 1 Introduction About This Document Product Overview Signal Pin Types and Descriptions PCI Bus Interfaces PCI Bus Interface 64-Bit Extension Bus Interface Clocks and Reset JTAG Interface Serial EEROM Interface Compact PCI Hot Swap Interface Hardware Straps Miscellaneous Signals Power and Ground Signals Ball Table Mappings Electrical Specifications Absolute Maximum Ratings Operating Conditions Power Supply and Thermal Requirements Power Supply Special Considerations A and A Pin Requirements Targeted DC Specifications IO Types Targeted AC Specifications AC Timing Waveforms AC Test Conditions...47 Figures Bridge Assembly Drawing Bridge Ball Map Left Side Bridge Ball Map Right Side Installing a Shottky Diode A and A Lowpass Filter Clock Timing Measurement Waveforms Output Timing Measurement Waveforms Input Timing Measurement Waveforms AC Test Load for All Signals Except PCIX PCI/PCI-X Tov(max) Rising Edge AC Test Load PCI/PCI-X Tov(max) Falling Edge AC Test Load PCI/PCI-X Tov(min) AC Test Load...49 Datasheet 3

4 Contents Tables 1 PCI to PCI Bridge Configurations Signal Pin Types PCI Bus Interfaces Device Mode/Frequency Capability Reporting PCI Bus Interface 64-Bit Extension (Two Interfaces) Bus Interface Clocks and Reset JTAG Serial EEROM Interface Compact PCI Hot Swap Hardware Straps Miscellaneous Signals Power and Ground Signals Pinout Ballpad Number Order Pinout Signal Order Absolute Maximum Ratings Operating Conditions Power Supply and Thermal Requirements IO Types DC Characteristics Icc Characteristics Input Clock Timings PCI Signal Timings PCI-X Slew Rates Boundary Scan Signal Timings CMOS General Purpose Interface Timings Bypass Mode Timings AC Measurement Conditions Datasheet

5 Contents Revision History Date Revision Description May Initial release August updated document title; corrected ballmap January updated Section 3.4 Datasheet 5

6 Introduction Introduction About This Document This document provides information on the Intel MHz PCI Bridge, including a functional overview, mechanical data, package signal location and bus functional waveforms. 1.2 Product Overview The Intel MHz PCI Bridge (also called Bridge) is a PCI component that functions as a highly concurrent, low latency transparent bridge between two PCI busses. The Bridge is capable of operating as a PCI-to-PCI bridge in the configurations shown in Table 1. The Bridge is used on motherboards to provide additional I/O expansion slots. It is also used on PCI add-in cards as a means of mitigating the restrictive electrical loading constraints imposed on an expansion slot, enabling multiple conventional PCI or multiple PCI-X devices to reside on a single PCI I/O adapter. The Bridge has additional hardware support for Compact PCI Hot Swap and Redundant System Slot via queue flush, arbiter lock, and clock output tri-stating. The Bridge supports any combination of 32- and 64-bit data transfers on its primary and secondary bus interfaces. The bridge is 33/66 MHz capable in conventional PCI mode, and can run at 66 MHz, 100 MHz, or 133 MHz when operating in PCI-X mode depending upon its surrounding environment. Table 1. PCI to PCI Bridge Configurations PrimaryBus Interface SecondaryBus Interface PCI Local Bus Specification, Revision 2.3 PCI Local Bus Specification, Revision 2.3 PCI Local Bus Specification, Revision 2.3 PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b PCI Local Bus Specification, Revision 2.3 PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b The Bridge is offered in a 421-lead PBGA package. This package is shown in Figure 1. Figure 2 shows the left side of the Bridge ball map. Figure 3 shows the right side of the ball map. 6 Datasheet

7 Introduction Figure Bridge AssemblyDrawing Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M Dimension is measured at the maximum solder ball diameter, parallel to primary datum Ø PIN #1 CORNER Primary datum and seating plane are defined by the 3 spherical crowns of the solder balls. 4. All dimensions, unless otherwise specified, are in millimeters. SEE DETAIL "A" // A ± ± 0.20 Ø 0.30 S C A S B S REF A B C D E F G H J K L M N P R T U V W Y AA AB AC B REF 1.27 BOTTOM VIEW (22.10 REF) ± ± A 3 X Ø1.00 THRU (22.10 REF) 45 CHAMFER 4 PLACES TOP VIEW PIN #1 CORNER NO RADIUS Au GATE ± ± // 0.15 C 90.0 PIN #1 I.D. (SHINY) 1.0 DIA. X 0.15 DEPTH 9.0 X 9.0 FROM CENTER LINE C ± ± 0.10 SIDE VIEW 3 SEATING PLANE DETAIL "A" NOT TO SCALE B Datasheet 7

8 Introduction Figure Bridge Ball Map Left Side A ACK64# AD56 AD60 CBE4# CBE7# P P PAR64 B AD43 AD54 SERR# AD49 AD50 AD52 AD55 AD57 AD59 AD63 CBE6# C SCAN_ EN AD48 STOP# P CLK OEN3 AD53 PERR# AD58 AD61 CBE5# REQ64# D E F CLK OEN2 AD38 AD47 CLK OEN1 QE AD45 P AD51 AD42 AD44 AD46 P AD62 H H H P R_REF LED_ OUT LSTAT ENUM# TRI STATE H FREQ0 G AD36 CLK OEN0 AD41 P H SM H AD35 AD39 AD40 M66EN J AD33 AD34 AD37 SR_ CLK K AD34 AD33 AD32 L AD32 AD36 AD35 SR_CS M P AD39 AD38 SR_DO N AD41 AD40 SR_DI P AD47 AD45 AD43 R AD37 AD49 AD48 GNT7# T VIO AD51 AD50 REQ7# U AD42 AD53 AD52 P GNT6# V AD55 MAX 100 AD54 W AD44 REQ2# CLK STABLE P REQ6# Y AD46 GNT2# AD56 P P AD57 CBE7# AA NC REQ1# TMODE 2 AD58 AD59 AD61 ACK64# AD00 PAR64 CBE5# AD06 AB GNT1# REQ3# GNT4# REQ4# AD60 AD62 AD63 AD01 CBE6# AD04 CBE0# AC CRS P P REQ5# GNT5# GNT3# TEN CBE4# AD02 AD B Datasheet

9 Datasheet 9 Introduction Figure Bridge Ball Map Right Side B A B C D E F G H J K L M N P R T U V W Y AA AB AC P A P TDI TCK P GPIO7 GPIO6 GPIO4 TMODE 1 OPAQUE _EN IDSEL_ MASK TMODE 3 RSRV0 DEV_ 64BIT# GPIO3 GPIO5 P TMODE 0 P P AD06 AD03 MT0# CBE2# DEV SEL# AD22 CLK GPIO2 CLKO0 CLKO2 CLKO1 CLKO4 GPIO1 GPIO0 H FREQ1 NT_ MASK# AD24 RST# AD16 AD26 AD14 AD20 AD31 AD19 AD25 AD21 AD23 CLKO3 AD27 AD28 CLKO5 AD27 CLKO6 AD30 AD31 AD25 AD26 AD28 BRG CLKO CLK07 CLKO8 M66EN AD24 PCIX CAP AD23 AD20 ARB _DIS ABLE AD22 GCLK OEN AD19 RST# AD18 AD16 AD17 AD14 AD29 CBE3# AD10 AD07 FRAME# PAR AD09 CBE1# REQ64# CBE2# STOP# A CLKI AD12 SERR# DEVSEL# IRDY# AD08 AD05 MT1# PERR# GNT0# AD13 REQ0# AD29 AD30 AD18 AD17 VIO AD12 AD13 AD11 AD01 AD07 AD04 FRAME# IRDY# CBE3# CBE0# AD00 AD02 CBE1# REQ# AD15 AD08 AD05 TRDY# IDSEL GNT# PAR AD10 AD09 TRST# P TMS REQ8# AD15 AD21 GNT8# TRDY# AD11 P P P TDO

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11 Introduction Datasheet 11

12 Signal Pin Types and Descriptions Signal Pin Types and Descriptions 2 Table 2 lists and describes the MHz PCI Bridge signal pin types. Table 2. Signal Pin Types Symbol I O I/O OD Ts Sts Description Input pin only Output pin only Pin can be either an input or output Open Drain pin Tri-State Sustained Tri-State PWR Power pin (See Section 2.9) GND Ground (See Section 2.9) The following sections describe the signals for the PCI interfaces. Section 2.1, PCI Bus Interfaces Section 2.2, PCI Bus Interface 64-Bit Extension Section 2.3, Bus Interface Clocks and Reset Section 2.4, JTAG Interface Section 2.5, Serial EEROM Interface Section 2.6, Compact PCI Hot Swap Interface Section 2.7, Hardware Straps Section 2.8, Miscellaneous Signals Section 2.9, Power and Ground Signals Section 2.10, Ball Table Mappings The # symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When # is not present after the signal name, the signal is asserted when at the high voltage level. 12 Datasheet

13 Signal Pin Types and Descriptions 2.1 PCI Bus Interfaces This section describes the signals related to the PCI Bus Interfaces. The MHz PCI Bridge implements two independent PCI-X buses (a Primary and a Secondary bus). See the PCI-X Addendum to the PCI Local Bus Specification 1.0b for more information. Table 3. PCI Bus Interfaces (Sheet 1 of 3) Signal Width Type Description AD[31:0]; AD[31:0] 32; 32 Ts-I/O PCI Address/Data: These signals are a multiplexed address and data bus. During the address phase or phases of a transaction, the initiator drives a physical address on AD[31:0]. During the data phases of a transaction, the initiator drives write data, or the target drives read data. CBE#[3:0]; CBE#[3:0] 4; 4 Ts-I/O Bus Command and Byte Enables: These signals are a multiplexed command field and byte-enable field. During the address phase or phases of a transaction, the initiator drives the transaction type on C/BE#[3:0]. When there are two address phases, the first address phase carries the dual address command and the second address phase carries transaction type. For both read and write transactions, the initiator drives byte enables on C/BE#[3:0] during the data phases. PAR; PAR 1; 1 Ts-I/O Parity: Even parity calculated on 36 bits AD[31:0] plus C/BE[3:0]#. This is calculated on all 36 bits regardless of the valid byte enables, and is generated for address and data phases. This is driven identically to the AD[31:0] lines, except that it is delayed by exactly one PCI clock. PAR is an output during the address phase for all MHz PCI Bridge-initiated transactions and all data phases when MHz PCI Bridge is the initiator of a PCI write transaction. DEVSEL#; DEVSEL# 1; 1 Sts-I/ O Device Select: As a target, the MHz PCI Bridge asserts DEVSEL# when a PCI master peripheral attempts to access an internal address or the address of a resource that resides on the MHz PCI Bridge's other bus. As an initiator, DEVSEL# indicates the response to a MHz PCI Bridge-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the MHz PCI Bridge until driven as a target. FRAME#; FRAME# 1; 1 Sts-I/ O Frame: FRAME# is driven by the Initiator to indicate the beginning and duration of an access. While FRAME# is asserted, data transfers continue. When FRAME# is negated, the bus is either idle or is in the final data phase of the current bus transaction. IRDY#; IRDY# 1; 1 Sts-I/ O Initiator Ready: IRDY# indicates the ability of the initiator to complete the current data phase of the transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted. TRDY#; TRDY# 1; 1 Sts-I/ O Target Ready: Indicates the ability of the target to complete the current data phase of the transaction. A data phase is completed when both TRDY# and IRDY# are sampled asserted. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the MHz PCI Bridge until driven as a target. STOP#; STOP# 1; 1 Sts-I/ O Stop: Indicates that the target is requesting an initiator to stop the current transaction. Datasheet 13

14 Signal Pin Types and Descriptions Table 3. PCI Bus Interfaces (Sheet 2 of 3) Signal Width Type Description PERR#; PERR# 1; 1 Sts-I/ O Parity Error: Driven by an external PCI device when it receives data that has a parity error one PCI Clock following the PAR/PAR64 signal assertion. Driven by the MHz PCI Bridge when, as an initiator, it detects a parity error during a read transaction as well as when receiving bad parity as the target of a write transaction. SERR# 1 Od SERR# 1 I REQ# 1 Ts-O GNT# 1 I REQ[8:1]# 8 I Primary System Error: SERR#canbepulsedactivebyanyPCIdevice(includingthe MHz PCI Bridge) that detects a system error. Secondary System Error: SERR# can be pulsed active by any PCI device (except the MHz PCI Bridge) that detects a system error condition. The MHz PCI Bridge samples SERR# as an input and conditionally forwards it to its primary interface. Primary Bus Request: The MHz PCI Bridge bus acquisition request input to the primary bus arbiter. Primary Bus Grant: Low assertion indicates that the MHz PCI Bridge is granted primary bus ownership following the completion of the current primary bus transaction. Secondary PCI Requests: The internal arbiter supports up to nine external masters on the PCI bus using the REQ[8:1]# and REQ[0]# pins. REQ[0]#/ BR_GNT# 1 I Secondary PCI REQ[0]# or Bridge GNT#: Depending upon whether or not the internal secondary arbiter is enabled, this signal serves as either a PCI request or a PCI grant. When secondary arbiter is enabled this input represents REQ[0]#. When secondaryarbiter is disabled, this input represents the MHz PCI Bridge secondarybus master interface's PCI GNT#. GNT[8:1]# 8 Ts-O Secondary PCI Grants Supports up to nine other masters on the PCI bus. The arbiter can assert one of the nine bus grant outputs to indicate that an initiator can start a transaction on the PCI Bus following completion of the current transaction. GNT[0]#/ BR_REQ# 1 TS-O Secondary PCI GNT[0]# or Bridge REQ#: Depending upon whether or not the internal secondary arbiter is enabled, this signal serves as either a PCI request or a PCI grant. When secondary arbiter is enabled, this output represents GNT[0]#. When secondary arbiter is disabled, this output represents the MHz PCI Bridge secondary bus master interface's PCI REQ#. 14 Datasheet

15 Signal Pin Types and Descriptions Table 3. PCI Bus Interfaces (Sheet 3 of 3) Signal Width Type Description M66EN 1 I IDSEL 1 I M66EN 1 I PCIXCAP 1 I Primary 66MHz Enable: The Primary bus M66EN signal input is sampled on the trailing edge of RST#. This signal is used to determine the primary bus frequency when operating in conventional PCI mode. When sampled as 1b, Indicates that the primary bus interface will be operating in 66MHz mode. When sampled as 0b, Indicates that the MHz PCI Bridge primary bus interface will be operating in 33MHz mode. When the primary bus emerges from RST# in PCI-X mode, the PCI-X initialization pattern broadcast by the Originating Device (host bridge typically) determines the primary bus frequency. Primary ID SEL: This input serves as a high active chip select for Type 0 Configuration cycles that target the bridges configuration space registers. Secondary 66MHz Enable: M66EN, along with PCIXCAP, indicate the mode (conventional PCI vs. PCI-X), and maximum frequency capabilities of the secondary bus devices. Secondary PCI-X Capable: PCIXCAP, along with M66EN, indicate the mode (conventional PCI vs. PCI-X), and maximum frequency capabilities of the secondary bus. Pin should be connected as shown in Table 4. Total 112 Table 4. Device Mode/FrequencyCapabilityReporting M66EN PCIXCAP Convention PCI Device FrequencyCapability PCI-X Device FrequencyCapability Ground Ground 33 MHz Not capable Not connected Ground 66 MHz Not capable Ground Pull-down 33 MHz PCI-X 66 MHz Not connected Pull-down 66 MHz PCI-X 66 MHz Ground Not connected 33 MHz PCI-X 133MHz Not connected Not connected 66 MHz PCI-X 133MHz Datasheet 15

16 Signal Pin Types and Descriptions 2.2 PCI Bus Interface 64-Bit Extension This section describes the signals related to 64 bit extension bus pins. Each PCI-X bus (Primary and Secondary) is capable of operating as a 32 or a 64 bit bus. Refer to PCI Local Bus Specification 3.0. Table 5. PCI Bus Interface 64-Bit Extension (Two Interfaces) Signal Width Type Description AD[63::32] 32 Ts-I/O PCI Address/Data: Multiplexed upper address and data bus. This bus provides an additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the upper 32 bits of 64-bit write data, and during 64-bit read transactions the target drives the upper 32 bits of 64-bit read data. When not driven, AD[63:32] must be pulled up to a valid logic high level through external resistors. AD[63::32] 32 CBE#[7::4] 4 Ts-I/O Bus Command and Byte enables upper 4 bits: These signals are a multiplexed command field and byte enable field. For both reads and write transactions, the initiator will drive byte enables for the AD[63:32] data bits on C/BE7:4] during the data phases when REQ64# and ACK64# are both asserted. When not driven, C/BE#[7:4] is pulled up to a valid logic high level through external resistors. CBE#[7::4] 4 PAR64 1 Ts-I/O PCI interface upper 32-bits parity: PAR64 carries the even parity of the 36 bits of AD[63:32] and C/BE#[7:4] for both address and data phases. When not driven, PAR64 is pulled up to a valid logic high level through an external resistor. PAR64 1 REQ64# 1 Sts-I/O PCI interface request 64-bit transfer: REQ64# is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. It has the same timing as FRAME#. When the MHz PCI Bridge is the initiator, this signal is an output. When the MHz PCI Bridge is the target, this signal is an input. REQ64# 1 XX XX ACK64# 1 Sts-I/O PCI interface acknowledge 64-bit transfer: This is asserted by the target only when REQ64# is asserted by the initiator to indicate the target ability to transfer data using 64 bits. It has the same timing as DEVSEL#. ACK64# 1 Total Datasheet

17 Signal Pin Types and Descriptions 2.3 Bus Interface Clocks and Reset Table 6 describes the signals related to bus interface clocks and reset. Table6. BusInterfaceClocksandReset Signal Width Type Description CLK 1 I Primary PCI Clock Input BRGCLKO 1 O CLKO[8::0] 9 O CLKI 1 I CLKSTABLE 1 I GCLKOEN 1 I CLKOEN[3:0] 4 I (strap) Secondary Bridge Clock Output: This output is identical to the other CLKO but does not have individual disable control. This signal is recommend, since the feedback clock for the bridge should be connected to CLKI when the internal clock generation is used. Secondary PCI Clock Outputs: 33/66/100/133 MHz clock for secondary bus PCI devices. These clocks can be disabled by strapping the CLKOEN[3:0] pins during reset. Secondary PCI Clock In: This signal is connected to an output of the low skew PCI clock buffer tree. When using the internal secondary clock generation, this pin should be connected to the BRGCLKO output. Secondary Clock Stable: This input is used to enforce the T rst-clk time as defined in the PCI Local Bus Specification. After this signal is asserted, the bridge will wait 100µS before de-asserting the secondary PCI reset. When using the internal secondary clock generation, this pin should be tied high. Secondary Global Clock Output Enable: This pin should be pulled high to enable the secondary clock outputs. When de-asserted (0b), all secondary clock outputs (CLKO[8::0] and BRGCLKO) will asynchronously tri-state. If an external clock source is used on the secondary interface, this signal should be pulled-low. Secondary Clock Enable These pins control the reset value of bits 8:0. The binary encoding on these pins indicates the number of secondary clock enabled. Datasheet 17

18 Signal Pin Types and Descriptions Table 6. Bus Interface Clocks and Reset Signal Width Type Description RST# 1 I Primary PCI Reset RST# 1 O Secondary PCI Reset: The MHz PCI Bridge asserts RST# to reset devices that reside on its secondary PCI bus. The MHz PCI Bridge asserts RST# due to one of the following events: RST# assertion Setting the Secondary Bus Reset bit (bit 6) in the Bridge Control Register. If PME# support from the D3 cold is required, then a weak pull-down should be placed on the RST# line. This, in conjunction with PME# which is routed around the bridge, enables ACPI S3 (or higher) PME# operation for downstream PCI-PM compliant PCI agents. Total JTAG Interface Table 7 describes the signals related to the JTAG interface. Table 7. JTAG (Sheet 1 of 2) Signal Width Type Description TDI 1 I TDO 1 O TMS 1 I TCK 1 I TRST# 1 I SCAN_EN 1 I Test Data In: TDI is the serial input through which JTAG instructions and test data enter the JTAG interface. TDI is sampled on the rising edge of TCK. IfTDIisnotdriven,itproducesthesameresultsasifTDIwere driven high. Test Data Out: TDO is the serial output through which test instructions and data from the test logic leave MHz PCI Bridge. Test Mode Select: TMS causes state transitions in the test access port (TAP) controller. If TMS is not driven, it produces the same results as if TMS were driven high. Test Clock: TCK is the clock controlling the JTAG logic. For systems that do not implement JTAG, this input should be pulled low. Test Reset: When TRST# is asserted (driven low), the TAP controller is asynchronously forced to enter a reset state, which in turn asynchronously initializes other test logic. TRST# must be pulled low to GND for normal operation. SCAN Mode Select: The SCAN_EN pin toggles between the shift operation and the capture operation in the scan testing mode. It is used for scan chain testing of the device only. During normal operation, this input should be tied low. 18 Datasheet

19 Signal Pin Types and Descriptions Table 7. JTAG (Sheet 2 of 2) Signal Width Type Description TMODE[3:0] 4 I MT#[1:0] 2 I Test Mode Select: These four pins are used to internally test MHz PCI Bridge at the time of manufacture. TMODE3 must be tied to V SS (logic 0) for normal operation. TMODE[2:0] all three pins must be tied to (preferred) or all must be tied to V CC. Normal Operation => 0000 or Manufacture Test pins. These two pins must be pulled high for normal operation. Total Serial EEROM Interface Table 8 describes the signals related to the Serial EEROM interface. Table 8. Serial EEROM Interface Signal Width Type Description SR_CLK 1 Ts-O SR_DI 1 Ts-O SR_DO 1 I SR_CS 1 Ts-O Serial EEROM Clock: Clock output. This pin is connected to the EEROM clock input Serial EEROM Data In: Serial data stream output that is connected to the EEROM DI input. Serial EEROM Data out: Serial data stream input that is connected to the EEROMs DO output Serial EEROM chip select: The MHz PCI Bridge drives this signal high to enable the serial ROM for a read or write cycle. Total 4 Datasheet 19

20 Signal Pin Types and Descriptions 2.6 Compact PCI Hot Swap Interface Table 9 describes the signals related to the cpci PCS Hot Swap interface. Table 9. Compact PCI Hot Swap Signal Width Type Description HENUM# 1 Od-O HLSTAT 1 I HLED_OUT 1 O HSM 1 I HFREQ[1:0] 2 I Primary Bus Compact PCI Hot Swap Event: This is conditionally asserted to notify the system host that either a board has been freshly inserted or is about to be extracted. This signal informs the system host that the configuration of the system has changed. The system host then performs any necessary maintenance, such as installing or quiescing a device driver. Compact PCI Hot Swap Latch Status: This is an input to the bridge, indicating the state of the ejector switch. 0= Indicates the ejector switch is closed 1=Indicates the ejector switch is open If Compact PCI Hot Swap is not supported, this signal must be tied low. LED Output: The MHz PCI Bridge outputs a logic one to illuminate the Hot Swap LED. Hot swap Startup Mode: This pin is sampled at the rising edge of RST#. If 0b, The MHz PCI Bridge retries any Type 0 Configuration cycles addressed to it until its serial ROM preload has completed. If 1b, the MHz PCI Bridge ignores (causes a master abort) any Type 0 configuration cycles addressed to it until its serial ROM preload has completed. This pin should be tied low for non-hot Swap systems. This pins are reserved for determining Primary Bus frequency and mode during a PCI-X hot swap event and are valid only when HSM = 1. The bus frequency and mode are described below: 00 => PCI Mode, 33 or 66 MHz. Use M66EN to determine frequency 01 => PCI-X Mode, 66 MHz 10 => PCI-X Mode, 100 MHz 11 => PCI-X Mode, 133 MHz These pins should be tied low for non-hot Swap systems. Total 6 20 Datasheet

21 Signal Pin Types and Descriptions 2.7 Hardware Straps Table 10 describes the signals related to the hardware straps. These are sampled during and on the trailing edge of RST# to set the mode of operation of the device. Table 10. Hardware Straps Signal Width Type Description ARB_DISABLE/ ARB_LOCK 1 I Secondary Arbiter Disable / Arbiter Lock: If sampled as 1b at the trailing edge of RST#, the internal secondary bus arbiter is disabled. In this event GNT#[0) is used for the bridge s secondary bus request output, and REQ#[0] is used for the bridge s secondary bus grant input. If a logic low is sampled at the trailing edge of RST#, the bridge s internal secondary arbiter is enabled for use. This pin must have either a pull-up resistor to V DD, or a pull down resistor to Vss. It must no be left floating. If sampled as 1b after the trailing edge of RST#, the bridge s internal secondary bus arbiter will lock and only provide the grant to itself. MAX100 1 OPAQUE_EN 1 IDSEL_MASK 1 DEV_64BIT# 1 Total 5 I (strap) I (strap) I (strap) I (strap) Secondary Bus Maximum Frequency: This trap bits, sampled on the trailing edge of RST#, provides the MHz PCI Bridge with necessary system specific secondary bus loading information that is required to correctly establish the maximum secondary bus clock frequency when operating in PCI-X mode. When asserted the secondary bus frequency will be limited to a maximum of 100MHz. This pin must have either pull-up resistors to V DD, or pull down resistors to Vss. It must not be left floating. Opaque Memory Space Enable: If sampled high at the trailing edge of RST#, the MHz PCI Bridge will set bit 11 in the offset 46H:VCR2 the MHz PCI Bridge Control Register 2. This will enable the Opaque Memory Base/Limit registers. This establishes a private memory space for secondary bus usage, independent of the MHz PCI Bridge downstream forwarding configuration. IDSEL Masking Enable. If sampled high at the trailing edge of RST#, the MHz PCI Bridge will change the default value of the Offset 5CH: Secondary IDSEL Select Register SISR. This will hide devices from the host. This signal is sampled on the trailing edge of RST# and sets bit 16 int the PCI-X Bridge Status Register. This strap is to support system management software and does not change the behavior to the bridge. Datasheet 21

22 Signal Pin Types and Descriptions 2.8 Miscellaneous Signals Table 11 describes the signals related to the special features of the MHz PCI Bridge. Table 11. Miscellaneous Signals (Sheet 1 of 2) Signal Width Type Description QE 1 O NT_MASK# 1 I TRISTATE 1 I Queues Empty: This output indicates the state of the MHz PCI Bridge internal request and data queues. When at a logic high level, this signal indicate that the MHz PCI Bridge internal queues are completely empty. This state of this output is valid only when the NT_MASK# pin is asserted. New Transaction Mask: When this pin is sampled asserted (logic low level), the MHz PCI Bridge does not enqueue any new transactions, except PCI configuration cycles targeting its configuration registers. Transactions enqueued at the time that this signal is sampled asserted are allowed to complete normally. Applications could, for example, use this pin and the QE pin to implement external hardware that flushes the MHz PCI Bridge request and data queues. Secondary Bus Tri-State Enable: All Secondary bus outputs (except BRGCLKO) are asynchronously tri-stated when this signal is asserted(1b). In cpci systems this input can be used to support Redundant System Slot (RSS) implementations. In non-rss platforms, this pin should be tied directly to ground. GPIO[7:0] 8 I/O General Purpose I/O. VIO 1 I VIO 1 I R_REF 1 I NC 1 O Primary Bus PCI Universal I/O Voltage Reference: This signal must be tied to either 3.3V or 5V, corresponding to the signaling environment of the primary PCI bus as described in the PCI Local Bus Specification. When any device on the primary bus uses 5V signaling levels, the system must connect VIO to 5V. VIO is connected to 3.3V by the system only when all the devices on the primary bus use 3.3V signaling levels. Secondary Bus PCI Universal I/O Voltage Reference: This signal must be tied to either 3.3V or 5V, corresponding to the signaling environment of the secondary PCI bus as described in the PCI Local Bus Specification. When any device on the secondary bus uses 5V signaling levels, the system must connect VIO to 5V. VIO is connected to 3.3V by the system only when all the devices on the secondary bus use 3.3V signaling levels. R_REF: This pin is connected to an external (board-level) precision pull-down resistor. The resistor is used as a reference for setting the I/O buffers output drive AC and DC parametrics, enabling the output buffers to meet the PCI/PCI-X parametric specifications. R=30Ω No Connect: This output should be left floating. 22 Datasheet

23 Signal Pin Types and Descriptions Table 11. Miscellaneous Signals (Sheet 2 of 2) Signal Width Type Description RSRV[1:0] 2 I Total 17 Reserved: The reserved inputs should be pulled to a valid logic level. 2.9 Power and Ground Signals Table 12 describes the power and ground-related signals. Table 12. Power and Ground Signals Signal Type Description A PWR Secondary bus clock PLL Supply Voltage A PWR Primary bus clock PLL Supply Voltage PWR 1.3V Supply Voltage P PWR 3.3V Supply Voltage VIO PWR Primary Reference Supply Voltage VIO PWR Secondary Reference Supply Voltage GND Ground 2.10 Ball Table Mappings The pinout for the MHz PCI Bridge PCI-X to PCI-X Bridge is described in the following tables. Table 13 lists the pinout entries in ballpad number order. Table 14 lists the entries alphabetically in signal order. Table 13. Pinout Ballpad Number Order (Sheet 1 of 7) Ball Number Signal Ball Number Signal A1 A13 CBE0# A2 ACK64# A14 A3 AD56 A15 CBE3# A4 AD60 A16 IRDY# A5 CBE4# A17 FRAME# A6 A18 A7 CBE7# A19 AD04 A8 P A20 AD07 A9 PAR64 A21 A A10 A22 P A11 A23 A12 P B1 AD43 Datasheet 23

24 Signal Pin Types and Descriptions Table 13. Pinout Ballpad Number Order (Sheet 2 of 7) Ball Number Signal Ball Number Signal B2 C17 AD09 B3 AD54 C18 PAR B4 SERR# C19 AD10 B5 AD49 C20 GNT# B6 AD50 C21 B7 AD52 C22 TDI B8 AD55 C23 TRST# B9 AD57 D1 CLKOEN2 B10 AD59 D2 AD47 B11 AD63 D3 QE B12 CBE6# D4 B13 AD00 D5 P B14 AD02 D6 AD51 B15 TRDY# D7 P B16 AD05 D8 B17 AD08 D9 B18 CBE1# D10 AD62 B19 IDSEL D11 B20 AD15 D12 B21 REQ# D13 B22 D14 CBE2# B23 TDO D15 C1 SCAN_EN D16 C2 AD48 D17 P C3 D18 AD11 C4 STOP# D19 P C5 P D20 C6 CLKOEN3 D21 DEVSEL# C7 AD53 D22 TMS C8 PERR# D23 AD22 C9 AD58 E1 AD38 C10 AD61 E2 CLKOEN1 C11 CBE5# E3 AD45 C12 REQ64# E4 P C13 AD01 E5 R_REF C14 MT0# E6 C15 AD03 E7 HLED_OUT C16 AD06 E8 HLSTAT 24 Datasheet

25 Signal Pin Types and Descriptions Table 13. Pinout Ballpad Number Order (Sheet 3 of 7) Ball Number Signal Ball Number Signal E9 HENUM# F15 E10 F16 E11 TRISTATE F17 E12 HFREQ0 F18 E13 HFREQ1 F19 E14 F20 AD13 E15 NT_MASK# F21 TCK E16 GPIO0 F22 AD12 E17 GPIO1 F23 E18 F1 E19 GPIO2 F10 E20 P F14 E21 CLK G1 AD36 E22 RST# G2 CLKOEN0 E23 AD24 G3 AD41 F1 G4 P F2 AD42 G5 HSM F3 AD44 G6 F4 AD46 G18 F5 G19 F6 G20 P F7 G21 AD16 F8 G22 AD14 F9 G23 AD26 F10 H1 AD35 F14 H3 AD40 F15 H4 F16 H5 M66EN F17 H6 F18 H18 F19 H19 F20 AD13 H2 AD39 F21 TCK H20 F22 AD12 H21 AD18 F23 H22 AD17 F1 H23 VIO F10 J1 AD33 F14 J2 AD34 Datasheet 25

26 Signal Pin Types and Descriptions Table 13. Pinout Ballpad Number Order (Sheet 4 of 7) Ball Number Signal Ball Number Signal J3 AD37 L20 J4 L21 AD28 J5 SR_CLK L22 AD27 J6 L23 J18 CLKO0 M1 P J19 CLKO2 M2 AD39 J20 M3 AD38 J21 AD20 M4 J22 AD19 M5 SR_DO J23 AD31 M10 K1 M11 K2 AD34 M12 K3 AD33 M13 K4 AD32 M14 K5 M19 CLKO5 K6 M20 K10 M21 AD30 K11 M22 AD29 K12 M23 AD27 K13 N1 K14 N2 AD41 K18 CLKO1 N3 AD40 K19 CLKO4 N4 K20 AD25 N5 SR_DI K21 AD23 N10 K22 AD21 N11 K23 N12 L1 AD32 N13 L2 AD36 N14 L3 AD35 N19 CLKO6 L4 N20 L5 SR_CS N21 AD30 L10 N22 AD31 L11 N23 AD25 L12 P1 L13 P2 AD47 L14 P3 AD45 L19 CLKO3 P4 AD43 26 Datasheet

27 Signal Pin Types and Descriptions Table 13. Pinout Ballpad Number Order (Sheet 5 of 7) Ball Number Signal Ball Number Signal P5 U2 AD53 P6 U3 AD52 P10 U4 P P11 U5 GNT6# P12 U6 P13 U18 P14 U19 GCLKOEN P18 BRGCLKO U20 P P19 CLKO7 U21 AD18 P20 AD26 U22 AD19 P21 AD28 U23 RST# P22 AD29 V1 P23 V2 AD55 R1 AD37 V3 MAX100 R2 AD49 V4 AD54 R3 AD48 V5 R4 V6 R5 GNT7# V7 R6 V8 R18 M66EN V9 R19 CLKO8 V10 R20 V14 R21 AD22 V15 GPIO3 R22 AD24 V16 GPIO5 R23 PCIXCAP V17 GNT8# T1 VIO V18 T2 AD51 V19 T3 AD50 V20 AD14 T4 V21 AD16 T5 REQ7# V22 AD17 T6 V23 T18 W1 AD44 T19 W2 REQ2# T20 W3 CLKSTABLE T21 ARB_DISABLE W4 P T22 AD20 W5 REQ6# T23 AD23 W6 U1 AD42 W7 Datasheet 27

28 Signal Pin Types and Descriptions Table 13. Pinout Ballpad Number Order (Sheet 6 of 7) Ball Number Signal Ball Number Signal W8 Y23 TMODE3 W9 AA1 NC W10 AA2 REQ1# W11 AA3 W12 AA4 TMODE2 W13 AA5 AD58 W14 AA6 AD59 W15 REQ8# AA7 AD61 W16 GPIO4 AA8 ACK64# W17 GPIO6 AA9 AD00 W18 GPIO7 AA10 PAR64 W19 AA11 CBE5# W20 P AA12 AD06 W21 AD15 AA13 AD07 W22 TMODE0 AA14 FRAME# W23 AD21 AA15 CBE3# Y1 AD46 AA16 AD10 Y2 GNT2# AA17 PAR Y3 AD56 AA18 OPAQUE_EN Y4 AA19 GNT0# Y5 P AA20 AD13 Y6 AD57 AA21 Y7 P AA22 RSRV0 Y8 AA23 REQ0# Y9 AB1 GNT1# Y10 CBE7# AB2 Y11 AB3 REQ3# Y12 AB4 GNT4# Y13 AB5 REQ4# Y14 TRDY# AB6 AD60 Y15 AB7 AD62 Y16 AB8 AD63 Y17 P AB9 AD01 Y18 AD11 AB10 CBE6# Y19 P AB11 AD04 Y20 AB12 CBE0# Y21 TMODE1 AB13 REQ64# Y22 DEV_64BIT# AB14 CBE2# 28 Datasheet

29 Signal Pin Types and Descriptions Table 13. Pinout Ballpad Number Order (Sheet 7 of 7) Ball Number Signal Ball Number Signal AB15 AD09 AC8 CBE4# AB16 CBE1# AC9 AD02 AB17 PERR# AC10 AB18 AD12 AC11 AD03 AB19 SERR# AC12 P AB20 STOP# AC13 AB21 A AC14 AB22 AC15 AD05 AB23 CLKI AC16 P AC1 AC17 AD08 AC2 P AC18 AC3 REQ5# AC19 IRDY# AC4 GNT5# AC20 MT1# AC5 GNT3# AC21 DEVSEL# AC6 AC22 IDSEL_MASK AC7 RSRV1 AC23 See Table14onpage30for a list of pinout entries in signal order. Datasheet 29

30 Signal Pin Types and Descriptions Table 14 lists the MHz PCI Bridge pinout entries alphabetically in signal order. Table 14. Pinout Signal Order (Sheet 1 of 6) Signal Ball Number Signal Ball Number DEV_64BIT# Y22 AD16 G21 GPIO0 E16 AD17 H22 GPIO1 E17 AD18 H21 GPIO2 E19 AD19 J22 GPIO3 V15 AD20 J21 GPIO4 W16 AD21 K22 GPIO5 V16 AD22 D23 GPIO6 W17 AD23 K21 GPIO7 W18 AD24 E23 HENUM# E9 AD25 K20 HFREQ0 E12 AD26 G23 HFREQ1 E13 AD27 L22 HLED_OUT E7 AD28 L21 HLSTAT E8 AD29 M22 HSM G5 AD30 M21 IDSEL_MASK AC22 AD31 J23 NC AA1 AD32 L1 NT_MASK# E15 AD33 J1 OPAQUE_EN AA18 AD34 J2 ACK64# A2 AD35 H1 AD00 B13 AD36 G1 AD01 C13 AD37 J3 AD02 B14 AD38 E1 AD03 C15 AD39 H2 AD04 A19 AD40 H3 AD05 B16 AD41 G3 AD06 C16 AD42 F2 AD07 A20 AD43 B1 AD08 B17 AD44 F3 AD09 C17 AD45 E3 AD10 C19 AD46 F4 AD11 D18 AD47 D2 AD12 F22 AD48 C2 AD13 F20 AD49 B5 AD14 G22 AD50 B6 AD15 B20 AD51 D6 30 Datasheet

31 Signal Pin Types and Descriptions Table 14. Pinout Signal Order (Sheet 2 of 6) Signal Ball Number Signal Ball Number AD52 B7 VIO H23 AD53 C7 QE D3 AD54 B3 R_REF E5 AD55 B8 RSRV0 AA22 AD56 A3 RSRV1 AC7 AD57 B9 ACK64# AA8 AD58 C9 AD00 AA9 AD59 B10 AD01 AB9 AD60 A4 AD02 AC9 AD61 C10 AD03 AC11 AD62 D10 AD04 AB11 AD63 B11 AD05 AC15 CBE0# A13 AD06 AA12 CBE1# B18 AD07 AA13 CBE2# D14 AD08 AC17 CBE3# A15 AD09 AB15 CBE4# A5 AD10 AA16 CBE5# C11 AD11 Y18 CBE6# B12 AD12 AB18 CBE7# A7 AD13 AA20 CLK E21 AD14 V20 DEVSEL# D21 AD15 W21 FRAME# A17 AD16 V21 GNT# C20 AD17 V22 IDSEL B19 AD18 U21 IRDY# A16 AD19 U22 MT0# C14 AD20 T22 M66EN H5 AD21 W23 PAR C18 AD22 R21 PAR64 A9 AD23 T23 PERR# C8 AD24 R22 REQ# B21 AD25 N23 REQ64# C12 AD26 P20 RST# E22 AD27 M23 SERR# B4 AD28 P21 STOP# C4 AD29 P22 TRDY# B15 AD30 N21 A A21 AD31 N22 Datasheet 31

32 Signal Pin Types and Descriptions Table 14. Pinout Signal Order (Sheet 3 of 6) Signal Ball Number Signal Ball Number AD32 K4 CBE4# AC8 AD33 K3 CBE5# AA11 AD34 K2 CBE6# AB10 AD35 L3 CBE7# Y10 AD36 L2 CLKI AB23 AD37 R1 CLKO0 J18 AD38 M3 CLKO1 K18 AD39 M2 CLKO2 J19 AD40 N3 CLKO3 L19 AD41 N2 CLKO4 K19 AD42 U1 CLKO5 M19 AD43 P4 CLKO6 N19 AD44 W1 CLKO7 P19 AD45 P3 CLKO8 R19 AD46 Y1 CLKOEN0 G2 AD47 P2 CLKOEN1 E2 AD48 R3 CLKOEN2 D1 AD49 R2 CLKOEN3 C6 AD50 T3 CLKSTABLE W3 AD51 T2 DEVSEL# AC21 AD52 U3 FRAME# AA14 AD53 U2 GCLKOEN U19 AD54 V4 GNT0# AA19 AD55 V2 GNT1# AB1 AD56 Y3 GNT2# Y2 AD57 Y6 GNT3# AC5 AD58 AA5 GNT4# AB4 AD59 AA6 GNT5# AC4 AD60 AB6 GNT6# U5 AD61 AA7 GNT7# R5 AD62 AB7 GNT8# V17 AD63 AB8 IRDY# AC19 ARB_DISABLE T21 MT1# AC20 BRGCLKO P18 M66EN R18 CBE0# AB12 MAX100 V3 CBE1# AB16 PAR AA17 CBE2# AB14 PAR64 AA10 CBE3# AA15 PCIXCAP R23 32 Datasheet

33 Signal Pin Types and Descriptions Table 14. Pinout Signal Order (Sheet 4 of 6) Signal Ball Number Signal Ball Number PERR# AB17 F10 REQ0# AA23 F15 REQ1# AA2 F17 REQ2# W2 G18 REQ3# AB3 H6 REQ4# AB5 H19 REQ5# AC3 J4 REQ6# W5 J20 REQ64# AB13 K6 REQ7# T5 L4 REQ8# W15 L20 RST# U23 N4 SERR# AB19 N20 STOP# AB20 R4 TRDY# Y14 R20 TRISTATE E11 R6 A AB21 T18 VIO T1 T19 SCAN_EN C1 U6 SR_CLK J5 V7 SR_CS L5 V9 SR_DI N5 V14 SR_DO M5 V18 TCK F21 W13 TDI C22 Y9 TDO B23 Y11 TMODE0 W22 Y13 TMODE1 Y21 Y15 TMODE2 AA4 P A8 TMODE3 Y23 P A12 TMS D22 P A22 TRST# C23 P AC2 D9 P AC12 D11 P AC16 D13 P C5 D15 P D5 F6 P D7 F8 P D17 Datasheet 33

34 Signal Pin Types and Descriptions Table 14. Pinout Signal Order (Sheet 5 of 6) Signal Ball Number Signal Ball Number P D19 F14 P E4 F16 P E20 F18 P G4 F19 P G20 F23 P M1 G6 P U4 G19 P U20 H4 P W4 H18 P W20 H20 P Y5 J6 P Y7 K1 P Y17 K5 P Y19 K10 A1 K11 A6 K12 A10 K13 A11 K14 A14 K23 A18 L10 A23 L11 B2 L12 B22 L13 C3 L14 C21 L23 D4 M4 D8 M10 D12 M11 D16 M12 D20 M13 E6 M14 E10 M20 E14 N1 E18 N10 F1 N11 F5 N12 F7 N13 F9 N14 34 Datasheet

35 Signal Pin Types and Descriptions Table 14. Pinout Signal Order (Sheet 6 of 6) Signal Ball Number Signal Ball Number P1 W9 P5 W10 P6 W11 P10 W12 P11 W14 P12 W19 P13 Y4 P14 Y8 P23 Y12 T20 Y16 T4 Y20 T6 AA3 U18 AA21 V1 AB2 V5 AB22 V6 AC1 V8 AC6 V10 AC10 V19 AC13 V23 AC14 W6 AC18 W7 AC23 W8 Datasheet 35

36 Electrical Specifications Electrical Specifications 3 This chapter describes the electrical specifications for the MHz PCI Bridge. 3.1 Absolute Maximum Ratings This section provides the Absolute Maximum ratings for the MHz PCI Bridge. Do not exceed the parameters listed in Table 15. Operations at the Absolute Maximum ratings are not guaranteed. Caution: Table 15. Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. Absolute Maximum Ratings Parameter Maximum Rating Storage Temperature Case Temperature Under Bias Supply Voltage P wrt. Supply Voltage VIO;VIO -55 ο C to +125 ο C 0 o Cto+70 o C 0.5V to +4.1V 0.5to5.5V Supply Voltage wrt. 0.5V to +2.3V (Note 1) Voltage on Any pin (non 5V tolerant) wrt. Voltage on Any pin (5V tolerant) wrt. 0.5V to V CC P + 0.5V 0.5V to 5.5V NOTE: 1-2.3V for fuse programming only. Normally 2.1V. 3.2 Operating Conditions Table 16 shows minimum and maximum voltage, frequency, and temperature specifications for the MHz PCI Bridge. Caution: Table 16. Operation beyond the specified Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability. Operating Conditions Symbol Parameter Min Max Units Notes P 3.3V Supply Voltage V VIO; VIO Reference Supply Voltage V See Section V Supply Voltage V Note 2 36 Datasheet

37 Electrical Specifications Table 16. Operating Conditions Symbol Parameter Min Max Units Notes A PLL Supply Voltage V A PLL Supply Voltage V F CLK Input Clock Frequency MHz Note 1 F s_clk Input Clock Frequency MHz Note 1 T C Case Temperature Under Bias 0 70 C NOTES: 1- Any input clock frequency less then 25MHz use PLL in bypass mode, PLL output not guaranteed. 2- is increased to 2.3V during fuse programming 3.3 Power Supplyand Thermal Requirements Table 17 shows the power supply and thermal requirements for the MHz PCI Bridge. Table 17. Power Supplyand Thermal Requirements Voltage Typical Maximum Units Notes 3.3 V 2.5 Watts Note V 0.70 Watts Note 1 Operational (Thermal Power) 1.75 Watts Notes 2,3 NOTES: 1- For Sizing 3.3V and 1.3V Supplies (instantaneous maximums) 2-3.3V and 1.3V in operational modes. For thermal calculations (sustained maximums). 3 -Tj=(80 C)+(1.75W)*(18.5 C/W) = 112 C 3.4 Power SupplySpecial Considerations If either VIO or VIO is not connected to the same power supply as Vccp, the user must perform one of the following steps: Ensure that the VIO or VIO power comes up before or simultaneously with Vccp and ensure that the VIO or VIO power goes down after or simultaneously with Vccp. Install a Shottky diode, as shown in Figure 4, between P and the VIO pin/pins (as appropriate). The diode should be sized appropriately for the system s power environment. (Recommended) Connect a 25Ohm current limit resistor in series with the VIO and VIO supply. VIO and VIO can never be at a lower voltage than P except in the case of a 25Ohm current limiting resistor in series with the VIO and VIO supply. Datasheet 37

38 Electrical Specifications Figure 4. Installing a ShottkyDiode P VIO SHOTTKY DIODE P VIO vz B A and A Pin Requirements To reduce clock skew and jitter, the A and A balls for the Phase Lock Loop (PLL) circuit are isolated on the package. The lowpass filter, as shown in Figure 5, reduces noise induced clock jitter and its effects on timing relationships in system designs. The 4.7 µf capacitor must be (low ESR solid tantalum), the 0.01 µf capacitor must be of the type X7R and the node connecting V CCPLL must be as short as possible. The V SS pins should be connected to the board ground plane immediately below capacitor. 38 Datasheet

39 Electrical Specifications Figure 5. A and A Lowpass Filter (Board Plane) A Ball + 4.7µF 0.01µF B Targeted DC Specifications 3.7 IO Types Table 18 lists the MHz PCI Bridge IO Types. These types are referred to in the subsections below. Table 18. IO Types Name Type PCI PCIX PCI-X cmos PCI only PCIX Only Both PCI and PCIX Non PCI-X compliant IO DC Characteristics The DC characteristics for each pin include input sense levels and output drive levels and currents. These parameters can be used to determine maximum DC loading, and also to determine maximum transition times for a given load. The DC Operating Conditions for the High- and Low-Strength Input, Output, and I/O pins are shown in Table 19. Table 19. DC Characteristics (Sheet 1 of 2) Symbol Parameter Min Max Units Notes V IL1 Input Low Voltage (cmos) V Note 2 V IH1 Input High Voltage (cmos) 2.0 P V V IL2 Input Low Voltage (PCI-X) P V V IH2 Input High Voltage (PCI-X/ PCI) 0.5P P V Note 1 Datasheet 39

40 Electrical Specifications Table 19. DC Characteristics (Sheet 2 of 2) Symbol Parameter Min Max Units Notes V IL3 Input Low Voltage (PCI) P V V OL1 Output Low Voltage (Misc) 0.4 V I OL = 4mA V OH1 Output High Voltage (Misc) 2.4 V I OH =-2mA V OL3 Output Low Voltage (PCI-X) 0.1P V I OL = 1500uA (Note 1) V OH3 Output HIGH Voltage (PCI-X) 0.9P V I OH = -500uA (Note 1) C IN Input pin Capacitance 8 pf C CLK Clock pin Capacitance 5 8 pf L PIN Pin Inductance 15 nh NOTES: 1 - Pads are 5V Tolerant (not operational). 2 - CMOS IOs include all IOs that are not PCI or PCIX-compliant IOs I cc Characteristics Table 20 describes the I CC characteristics. Table 20. Icc Characteristics (Sheet 1 of 2) Symbol Parameter Min Max Units Notes I LI1 I LI2 Input Leakage Current for each signal except TCK, TMS, TRST#, TDI Input Leakage Current for TCK, TMS, TRST#, TDI µa µa I CC33 Active (Power Supply) I CC13 Active (Power Supply) I CC13 Fuse Program (Power Supply) Power Supply Current 0.70 A Power Supply Current 0.65 A Power Supply Current.1.1 A 40 Datasheet

41 Electrical Specifications Table 20. Icc Characteristics (Sheet 2 of 2) Symbol Parameter Min Max Units Notes I CC33 Active (Power Modes) Reset Mode Hi-Z Mode A I CC13 Active (Power Modes) Reset Mode Hi-Z Mode A I CC Active (Power Supply) value is provided for selecting your system s power supply. This is measured using one of the worst case instruction mixes with P = 3.6V, = 1.365V, and ambient temperature = 55 C. Input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 3.8 Targeted AC Specifications The AC characteristics for each pin are described in the following sections Input Clock Timings This section describes PCI input clock timings for the MHz PCI Bridge. Table 21 summarizes the minimum and maximum clock timings at 133, 100, 66, and 33 MHz. Table 21. Input Clock Timings Symbol Parameter PCI-X 133 PCI-X 100 PCI-X 66 PCI 66 PCI 33 Min Max Min Max Min Max Min Max Min Max Units Notes T F1 T C1 T CH1 TCL1 TSR1 PCI clock Frequency PCI clock Cycle Time PCI clock High Time PCI clock Low Time PCI clock Slew Rate MHz Note ns ns ns V/ns Note 2 NOTES: 1- In PCI-33 clock can vary down to DC. Any input below 25MHZ must be in PLL bypass mode. 2 -This slew rate as defined in PCI, PCIX specifications The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter PCI Interface Signal Timings This section shows the PCI interface signal timings for the MHz PCI Bridge. Table 22 summarizes the minimum and maximum signal timings at 133, 100, 66, and 33 MHz. Datasheet 41

42 Electrical Specifications Table 22. PCI Signal Timings (Sheet 1 of 2) Symbol Parameter PCI-X 133 PCI-X 100 PCI-X 66 PCI 66 PCI 33 Units Notes Min Max Min Max Min Max Min Max T OV1 Clock to Output Valid Delay for bused signals ns Notes 1,2,6,7 T OV2 Clock to Output Valid Delay for point to point signals ns Notes 1,2,6,7 TOF Clock to Output Float Delay ns TIS1 Input Setup to clock for bused signals ns Notes 1,3 TIS2 Input Setup to clock for point to point signals , 12 ns Notes 1,3 T IH1 Input Hold time from clock ns Notes 1,3 T RST T RF T IS3 T IH2 T IS4 Reset Active Time Reset Active to output float delay REQ64# to Reset setup time Reset to REQ64# hold time PCI-X initialization pattern to Reset setup time ms ns clocks ns Notes 1,3 Notes 1, clocks 1,3 42 Datasheet