Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface

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1 Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface Steven Strell Senior Applications Engineer, Altera Corporation (408) Abstract Today s high-speed, high pin count FPGA devices demand skilled printed circuit board design practices. FPGA designers must consider final board design when creating I/O assignments. Making accurate assignments and intelligent transfers between FPGA designers and board designers is a daunting task for FPGA devices with more than 1000 pins. The reprogrammability inherent in FPGA design creates a continually evolving product with increased complexity. Altera Quartus II FPGA design software features built-in I/O assignment capabilities and checks that assist development. Quartus II software and Mentor Graphics' I/O Designer software both support the import and export of I/O assignments through the industry standard FPGA Xchange format. By tightly integrating Quartus II advanced FPGA design environment, I/O Designer s schematic symbol creation capabilities, and DxDesigner s schematic capture toolset, a complete design loop is created that increases engineer productivity and decreases board integration time. 2 FPGA to Board Design Flow Issues FPGA components are becoming much more complex. Devices with over a thousand pins make I/O management a difficult task. With an increasing pin count, FPGA devices run at faster speeds and require multiple clean power rails to achieve normal operation. With more complex FPGA devices being used, greater care must be taken in board design. Boards integrating FPGA devices require more simulation time, stricter routing constraints, and proper line termination to operate correctly. In a typical design flow using FPGA devices, FPGA and board designs often take place concurrently between two different engineers or engineering teams (See Figure 1). FPGA design engineers spend most of their time using FPGA design software, such as Quartus II software, designing, simulating, and testing logic, as well as configuring and programming test devices, which are typically on a development board. Board design engineers are responsible for creating schematic symbols for components and integrating these symbols into circuit schematics. From the circuit schematics, a board layout is created and routed. Board design engineers are also responsible for creating a bill of materials for populating the board with components. Once the board is fabricated and assembled, board designers bring up the board and test for proper operation. These parallel design flows work perfectly for both types of engineers, but it is possible there is little or no interaction between the two. Working independently, I/O assignment errors can be transferred back and forth without either engineering group knowing. This typically happens if FPGA pin assignments need to change based on a logic design change or if board routing requires adjustment to accommodate new components or improve layout. If a design change occurs on either side, it must be transferred accurately to the other side. If this fails, FPGA pins could be attached to wrong signals on the board, affecting the functionality of the system or causing damage to the device if the error involves power rails. Transferring I/O assignments between a FPGA and a board design is complicated and leads to further error. If an I/O change is made in a FPGA design, the change must be reflected in the board design by a change to the circuit schematic symbol for the device. 1

2 date. Also lacking are some desired features previously mentioned, including a process of automatically updating information and maintaining revision control. The best solution is direct linking between the design processes. If I/O assignments created by a FPGA engineer could be immediately reflected in the circuit schematic symbols created by a board design engineer and vice versa, the link would be established. This type of link is possible by using I/O assignment transfers through files generated by the tools each engineer is using. File types presented are the pin-out file, or.pin, and the FPGA Xchange file, or.fx. By creating a link using these files, it is simple to generate and update files whenever needed without the possibility of introducing errors or typos through a manual process, as with a spreadsheet. Figure 1. The Bridge Between the FPGA and Board Design Flows 3 Solutions There are several ways to solve these problems. Close collaboration between engineers, resulting in a better understanding of each other's design flow is the best solution. When both understand the entire design process completely, communicating changes is easier. Other solutions utilize electronic means of assignment protection and transfer. For example, source control disallows either designer to make changes (or mistakes) without the other knowing. A design repository with revision control requiring checking in and checking out of a single copy of the project serves as protection. Some tools lock I/O assignments preventing changes and requiring communication between the two parties to understand possible changes. A better solution is automatic updating and change notification between engineers not requiring manual design changes by either. A simple and very common solution is using a spreadsheet for transferring and tracking I/O assignments. Spreadsheet rows correspond to individual pins on the FPGA device. Columns are used to supply information about each pin such as voltage, signal direction, or I/O bank. Signals assigned to each pin are listed in columns. Using a spreadsheet provides an easy way to read and interpret I/O assignment information. However, tracking and updating information on a spreadsheet can cause problems. A spreadsheet is manually edited, making it prone to error. Unless a spreadsheet has an up-to-date timestamp, it is possible for information to be out of 4 I/O Assignment Transfer File Types The two file types store information about device pins similarly to a spreadsheet, but each file type has unique properties. The.pin file is an Altera standard file type generated by the Fitter in Quartus II. It is a list of all the pins in the selected device whether or not a signal has been assigned to a particular pin. Each row of the file represents a device pin, while each column specifies information about that pin. The.pin file transfers standard information about each pin including any assigned signal name, signal direction, I/O standard, voltage, and assigned I/O bank. The.pin file is an output file only. Quartus II generates this file but cannot import the assignment information. A.fx file is also used in the automated I/O assignment transfer process. The.fx file is an industry standard file type defined by Mentor Graphics specifically for I/O assignment transfer. Quartus II EDA Netlist Writer generates a.fx file during design compilation. When Quartus II generates the file, only pins that have signals assigned to them manually through Quartus II Assignment Editor and Pin Planner or automatically with the Fitter are listed. Unassigned device pins are not listed. However, when board design tools from Mentor Graphics generate a.fx file, a complete list of assigned and unassigned pins for the device is created. The.fx file contains the same information found in the.pin file, as well as additional data concerning signal drive strength, differential pairs, and swappable pin groups. While a.pin file cannot be imported into Quartus II, a.fx file may be freely imported and exported whenever needed to update I/O assignments. 2

3 Conference website: With both files generated from Quartus II, board design tools import a complete picture of all the I/O assignment information created in Quartus II for the FPGA design. This is referred to as the forward design flow. When Quartus II imports an FPGA Xchange file generated by board design tools to update I/O assignments, this is referred to as reverse design flow. The names are arbitrary; a board designer can create I/O assignments and transfer those assignments to a FPGA designer for the initial creation of the FPGA design, making this the forward flow. For clarity, the forward and reverse design flows follow the paths shown in Figures 3 and 4. 5 Using Mentor Graphics Tools in the Design Flow Using the combination of Quartus II and board design tools from Mentor Graphics enables the forward and reverse design flows. I/O Designer utilizes assignment file transfer. It is a tool specifically created for design transfer between FPGA and board designs. Using I/O Designer provides complete forward and reverse flow, thus assignment information is readily transferred back and forth from Quartus II to I/O Designer. In addition to transfer capabilities, I/O Designer makes I/O assignment changes using an interface similar to Quartus II Pin Planner (see Figure 2). This functionality yields a graphical representation of the device where signals are assigned to pins by simply dragging and dropping from a list. Additionally, I/O Designer creates circuit schematic symbols that are used by schematic capture tools from Mentor Graphics. Extra features that assist with the design flow are pin assignment locking that prevents accidental assignment changes, and support for industry standard design repositories such as CVS. This permits only one user at a time to check into or out of a design while logging all previously made changes. Figure 2. Pin Planner and Device Editor Comparison To complete the design flow, symbols created in I/O Designer are instantiated in a schematic capture tool. I/O Designer directly supports all schematic capture tools from Mentor Graphics. For medium to highly complex designs, DxDesigner is a highly efficient and productive tool to use. DxDesigner is Mentor Graphics high-end circuit schematic capture tool and complements I/O Designer's functionality. Schematic symbols created in I/O Designer are stored in the symbol library of a designated DxDesigner project. These symbols are immediately available for instantiation in a DxDesigner schematic. Board designers using DxDesigner with I/O Designer can back-annotate pin swap changes made in either a board layout tool or changes made to a symbol in the DxDesigner symbol editor. With this capability, pin assignment changes made to improve the board layout are transferred back through I/O Designer for import into the original Quartus II project. The original design is then recompiled and refit utilizing the new assignments. DxDesigner software also has symbol creation capabilities to generate symbols based on just a.pin file from the Quartus II project. However, any assignment changes made in DxDesigner to symbols made from.pin files or back-annotated from a board layout tool cannot be transferred back to Quartus II. I/O Designer is required for this function. 6 Tasks in the Design Flow With the design flow established, the main tasks in the forward and reverse design flows are defined. 6.1 Tasks in the Forward Design Flow Figure 3 shows the details of the forward design flow. First, Quartus II is configured to generate assignment transfer files. A.pin file is always created when I/O Assignment Analysis or a full compilation runs in Quartus II; as a result, the only setup required is generation of the.fx file. This function is set in the Quartus II Assignment Settings. FPGA Xchange file generation is selected in the Board Level EDA Tool settings. Once set, the.fx file is generated when EDA Netlist Writer or a full compilation is run. The files are then generated and exported. Once files are created, they are used to set up a new or update an existing I/O Designer database file that stores all the assignment and symbol information about the device. Database files also keep track of any changes made to the I/O assignments or schematic symbols by using I/O Designer Update Wizard. In the database files, pointers to source files and generated schematic symbols in the Update Wizard automatically detect changes, alerting the user to perform an update to the database. 3

4 6.3 Tasks in the Reverse Design Flow If assignment changes are made in I/O Designer or back-annotated from the board layout, the FPGA design must be updated with the new assignments. This is the reverse design flow shown in Figure 4. Sending assignment changes back to a Quartus II FPGA design updates a.fx file in I/O Designer. By updating the FPGA Xchange file, changes are sent back to Quartus II by simply importing the updated.fx file into a Quartus II FPGA project. Running I/O Assignment Analysis in Quartus II checks any imported assignments. This verifies the new assignments function correctly in the design and validates the target device, thus making forward and reverse design flows complete. Figure 3. Forward Design Flow Assignment changes are made directly in I/O Designer using the Pin Planner-like interface (see Figure 4) or back-annotated from the board layout tool through DxDesigner into I/O Designer. If no further changes are required to I/O assignments, schematic symbols are built in DxDesigner using the I/O Designer Symbol Wizard. 6.2 Schematic Symbol Creation for DxDesigner The I/O Designer Symbol Wizard has many options for customizing the look of the final schematic symbols as well as functionality to fracture or split symbols into multiple, smaller parts. This is useful for FPGA devices as it breaks a large symbol with possibly over a thousand pins into a set of organized smaller symbols where each symbol is used for a specific function. For example, one symbol fracture contains all JTAG and configuration signals required by the device, while another may be used for just power and ground pins. This assists with fitting symbols on schematic pages as well as making circuit schematics easily read and specific signals easier to find. Symbols and symbol fractures created using Symbol Wizard are stored in the symbol library of the designated DxDesigner project. Symbols are then available for immediate instantiation into a DxDesigner schematic project. Completed schematics are forwarded to a board layout tool for routing and eventual board fabrication. 7 Conclusion Figure 4. Reverse Design Flow With the complexity of FPGA and board designs increasing, the time allocated for typical production schedules, including design, fabrication, and testing, is rapidly decreasing. Combining Quartus II with I/O Designer and DxDesigner provides a complete forward and reverse design flow for transferring I/O assignment information between a FPGA design and a board design. By partially automating the process, errors are avoided, productivity increased, and design cycles decreased. Creating and using a FPGA Xchange file and a pin-out file bridges parallel design flows, making the process fully operational. 4

5 8 References [1] Rick Stroot: Using I/O Designer in an Altera Quartus flow with FPGA Xchange, Mentor Graphics I/O Designer Application Note, July 2005 [2] Quartus II Development Software Handbook v.5.1, October

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