Video and Image Processing Suite
|
|
|
- Jane Summers
- 5 years ago
- Views:
Transcription
1 Video and Image Processing Suite December 2006, Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the MegaCore functions in the Video and Image Processing Suite, v7.0. Errata are functional defects or errors, which may cause the Video and Image Processing Suite MegaCore function to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from the current published specifications or product documents. Table 1 shows the issues that affect the Video and Image Processing Suite, v7.0. Table 1. Video and Image Processing Suite, v7.0 Issues Applicability Issue Page All MegaCore functions Suite v1.0 is Not Supported in v7.0 of the Quartus II Software 2 All MegaCore functions 64-bit Linux Operating Systems are Not Supported 2 All MegaCore functions Output Directory Must be Same as Project Directory 3 All MegaCore functions Cannot Interrupt Hardware Generation 3 Alpha Blending Mixer, Gamma Corrector M4K Write Operations May Fail for Cyclone II Devices 5 Gamma Corrector, Deinterlacer Multiple Clock Domains are Not Supported 5 Deinterlacer Deinterlacer Has Restricted Base Address Range 5 Scaler Generation Report for Scaler Omits Memory Initialization File 6 Currently, there are no specific errata for the Color Space Converter, Chroma Resampler, 2D FIR Filter, 2D Median Filter, or Line Buffer Compiler MegaCore functions. f For the most up-to-date errata for this release, refer to the errata sheet on the Altera website: Altera Corporation 1 ES-VIP
2 Video and Image Processing Suite Video and Image Processing Suite Issues Altera has identified the following issues that affects all MegaCore functions in the Video and Image Processing Suite: Suite v1.0 is Not Supported in v7.0 of the Quartus II Software The Video and Image Processing Suite version 1.0 is not compatible with version 6.1 or 7.0 of the Quartus II software. This issue affects all MegaCore functions in the Video and Image The MegaCore functions in version 1.0 of the Video and Image Processing Suite fail to launch from the MegaWizard Plug-In Manager in version 7.0 of the Quartus II software. This is because the hardware generation engine used by the Video and Image Processing Suite in Quartus II v7.0 has been changed to significantly reduce generation times. In addition, any HDL from version 6.0 Video and Image Processing Suite MegaCore functions which were generated with version 6.0 of the Quartus II software cannot be recompiled using version 7.0 if there are any version 6.1 or 7.0 MegaCore functions used in the design. Install version 7.0 of the Video and Image Processing Suite and upgrade any existing designs to use this new version. Future versions of the MegaCore functions in the Video and Image Processing Suite will be supported by the current and previous primary release of the Quartus II software tools. 64-bit Linux Operating Systems are Not Supported The Video and Image Processing Suite is not supported on 64-bit Linux operating systems. This issue affects all Video and Image Processing Suite MegaCore functions on Linux operating systems. 2 Altera Corporation
3 Video and Image Processing Suite Issues MegaCore Function generation would give unreliable results. Use a 32-bit Linux or Windows system. 64-bit Linux operating systems will be supported in a future release of the Video and Image Output Directory Must be Same as Project Directory The output directory specified in the MegaWizard interface must be the same as the project directory. This issue affects all MegaCore functions in the Video and Image If the output directory of a MegaWizard interface generated file is different from the project directory, an error is issued the generation fails to complete. Specify the same directory for your output files and the Quartus II project. Cannot Interrupt Hardware Generation The Cancel button in the MegaCore function Generation Report window may not immediately take effect because the "Generating hardware..." stage will only respond to an interrupt once it has completed. Altera Corporation 3
4 Video and Image Processing Suite This issue affects all MegaCore functions in the Video and Image The hardware generation phase must be allowed to complete. This may take several minutes. You can then exit from the generation report window and re-invoke the MegaWizard Plug-In Manager to update the MegaCore function. You must wait until the hardware generation phase has been completed. MegaCore Function Issues Altera has identified the following issues that affect specific MegaCore functions in the Video and Image Processing Suite: M4K Write Operations May Fail for Cyclone II Devices M4K block write operations may fail for Cyclone II devices with the Alpha Blending Mixer and Gamma Corrector MegaCore functions. This issue affects configurations using Cyclone II devices and the Alpha Blending Mixer or Gamma Corrector MegaCore function. The following error message is issued: Error: M4K memory block WYSIWYG primitive "vhdl_gam:vhdl_gam_inst TTA_X_smem_av:gamma_lut altsy ncram:\ds1:altsyncram_component altsyncram_rvh1:auto_ generated ram_block1a0" utilizes the dual-port dualclock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature. 4 Altera Corporation
5 MegaCore Function Issues If you are targeting any affected revision (Rev a or b of the 2c35 or Rev a of any other Cyclone II part), set the CYCLONEII_SAFE_WRITE variable to RESTRUCTURE. This causes the Quartus II software to fix the problem at a cost in M4Ks and F max. If you are using a newer revision device, set the CYCLONEII_SAFE_WRITE variable to VERIFIED_SAFE which turns off the error message. Refer to the Cyclone II FPGA Family Errata Sheet for more information about this issue. This issue has been fixed for the latest silicon devices but remains an issue if you are using the earlier silicon. Multiple Clock Domains are Not Supported You cannot use multiple clock domains with the Gamma Corrector and Deinterlacer MegaCore functions. This issue affects all configurations of the Gamma Corrector and Deinterlacer MegaCore functions. Although the Gamma Corrector and Deinterlacer have separate ports for their own internal clock and the Avalon clock for the control port, these should be connected to the same clock source or unreliable behavior may result. Run your MegaCore function at the same clock speed as the Avalon system. Deinterlacer Has Restricted Base Address Range The Deinterlacer MegaCore function only supports base addresses in the range 0 to 0x7fffffff. Altera Corporation 5
6 Video and Image Processing Suite This issue affects all configurations of the Deinterlacer MegaCore function. The parameterization will not complete if you choose an address higher than the supported range. Use a base address in the range 0 to 0x7fffffff. This issue will be fixed to allow the full range of 32 bit addresses in a future release of the Video and Image Generation Report for Scaler Omits Memory Initialization File The generation report for the Scaler MegaCore function in bicubic mode does not list the memory initialization file (MIF) for the coefficients. This issue affects any configuration of the Scaler MegaCore function that uses bicubic interpolation. If the memory initialization file is not found by the Quartus II software, the coefficients will be treated as 0, causing the Scaler MegaCore function to output black data regardless of input. Ensure that the file <instance name>_scl_coeffs_reg_file_contents.hex is in the same directory as your Quartus II project. This can be checked by looking in the RAM Summary section of the Analysis & Synthesis compilation report. There should be an ALT_MEM component named coeff_reg_file inside the Scaler entity with an associated MIF file named <instance name>_scl_coeffs_reg_file_contents.hex. 6 Altera Corporation
7 Contact Information Contact Information Revision History For more information, contact Altera's mysupport website at and click Create New Service Request. Choose the Product Related Request form. Table 2 shows the revision history for the Video and Image Processing Suite, v7.0 Errata Sheet. Table 2. Revision History Version Date Errata Summary 1.1 December 2006 Added errata M4K Write Operations May Fail for Cyclone II Devices. 1.0 December 2006 First release of this errata sheet 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: literature@altera.com Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Corporation 7
Table 1 shows the issues that affect the FIR Compiler v7.1.
May 2007, Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the Altera, v7.1. Errata are functional defects or errors, which may cause an Altera MegaCore function
DSP Builder. DSP Builder v6.1 Issues. Error When Directory Pathname is a Network UNC Path
March 2007, Version 6.1 Errata Sheet This document addresses known errata and documentation changes for DSP Builder version 6.1. Errata are functional defects or errors which may cause DSP Builder to deviate
DSP Development Kit, Stratix II Edition
DSP Development Kit, Stratix II Edition August 2005, Development Kit version 1.1.0 Errata Sheet This document addresses known errata and documentation changes the DSP Development Kit, Stratix II Edition
Table 1 shows the issues that affect the FIR Compiler, v6.1. Table 1. FIR Compiler, v6.1 Issues.
December 2006, Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the Altera FIR Compiler, v6.1. Errata are functional defects or errors, which may cause an Altera
Cyclone II FPGA Family
ES-030405-1.3 Errata Sheet Introduction This errata sheet provides updated information on Cyclone II devices. This document addresses known device issues and includes methods to work around the issues.
RapidIO MegaCore Function
March 2007, MegaCore Function Version 3.1.1 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.1. Errata are functional defects
POS-PHY Level 4 MegaCore Function
POS-PHY Level 4 MegaCore Function November 2004, MegaCore Version 2.2.2 Errata Sheet Introduction This document addresses known errata and documentation changes for version v2.2.2 of the POS-PHY Level
DDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler march 2007, Compiler Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 7.0.
UTOPIA Level 2 Slave MegaCore Function
UTOPIA Level 2 Slave MegaCore Function October 2005, Version 2.5.0 Release Notes These release notes for the UTOPIA Level 2 Slave MegaCore function contain the following information: System Requirements
DDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler May 2006, Compiler Version 3.3.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1.
DDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler August 2007, Compiler Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version
RapidIO Physical Layer MegaCore Function
RapidIO Physical Layer MegaCore Function April 2005, MegaCore version 2.2.1 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.2.1 of the RapidIO Physical
Nios II Embedded Design Suite 6.1 Release Notes
December 2006, Version 6.1 Release Notes This document lists the release notes for the Nios II Embedded Design Suite (EDS) version 6.1. Table of Contents: New Features & Enhancements...2 Device & Host
RLDRAM II Controller MegaCore Function
RLDRAM II Controller MegaCore Function November 2006, MegaCore Version 1.0.0 Errata Sheet This document addresses known errata and documentation issues for the RLDRAM II Controller MegaCore function version
RapidIO MegaCore Function
March 2007, MegaCore Function Version 3.1.0 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.0. Errata are functional defects
DDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller October 2005, Compiler Version 3.3.0 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.0 contain the following information: System
DDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller December 2005, Compiler Version 3.3.1 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1 contain the following information: System
FFT MegaCore Function
FFT MegaCore Function March 2007, MegaCore Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the FFT MegaCore function version 6.1. Errata are functional defects
SONET/SDH Compiler. Introduction. SONET/SDH Compiler v2.3.0 Issues
January 2005, Compiler Version 2.3.0 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.3.0 of the SONET/SDH Compiler. Errata are design functional defects
PCI Express Compiler. System Requirements. New Features & Enhancements
April 2006, Compiler Version 2.1.0 Release Notes These release notes for the PCI Express Compiler version 2.1.0 contain the following information: System Requirements New Features & Enhancements Errata
Nios II Embedded Design Suite 7.1 Release Notes
Nios II Embedded Design Suite 7.1 Release Notes May 2007, Version 7.1 Release Notes This document contains release notes for the Nios II Embedded Design Suite (EDS) version 7.1. Table of Contents: New
RapidIO MegaCore Function
RapidIO MegaCore Function October 2007, MegaCore Function Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 7.0. Errata
Using the Serial FlashLoader With the Quartus II Software
Using the Serial FlashLoader With the Quartus II Software July 2006, ver. 3.0 Application Note 370 Introduction Using the Joint Test Action Group () interface, the Altera Serial FlashLoader (SFL) is the
Enhanced Configuration Devices
Enhanced Configuration Devices October 2007, Version 1.2 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices
FPGAs Provide Reconfigurable DSP Solutions
FPGAs Provide Reconfigurable DSP Solutions Razak Mohammedali Product Marketing Engineer Altera Corporation DSP processors are widely used for implementing many DSP applications. Although DSP processors
FFT MegaCore Function User Guide
FFT MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: 11.0 Document Date: May 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The
Introduction. Design Hierarchy. FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow
FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow February 2002, ver. 2.0 Application Note 171 Introduction To maximize the benefits of the LogicLock TM block-based design methodology in the
Simulating the Reed-Solomon Model
July 2000, ver. 1 Simulating the Reed-Solomon Model with the Visual IP Software User Guide Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera, and
DDR and DDR2 SDRAM Controller Compiler User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Operations Part Number Compiler Version: 8.1 Document Date: November 2008 Copyright 2008 Altera
Active Serial Memory Interface
Active Serial Memory Interface October 2002, Version 1.0 Data Sheet Introduction Altera Cyclone TM devices can be configured in active serial configuration mode. This mode reads a configuration bitstream
Simple Excalibur System
Excalibur Solutions Simple Excalibur System August 2002, ver. 1.0 Application Note 242 Introduction This application note describes a simple Excalibur system design that consists of software running on
Simulating the PCI MegaCore Function Behavioral Models
Simulating the PCI MegaCore Function Behavioral Models August 2001, ver. 1.0 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,
Simulating the PCI MegaCore Function Behavioral Models
Simulating the PCI MegaCore Function Behavioral Models February 2003, ver. 1.2 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,
PCI Express Multi-Channel DMA Interface
2014.12.15 UG-01160 Subscribe The PCI Express DMA Multi-Channel Controller Example Design provides multi-channel support for the Stratix V Avalon Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core.
DSP Builder Release Notes
April 2006, Version 6.0 SP1 Release Notes These release notes for DSP Builder version 6.0 SP1 contain the following information: System Requirements New Features & Enhancements Errata Fixed in This Release
24K FFT for 3GPP LTE RACH Detection
24K FFT for GPP LTE RACH Detection ovember 2008, version 1.0 Application ote 515 Introduction In GPP Long Term Evolution (LTE), the user equipment (UE) transmits a random access channel (RACH) on the uplink
Estimating Nios Resource Usage & Performance
Estimating Nios Resource Usage & Performance in Altera Devices September 2001, ver. 1.0 Application Note 178 Introduction The Excalibur Development Kit, featuring the Nios embedded processor, includes
Simulating the ASMI Block in Your Design
2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,
Using MAX 3000A Devices as a Microcontroller I/O Expander
Using MAX 3000A Devices as a Microcontroller I/O Expander August 2003, Ver 1.0 Application Note 265 Introduction Advantages of Using MAX 3000A Devices Many microcontrollers and microprocessors limit I/O
4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices
January 2011 HIV51004-2.2 4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices HIV51004-2.2 This chapter describes TriMatrix memory blocks, modes, features, and design considerations in HardCopy
Using Verplex Conformal LEC for Formal Verification of Design Functionality
Using Verplex Conformal LEC for Formal Verification of Design Functionality January 2003, ver. 1.0 Application Note 296 Introduction The Altera Quartus II software, version 2.2, easily interfaces with
Using VCS with the Quartus II Software
Using VCS with the Quartus II Sotware December 2002, ver. 1.0 Application Note 239 Introduction As the design complexity o FPGAs continues to rise, veriication engineers are inding it increasingly diicult
Stratix FPGA Family. Table 1 shows these issues and which Stratix devices each issue affects. Table 1. Stratix Family Issues (Part 1 of 2)
January 2007, ver. 3.1 Errata Sheet This errata sheet provides updated information on Stratix devices. This document addresses known issues and includes methods to work around the issues. Table 1 shows
FFT/IFFT Block Floating Point Scaling
FFT/IFFT Block Floating Point Scaling October 2005, ver. 1.0 Application Note 404 Introduction The Altera FFT MegaCore function uses block-floating-point (BFP) arithmetic internally to perform calculations.
CORDIC Reference Design. Introduction. Background
CORDIC Reference Design June 2005, ver. 1.4 Application Note 263 Introduction The co-ordinate rotation digital computer (CORDIC) reference design implements the CORDIC algorithm, which converts cartesian
For Quartus II Software. This Quick Start Guide will show you how to set up a Quartus
Quick Start Guide For Quartus II Software This Quick Start Guide will show you how to set up a Quartus II project, enter timing requirements, and compile the design into an Altera device. 1 Three-Step
Stratix II FPGA Family
October 2008, ver. 2.1 Errata Sheet Introduction This errata sheet provides updated information on Stratix II devices. This document addresses known device issues and includes methods to work around the
Toolflow for ARM-Based Embedded Processor PLDs
Toolflow for ARM-Based Embedded Processor PLDs December 2000, ver. 1 Application Note Introduction The Excalibur embedded processor devices achieve a new level of system integration from the inclusion
Enhanced Configuration Devices
Enhanced Configuration Devices July 2008, Version 1.3 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices
Design Verification Using the SignalTap II Embedded
Design Verification Using the SignalTap II Embedded Logic Analyzer January 2003, ver. 1.0 Application Note 280 Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera
Nios II Performance Benchmarks
Subscribe Performance Benchmarks Overview This datasheet lists the performance and logic element (LE) usage for the Nios II Classic and Nios II Gen2 soft processor, and peripherals. Nios II is configurable
Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander
Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander March 2004, ver 2.0 Application Note 265 Introduction Advantages of Using MAX II & MAX 3000A Devices Many microcontroller and microprocessors
Arria II GX FPGA Development Board
Arria II GX FPGA Development Board DDR2 SODIMM Interface 2011 Help Document DDR2 SODIMM Interface Measurements were made on the DDR2 SODIMM interface using the Board Test System user interface. The Address,
Excalibur Solutions DPRAM Reference Design
Excalibur Solutions DPRAM Reference Design August 22, ver. 2.3 Application Note 173 Introduction The Excalibur devices are excellent system development platforms, offering flexibility, performance, and
ByteBlaster II Parallel Port Download Cable
ByteBlaster II Parallel Port Download Cable December 2002, Version 1.0 Data Sheet Features Allows PC users to perform the following functions: Program MAX 9000, MAX 7000S, MAX 7000AE, MAX 7000B, MAX 3000A,
Exercise 1 In this exercise you will review the DSSS modem design using the Quartus II software.
White Paper DSSS Modem Lab Background The direct sequence spread spectrum (DSSS) digital modem reference design is a hardware design that has been optimized for the Altera APEX DSP development board (starter
altshift_taps Megafunction User Guide
altshift_taps Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Document Version: 1.0 Document Date: September 2004 Copyright 2004 Altera Corporation. All rights
4K Format Conversion Reference Design
4K Format Conversion Reference Design AN-646 Application Note This application note describes a 4K format conversion reference design. 4K resolution is the next major enhancement in video because of the
Introduction. Synchronous vs. Asynchronous Memory. Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs
Converting from synchronous to Synchronous for Stratix & Stratix GX esigns November 2002, ver. 2.0 pplication Note 210 Introduction The Stratix TM and Stratix GX device families provide a unique memory
Matrices in MAX II & MAX 3000A Devices
Crosspoint Switch Matrices in MAX II & MAX 3000A Devices March 200, ver. 2.0 Application Note 29 Introduction With a high level of flexibility, performance, and programmability, you can use crosspoint
White Paper Using the MAX II altufm Megafunction I 2 C Interface
White Paper Using the MAX II altufm Megafunction I 2 C Interface Introduction Inter-Integrated Circuit (I 2 C) is a bidirectional two-wire interface protocol, requiring only two bus lines; a serial data/address
10. Introduction to UniPHY IP
10. Introduction to Uni IP November 2012 EMI_RM_008-2.1 EMI_RM_008-2.1 The Altera,, and LP SDRAM controllers with Uni, QDR II and QDR II+ SRAM controllers with Uni, RLDRAM II controller with Uni, and RLDRAM
Implementing LED Drivers in MAX and MAX II Devices. Introduction. Commercial LED Driver Chips
Implementing LE rivers in MAX and MAX II evices October 2008 AN-286-2.3 Introduction iscrete LE driver chips are common on many system boards. Altera MAX II, MAX 7000B, MAX 7000A, MAX 3000A, and MAX 7000S
MAX 10 User Flash Memory User Guide
MAX 10 User Flash Memory User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-M10UFM 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents MAX 10 User Flash Memory
ByteBlaster II Download Cable User Guide
ByteBlaster II Download Cable User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com UG-BBII81204-1.1 P25-10324-00 Document Version: 1.1 Document Date: December 2004 Copyright
Using the Nios Development Board Configuration Controller Reference Designs
Using the Nios Development Board Controller Reference Designs July 2006 - ver 1.1 Application Note 346 Introduction Many modern embedded systems utilize flash memory to store processor configuration information
AIRbus Interface. Features Fixed width (8-, 16-, or 32-bit) data transfers (dependent on the width. Functional Description. General Arrangement
AIRbus Interface December 22, 2000; ver. 1.00 Functional Specification 9 Features Fixed width (8-, 16-, or 32-bit) data transfers (dependent on the width of the data bus) Read and write access Four-way
Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide
Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide 11 Innovation Drive San Jose, CA 95134 www.altera.com Software Version 8. Document Version: 2. Document Date: June 28
Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim
Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Ray Duran Staff Design Specialist FAE, Altera Corporation 408-544-7937
Implementing LED Drivers in MAX Devices
Implementing LE rivers in MAX evices ecember 2002, ver. 1.0 Application Note 286 Introduction Commercial LE river Chips iscrete light-emitting diode (LE) driver chips are common on many system boards.
FFT MegaCore Function User Guide
FFT MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: 8.1 Document Date: November 2008 Copyright 2008 Altera Corporation. All rights reserved. Altera,
Errata Sheet for Cyclone IV Devices
Errata Sheet for Cyclone IV Devices ES-01027-2.3 Errata Sheet This errata sheet provides updated information on known device issues affecting Cyclone IV devices. Table 1 lists specific Cyclone IV issues,
December 2002, ver. 1.3 Application Note 191. Six individual interrupts Six-bit priority scheme Five-bit priority scheme plus one individual interrupt
Excalibur Solutions Using the Interrupt Controller December 22, ver..3 Application Note 9 Introduction This document describes the operation of the interrupt controller for the Excalibur devices, particularly
Video Input Daughter Card Reference Manual
Video Input Daughter Card Reference Manual 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Document Version 1.0 Document Date November 2006 Copyright 2006 Altera Corporation.
White Paper. Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core. Introduction. Parameters & Ports
White Paper Introduction Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core The floating-point fast fourier transform (FFT) processor calculates FFTs with IEEE 754 single precision (1
On-Chip Memory Implementations
On-Chip Memory Implementations Using Cyclone Memory Blocks March 2003, ver. 1.1 Application Note 252 Introduction Cyclone devices feature embedded memory blocks that can be easily configured to support
Debugging Nios II Systems with the SignalTap II Logic Analyzer
Debugging Nios II Systems with the SignalTap II Logic Analyzer May 2007, ver. 1.0 Application Note 446 Introduction As FPGA system designs become more sophisticated and system focused, with increasing
8. Introduction to UniPHY IP
8. Introduction to Uni IP November 2011 EMI_RM_008-1.1 EMI_RM_008-1.1 The Altera and SDRAM controllers with Uni, QDR II and QDR II+ SRAM controllers with Uni, and RLDRAM II controller with Uni provide
Simultaneous Multi-Mastering with the Avalon Bus
Simultaneous Multi-Mastering with the Avalon Bus April 2002, ver. 1.1 Application Note 184 Introduction The Excalibur Development Kit, featuring the Nios embedded processor version 2.1 supports an enhanced
Legacy SDRAM Controller with Avalon Interface
Legacy SDRAM Controller with Avalon Interface January 2003, Version 1.0 Data Sheet Introduction PTF Assignments SDRAM is commonly used in cost-sensitive applications requiring large amounts of memory.
AN 549: Managing Designs with Multiple FPGAs
AN 549: Managing Designs with Multiple FPGAs October 2008 AN-549-1.0 Introduction Managing designs that incorporate multiple FPGAs raises new challenges that are unique compared to designs using only one
White Paper Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace
Introduction White Paper Between Altera Classic Timing Analyzer and Xilinx Trace Most hardware designers who are qualifying FPGA performance normally run bake-off -style software benchmark comparisons
Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices Subscribe Feedback The Altera Transceiver Reconfiguration Controller dynamically reconfigures
Nios Soft Core Embedded Processor
Nios Soft Core Embedded Processor June 2000, ver. 1 Data Sheet Features... Preliminary Information Part of Altera s Excalibur TM embedded processor solutions, the Nios TM soft core embedded processor is
EFEC20 IP Core. Features
EFEC20 IP Core DS-1034-1.2 Data Sheet The Altera 20% Enhanced Forward Error Correction (EFEC20) IP core includes a highperformance encoder and decoder for Optical Transport Network (OTN) FEC applications.
ZBT SRAM Controller Reference Design
ZBT SRAM Controller Reference Design for APEX II Devices December 2001, ver. 1.0 Application Note 183 Introduction As communication systems require more low-latency, high-bandwidth interfaces for peripheral
FPGA Design Security Solution Using MAX II Devices
White Paper FPGA Solution Using MAX II Devices Introduction SRAM-based FPGAs are volatile devices. They require external memory to store the configuration data that is sent to them at power up. It is possible
Figure 1. Device Package Ordering Information for Stratix, Stratix GX, Cyclone, APEX 20KC, APEX II, Mercury & Excalibur Devices EP1S 25 F 780 C 5 N
April 2003, ver. 15 Altera Devices Figures 1 and 2 explain the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes.
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current January 2009 AN-547-10 Introduction To save power, the MAX II CPLD can be completely powered down into hibernation mode
White Paper Configuring the MicroBlaster Passive Serial Software Driver
White Paper Configuring the MicroBlaster Passive Serial Software Driver Introduction The MicroBlaster TM software driver is designed to configure Altera programmable logic devices (PLDs) through the ByteBlasterMV
Stratix vs. Virtex-II Pro FPGA Performance Analysis
White Paper Stratix vs. Virtex-II Pro FPGA Performance Analysis The Stratix TM and Stratix II architecture provides outstanding performance for the high performance design segment, providing clear performance
Low Power Design Techniques
Low Power Design Techniques August 2005, ver 1.0 Application Note 401 Introduction This application note provides low-power logic design techniques for Stratix II and Cyclone II devices. These devices
System Debugging Tools Overview
9 QII53027 Subscribe About Altera System Debugging Tools The Altera system debugging tools help you verify your FPGA designs. As your product requirements continue to increase in complexity, the time you
E3 Mapper MegaCore Function (E3MAP)
MegaCore Function (E3MAP) March 9, 2001; ver. 1.0 Data Sheet Features Easy-to-use MegaWizard Plug-In generates MegaCore variants Quartus TM II software and OpenCore TM feature allow place-androute, and
100G Interlaken MegaCore Function User Guide
00G Interlaken MegaCore Function User Guide Subscribe UG-028 05.06.203 0 Innovation Drive San Jose, CA 9534 www.altera.com TOC-2 00G Interlaken MegaCore Function User Guide Contents About This MegaCore
Excalibur Solutions Using the Expansion Bus Interface. Introduction. EBI Characteristics
Excalibur Solutions Using the Expansion Bus Interface October 2002, ver. 1.0 Application Note 143 Introduction In the Excalibur family of devices, an ARM922T processor, memory and peripherals are embedded
Logic Optimization Techniques for Multiplexers
Logic Optimiation Techniques for Multiplexers Jennifer Stephenson, Applications Engineering Paul Metgen, Software Engineering Altera Corporation 1 Abstract To drive down the cost of today s highly complex
Stratix II vs. Virtex-4 Performance Comparison
White Paper Stratix II vs. Virtex-4 Performance Comparison Altera Stratix II devices use a new and innovative logic structure called the adaptive logic module () to make Stratix II devices the industry
Dynamic Reconfiguration of PMA Controls in Stratix V Devices
Dynamic Reconfiguration of PMA Controls in Stratix V Devices AN-645-1.0 Application Note This application note describes how to use the transceiver reconfiguration controller to dynamically reconfigure
Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators
White Paper Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators You can use the Visual IP software from Innoveda with Altera-provided models to simulate Altera