PCI 2.3 and PCI 3.0 Key Changes Dan Neal Senior Consultant QuestTech

Size: px

Start display at page:

Download "PCI 2.3 and PCI 3.0 Key Changes Dan Neal Senior Consultant QuestTech"

Emerald Ross
5 years ago
Views:

5 Background PCI 2.1 Key Changes 66 MHz PCI provided a significant performance improvement Addition of Delayed Transaction also allowed a significant performance improvement Copyright 2003, PCI-SIG, All Rights Reserved 5

6 Background PCI 2.2 incorporated new ECNs, such as: New Capabilities structure to expand configuration space Certain capabilities added to PCI starting in PCI 2.2 are supported by adding a set of registers to a linked list called the Capabilities List. This optional data structure is indicated in the PCI Status Register by setting the Capabilities List bit (bit 4) to indicate that the Capabilities Pointer is located at offset 34h. This register points to the first item in the list of capabilities. Capabilities Pointer A4h Offset 34h Capability X E0h ID for X 5Ch Capability Y 5Ch ID for Y 4Ah Capability Z 00h ID for Z E0h Copyright 2003, PCI-SIG, All Rights Reserved 6

7 Background PCI 2.2 incorporated new ECNs (cont) New PME# signal for remote wake up capability Adds a 3.3VAux signal defining a standard source of power for power management wake events Copyright 2003, PCI-SIG, All Rights Reserved 7

8 Background PCI 2.2 incorporated new ECNs (cont) Defines a Max Retry Time Devices cannot Retry a memory write request for longer than 10 us Some displays were found to hold off accesses with retry, while the frame buffer was used in refreshing the screen (BW was good enough to support the screen refresh, but not simultaneously handle new accesses). This is an item tested at the workshops. Message signaled interrupts was added, giving I/O controllers ability to deliver message based interrupts Copyright 2003, PCI-SIG, All Rights Reserved 8

9 Background PCI 2.2 incorporated new ECNs (cont) A definition for Spread Spectrum Clocking was added This adds a low frequency variation about the clock frequency to reduce EMI (30-33 KHz variation, -1%) Incorporates an alternative access method to VPD Alternative enables less expensive use of EEPROMS Copyright 2003, PCI-SIG, All Rights Reserved 9

11 Key Changes in PCI 2.3 A very significant change with PCI 2.3: Support for 5V Add-in Cards removed PCI 2.3 is the last PCI Spec defined to allow the 5V Keyed option slot. Add-in card designers that want their cards to plug into these option slots must utilize the Universal Addin Card. When added performance is required, system designers are encouraged to migrate their 33 MHz or 66 MHz PCI option slots to PCI-X 66, which will accept all PCI 2.3 compliant Add-in cards. Copyright 2003, PCI-SIG, All Rights Reserved 11

12 Key Changes in PCI Spec Change Requiring Silicon Change: Chapter 6 Configuration Space Added Interrupt Disable bit to the command register. Added Interrupt Status bit to the status register. Copyright 2003, PCI-SIG, All Rights Reserved 12

13 Key Changes in PCI 2.3 Other General PCI 2.3 Spec changes: Incorporated Errata list Use of multiple names for the same thing were changed to be consistent: I.e. change to Add-in Card, and System Board. Preface: Updated ECN list Copyright 2003, PCI-SIG, All Rights Reserved 13

14 Key Changes in PCI Spec Changes Requiring system or Add-in Card Changes: Support for 5V Add-in Card removed (test, figures, etc) Chapter 1 Introduction: Sections 1.3, 1.4, & 1.5 modified to indicate the 5V keyed card is no longer supported and included references to PCI-X spec and its higher operating frequencies. Chapter 4 Electrical Specification: Removed support for 5V keyed Add-in Cards. Section Moved 3.3V system timing budget description from section to this section. Table 4-11 Reversed the position of the 3.3V and 5V System Environment columns. Table 4-13 Deleted the 5V Add-in Card column. Chapter 5 Mechanical Specification Deleted the 5V keyed Add-in Card and Micro Channel figures Copyright 2003, PCI-SIG, All Rights Reserved 14

15 Key Changes in PCI Spec Changes Requiring system or Add-in Card Changes (cont): Added Reset Timing parameter T pvrh = 100 ms minimum (power valid to reset high) This ECN adds a timing requirement to guarantee a minimum time between power valid and reset deassertion Gives time for FPGAs to be loaded, prior to accessing the device during configuration. Copyright 2003, PCI-SIG, All Rights Reserved 15

16 Key Changes in PCI Spec Changes whose implementation is optional Added SMBus ECN as chapter 8 This ECN adds a two-wire management interface to the PCI connector. Chapter 2 Signal Definition: Section The SMBus signals were added. Chapter 4 Table 4-11 Added SMBus signals to the table Copyright 2003, PCI-SIG, All Rights Reserved 16

17 Key Changes in PCI Spec Changes whose implementation is optional (cont) Added the Low Profile ECN (Chapter 5 Mechanical) This ECN added a new mechanical form factor to the PCI Local Bus Specification for low profile systems Low Profile PCI cards have the same signal protocol, electrical definitions, and configuration definitions as standard PCI cards. Copyright 2003, PCI-SIG, All Rights Reserved 17

18 Key Changes in PCI Spec Changes whose implementation is optional (cont) Incorporated the Add-in Card Trace Impedance ECN. Chapter 4 Electrical Specification, Section : This extends the impedance range to ohms. Change needed for compatibility with PCI-X Added Extensible Firmware Interface to the Code Type item in Chapter 6 Configuration Space, Section Copyright 2003, PCI-SIG, All Rights Reserved 18

19 Key Changes in PCI 2.3 Other 2.3 Spec Changes Chapter 3 Bus Operation: Section A reference to section was added for parity errors. Section Changed from Address/Data stepping to IDSEL Stepping. Make more similar to PCI-X (change from add/data stepping to IDSEL stepping to be more like PCI-X (add/data stepping not allowed in PCI-X) Chapter 4 Electrical Specification: Table 4-11 Added PCIXCAP signal to the table Table 4-13 Deleted the 5V Add-in Card column. Copyright 2003, PCI-SIG, All Rights Reserved 19

20 Key Changes in PCI 2.3 Other 2.3 Changes (cont) Appendix D Class Codes: Updated appendix D with new class code assignments - See additions to Base Class 01h, Base Class 02h, Base Class 06h, Base Class 07h, Base Class 0Ch, Base Class 0Dh, and Base Class 11h. Appendix H Capability IDs: Updated appendix H with new Capability IDs Added IDs 7-0xC. Appendix I Vital Product Data: Added VPD read-only keywords of FG, LC, & PG. These new keywords are intended to be used only in designs based on PICMG specifications. Copyright 2003, PCI-SIG, All Rights Reserved 20

22 Key Changes PCI 3.0 PCI 3.0 Status: Member review accomplished Publication waiting on finalization of MSI-X ECN MSI-X ECN is against PCI 2.3 However, MSI-X ECN content was included in PCI 3.0 member review draft (ECN and PCI 3.0 review in parallel) PCI 3.0 to be published 2 nd half 2003 Copyright 2003, PCI-SIG, All Rights Reserved 22

23 Key Changes PCI 3.0 The primary change for PCI 3.0: Support for the 5V Keyed option slot is removed PCI 3.0 is the first PCI Spec that no longer allows support for the 5V Keyed option slot. Add-in card designers that want their cards to plug into 3.0 compliant systems must utilize the Universal Add-in Card or the 3.3V Add-in Card. When added performance is required, system designers are encouraged to migrate their 33 MHz or 66 MHz PCI option slots to PCI-X 66, which will accept all PCI 2.3 compliant Add-in cards. Copyright 2003, PCI-SIG, All Rights Reserved 23

25 Key Changes PCI 3.0 MSI Message Signaled Interrupts (MSI) is an optional feature that enables a device function to request service by writing a system-specified data value to a system-specified address (using a PCI DWORD memory write transaction). System software initializes the message address and message data (referred to as the vector ) during device configuration, allocating one or more vectors to each MSI capable function. Copyright 2003, PCI-SIG, All Rights Reserved 25

26 Key Changes PCI 3.0 MSI-X MSI-X defines a separate optional extension to basic MSI functionality. Many of the characteristics of MSI-X are identical to those of MSI. MSI-X additional capabilities include, a larger maximum number of vectors per function the ability for software to control aliasing, when fewer vectors are allocated than requested the ability for each vector to use an independent address and data value, specified by a table that resides in Memory Space. Copyright 2003, PCI-SIG, All Rights Reserved 26

27 Key Changes PCI 3.0 MSI and MSI-X ECN MSI and MSI-X each support per-vector masking. Per-vector masking is an optional extension to MSI, and a standard feature with MSI-X. A function that supports the per-vector masking extension to MSI is still backward compatible with system software that is unaware of the extension. MSI-X also supports a Function Mask bit, which when set masks all of the vectors associated with a function. Copyright 2003, PCI-SIG, All Rights Reserved 27

28 Key Changes PCI 3.0 Per-vector masking Per-vector masking is managed through a Mask and Pending bit pair per MSI vector or MSI-X Table entry. An MSI vector is masked when its associated Mask bit is set. An MSI-X vector is masked when its associated MSI-X Table entry Mask bit or the MSI-X Function Mask bit is set. While a vector is masked, the function is prohibited from sending the associated message, and the function must set the associated Pending bit whenever the function would otherwise send the message. Copyright 2003, PCI-SIG, All Rights Reserved 28

29 Key Changes PCI 3.0 MSI-X ECN A function is permitted to implement both MSI and MSI-X, but system software is prohibited from enabling both at the same time. For the sake of software backward compatibility, MSI and MSI-X use separate and independent capability structures. On functions that support both MSI and MSI-X, system software that supports only MSI can still enable and use MSI without any modification. Copyright 2003, PCI-SIG, All Rights Reserved 29

30 Key Changes PCI 3.0 MSI Capability Structure Capability Structure for 32-bit Message Address Message Control Next Pointer Message Address Message Data Capability ID Capability Pointer Capability Pointer + 04h Capability Pointer + 08h To request service, an MSI function writes the contents of the Message Data register to the address specified by the contents of the Message Address register. The message control register indicates the function s capabilities and provides system software control over MSI. Copyright 2003, PCI-SIG, All Rights Reserved 30

31 Key Changes PCI 3.0 MSI Capability Structure Capability Structure for 64-bit Message Address Message Control Next Pointer Message Address Message Upper Address Message Data Capability ID Capability Pointer Capability Pointer + 04h Capability Pointer + 08h Capability Pointer + 0Ch To request service, an MSI function writes the contents of the Message Data register to the address specified by the contents of the Message Address register. The message control register indicates the function s capabilities and provides system software control over MSI. Copyright 2003, PCI-SIG, All Rights Reserved 31

32 Key Changes PCI 3.0 MSI Capability Structure Capability Structure for 32-bit Message Address and Per-vector Masking Message Control Next Pointer Message Address Reserved Mask Bits Pending Bits Capability ID Message Data Capability Pointer Capability Pointer + 04h Capability Pointer + 08h Capability Pointer + 0Ch Capability Pointer + 10h Copyright 2003, PCI-SIG, All Rights Reserved 32

33 Key Changes PCI 3.0 MSI Capability Structure Capability Structure for 64-bit Message Address and Per-vector Masking Message Control Next Pointer Message Address Message Upper Address Reserved Mask Bits Pending Bits Capability ID Message Data Capability Pointer Capability Pointer + 04h Capability Pointer + 08h Capability Pointer + 0Ch Capability Pointer + 10h Capability Pointer + 14h Copyright 2003, PCI-SIG, All Rights Reserved 33

34 Key Changes PCI 3.0 MSI-X Capability and Table Structures Message Control Next Capability CP +00h Pointer ID Table Offset PBA Offset MSI-X Capability Structure Table BIR PBA BIR CP +00h CP +00h Different from MSI, the MSI-X capability structure points to an MSI-X Table Structure and a MSI-X Pending Bit Array (PBA) structure, each residing in Memory Space. Each structure is mapped by a Base Address register (BAR) belonging to the function. A BAR Indicator register (BIR) indicates which BAR, and maps Memory space. Copyright 2003, PCI-SIG, All Rights Reserved 34

35 Key Changes PCI 3.0 MSI-X Capability and Table Structures DWORD3 DWORD2 DWORD1 DWORD0 Vector Ctrl Msg Data Msg Upper Addr Msg Address entry 0 Base Vector Ctrl Msg Data Msg Upper Addr Msg Address entry 1 Base +1*16 Vector Ctrl Msg Data Msg Upper Addr Msg Address entry 2 Base +2* Vector Ctrl Msg Data Msg Upper Addr Msg Address entry (N-1) Base +(N-1)*16 MSI-X Table Structure Copyright 2003, PCI-SIG, All Rights Reserved 35

36 Key Changes PCI 3.0 MSI-X Capability and Table Structures Pending Bits 0 through 63 Pending Bits 64 through 127. Pending Bits ((N-1) div 64)*64 through N-1 QWORD0 Base QWORD1 Base + 1*8 QWORD0 Base QWORD((N-1) div 64) Base+((N-1) div 64)*8 MSI-X PBA Structure Copyright 2003, PCI-SIG, All Rights Reserved 36

37 Key Changes PCI 3.0 Enabling and Sending Message Interrupts Both MSI and MSI-X are disabled following reset. System configuration software sets either the MSI Enable bit or the MSI-X Enable bit to enable either MSI or MSI-X, but never both simultaneously. Once MSI or MSI-X is enabled, and one or more vectors is unmasked, the function is permitted to send messages. To send a message, a function does a DWORD memory write to the appropriate message address with the appropriate message data. Copyright 2003, PCI-SIG, All Rights Reserved 37

Architecture Specification

PCI-to-PCI Bridge Architecture Specification, Revision 1.2 June 9, 2003 PCI-to-PCI Bridge Architecture Specification Revision 1.1 December 18, 1998 Revision History REVISION ISSUE DATE COMMENTS 1.0 04/05/94