ExpressLane PEX 8114-BC/BD

Transcription

1 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book Version 3.2 September 2010 Website Technical Support Phone FAX Copyright 2010 by PLX Technology, Inc. All Rights Reserved Version 3.2 September, 2010

2 Data Book PLX Technology, Inc. Copyright Information Copyright PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG). All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Document Number: 8114-BC/BD-SIL-DB-P1-3.2 ii Copyright 2010 by PLX Technology, Inc. All Rights Reserved

3 September, 2010 Revision History Revision History Version Date Description of Changes 1.0 June, 2006 Initial production release, Silicon Revision BA. 1.1 August, December, 2006 Added notes regarding NT mode errata. Revised Register 17-12, offset 30h Expansion ROM Base Address. Updated miscellaneous electrical specifications. Added pull-up information for JTAG_TCK, and removed pull-up information from EE_PR# and all Hot Plug outputs. Moved thermal resistance information to Chapter 20 (from Chapter 19) and added heat sink-related information. Applied miscellaneous corrections throughout the data book. Production release, Silicon Revision BB. Removed support for Silicon Revision BA and Non-Transparent mode. Applied miscellaneous corrections and enhancements throughout the data book. 3.0 January, 2007 Production release, Silicon Revision BC. 3.1 February, September, 2010 Production release, Silicon Revision BD. Data book now supports Silicon Revisions BC and BD. Rewrote Chapters 1, 3, 12, and 15, and applied many updates to Chapter 14. Reorganized Tables 2-10 and Renamed Chapter 17 to Thermal and Mechanical Specifications. (As a result, Table 17-1 is now Table 17-2, and Table 17-2 is now Table 17-1.) Added Note d to Table Added new Power Characteristics section to Chapter 16 (Section 16.4), and renumbered all subsequent sections accordingly. Changed minimum serial EEPROM size referenced in Section 9.2. Updated Tables 15-2 and Changed minimum storage temperature. Applied miscellaneous corrections and enhancements throughout the data book. Production update, Silicon Revisions BC and BD. Added solder mask opening information to Table Copyright 2010 by PLX Technology, Inc. All Rights Reserved iii

4 Preface PLX Technology, Inc. Preface The information contained in this document is subject to change without notice. This document is periodically updated as new information is made available. Audience This data book provides the functional details of the PLX ExpressLane PEX 8114-BC/BD PCI Expressto-PCI/PCI-X Bridge, for hardware designers and software/firmware engineers. Supplemental Documentation This data book assumes that the reader is familiar with the following documents: PLX Technology, Inc. 870 W Maude Avenue, Sunnyvale, CA USA Tel: (domestic only) or , Fax: , The PLX PEX 8114 Toolbox includes this data book, as well as other PEX 8114 documentation, including the Errata. PCI Special Interest Group (PCI-SIG) 3855 SW 153 rd Drive, Beaverton, OR USA Tel: , Fax: , PCI Local Bus Specification, Revision 2.3 PCI Local Bus Specification, Revision 3.0 PCI Express Card Electromechanical Specification, Revision 1.0a PCI Express Card Electromechanical Specification, Revision 1.1 PCI to PCI Bridge Architecture Specification, Revision 1.1 PCI Bus Power Management Interface Specification, Revision 1.2 PCI Hot Plug Specification, Revision 1.1 PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 PCI-X Addendum to PCI Local Bus Specification, Revision 1.0b PCI-X Addendum to PCI Local Bus Specification, Revision 2.0a PCI Express Base Specification, Revision 1.0a PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 445 Hoes Lane, Piscataway, NJ USA Tel: (domestic only) or , Fax: , IEEE Standard , IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard b-1994, Specifications for Vendor-Specific Extensions IEEE Standard , IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions iv Copyright 2010 by PLX Technology, Inc. All Rights Reserved

5 September, 2010 Supplemental Documentation Abbreviations Supplemental Documentation Abbreviations In this data book, shortened titles are associated with the previously listed documents. The following table defines these abbreviations. Abbreviation Document PCI r3.0 PCI Local Bus Specification, Revision 3.0 PCI Express CEM r1.0a PCI Express Card Electromechanical Specification, Revision 1.0a PCI Express CEM r1.1 PCI Express Card Electromechanical Specification, Revision 1.1 PCI-to-PCI Bridge r1.1 PCI to PCI Bridge Architecture Specification, Revision 1.1 PCI Power Mgmt. r1.2 PCI Bus Power Management Interface Specification, Revision 1.2 PCI Hot Plug r1.1 PCI Hot Plug Specification, Revision 1.1 PCI Standard Hot Plug Controller and Subsystem r1.0 PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 PCI-X r1.0b PCI-X Addendum to PCI Local Bus Specification, Revision 1.0b PCI-X r2.0a PCI-X Addendum to PCI Local Bus Specification, Revision 2.0a PCI Express r1.0a PCI Express Base Specification, Revision 1.0a PCI Express-to-PCI/PCI-X Bridge r1.0 PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 IEEE Standard IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions Data Assignment Conventions Data Width PEX 8114 Convention 1 byte (8 bits) Byte 2 bytes (16 bits) Word 4 bytes (32 bits) DWORD/DWord Copyright 2010 by PLX Technology, Inc. All Rights Reserved v

6 Terms and Abbreviations PLX Technology, Inc. Terms and Abbreviations The following table defines common terms and abbreviations used in this document. Terms and abbreviations defined in the PCI Express r1.0a are not included in this table. Terms and Abbreviations Definition # Active-Low signal. ACK ADB ADQ BAR Bridge, Transparent Cold Reset Completer Cpl CRC CSR DL_Down DLLP DW, DWord ECC EEPROM Endpoint Fundamental Reset Host Hot Reset Acknowledge Control Packet. A control packet used by a destination to acknowledge data packet receipt. A signal that acknowledges signal receipt. Allowable Disconnect Boundary. Allowable Disconnect Quantity. In the PCI Express interface, the ADQ is a buffer size, which is used to indicate memory requirements or reserves. Base Address Register. Provides connectivity from the Conventional PCI or PCI-X Bus system to the PCI Express hierarchy or subsystem. The bridge not only converts the physical bus to PCI Express point-to-point signaling, it also translates the PCI or PCI-X Bus protocol to PCI Express protocol. The Transparent bridge allows the Address domain on one side of the bridge to be mapped into the CPU system hierarchy on the primary side of the bridge. A Fundamental Reset following the application of power. Device addressed by a Requester. Completion Transaction. Cyclic Redundancy Check Configuration Status Register; Control and Status Register; Command and Status Register. Data Link Layer is down (a PCI Express link/port status). Data Link Layer Packet (originate at the Data Link Layer); allow Flow Control (FCx DLLPs) to acknowledge packets (ACK and NAK DLLPs); and Power Management (PMx DLLPs). Double-word. Error Checking and Correction. Electrically Erasable Programmable Read-Only Memory. Device, other than the Root Complex and switches that are Requesters or Completers of PCI Express transactions. Endpoints can be PCI Express endpoints or Conventional PCI endpoints. Conventional PCI endpoints support I/O and Locked transaction semantics. PCI Express endpoints do not. The mechanism of setting or returning all registers and state machines to default/initial conditions, as defined in all PCI Express, PCI, PCI-X and Bridge specifications. This mechanism is implemented by way of the PEX_PERST# Input ball/signal. A Host computer provides services to computers that connect to it on a network. It is considered in charge over the remainder of devices connected on the bus. A reset propagated in-band across a link, using a Physical Layer mechanism (Training Sequence). vi Copyright 2010 by PLX Technology, Inc. All Rights Reserved

7 September, 2010 Terms and Abbreviations Terms and Abbreviations Definition I I/O INCH ITCH Lane Layers CMOS Input. CMOS Bidirectional Input/Output. Ingress Credit Handler. Internal Credit Handler. Differential signal pair in each direction. PCI Express defines three layers: Transaction Layer Provides assembly and disassembly of TLPs, the major components of which are Header, Data Payload, and an optional Digest field. Data Link Layer Provides link management and data integrity, including error detection and correction. Defines the data control for PCI Express. Physical Layer Appears to the upper layers as PCI. Connects the lower protocols to the upper layers. Physical connection between two devices that consists of xn lanes. A x1 link consists of one Transmit and one Receive signal, where each signal is a differential pair. This is one lane. There are four lines or signals in a x1 link. A x4 link contains four lanes or four differential signal pairs for each direction, for a total of 16 lines or signals. A Differential Pair Link This is a x1 Link. There are four signals. One Differential Pair in each direction = one Lane. Four Differential Pairs in each direction = four Lanes. This is a x4 Link. There are 16 signals. Copyright 2010 by PLX Technology, Inc. All Rights Reserved vii

8 Terms and Abbreviations PLX Technology, Inc. Terms and Abbreviations Definition LLIST LVDSRn LVDSRp LVDSTn LVDSTp MSI NAK Non-Posted Request Packet O OD Packet Types PCI PCI PCI-X PEX Port Posted Request Packet PRBS PU RC RCB Requester RoHS Rx Link List. Differential low-voltage, high-speed, LVDS negative Receiver Inputs. Differential low-voltage, high-speed, LVDS positive Receiver Inputs. Differential low-voltage, high-speed, LVDS negative Transmitter Outputs. Differential low-voltage, high-speed, LVDS positive Transmitter Outputs. Message Signaled Interrupt. Negative Acknowledge. Packet transmitted by a Requester that has a Completion packet returned by the associated Completer. CMOS Output. Open Drain Output. There are three packet types: TLP, Transaction Layer Packet DLLP, Data Link Layer Packet PLP, Physical Layer Packet Peripheral Component Interconnect. A PCI Bus is a high-performance, 32- or 64-bit bus. It is designed to use with devices that contain high-bandwidth requirements; for example, the display subsystem. A PCI Bus is an I/O bus that can be dynamically configured. PCI/PCI-X Compliant. Peripheral Component Interconnect Extended. An extension to PCI, designed to address the need for the increased bandwidth of PCI devices. PCI Express. Interface between a PCI Express component and the link, and consists of Transmitters and Receivers. An ingress port receives a packet. An egress port that transmits a packet. Packet transmitted by a Requester that does have a Completion packet returned by the associated Completer. Pseudo-Random Bit Sequence. Signal is internally pulled up. Root Complex. Device that connects the CPU and Memory subsystem to the PCI Express fabric, which supports one or more PCI Express ports. Read Completion Boundary. Device that originates a transaction or places a transaction sequence into the PCI Express fabric. Restrictions on the use of certain Hazardous Substances (RoHS) Directive. Receiver. viii Copyright 2010 by PLX Technology, Inc. All Rights Reserved

9 September, 2010 Terms and Abbreviations Sticky bits STRAP STS Switch TC TLP TP Transparent Bridge TS Tx VC VC&T Terms and Abbreviations Warm Reset Status bits that are reset to default on a Fundamental Reset. Sticky bits are not modified nor initialized by a reset, except a Fundamental Reset. Devices that consume AUX power preserve register values when AUX power consumption is enabled (by way of AUX power or PME Enable). HwInit, ROS, RWCS, and RWS CSR types. (Refer to Table 14-2 for CSR type definitions.) Input Strapping pads must be tied High to VDD33 or Low to VSS on the board. PCI-X Sustained Three-State Output, driven High for One CLK before Float. Device that appears to software as two or more logical PCI-to-PCI bridges. Traffic Class. Translation Layer Packet. Totem Pole. Provides connectivity from the Conventional PCI or PCI-X Bus system to the PCI Express hierarchy or subsystem. The bridge not only converts the physical bus to PCI Express point-to-point signaling, it also translates the PCI or PCI-X Bus protocol to PCI Express protocol. The Transparent bridge allows the Address domain on one side of the bridge to be mapped into the CPU system hierarchy on the primary side of the bridge. Three-State Bidirectional. Transceiver. Virtual Channel. Definition Virtual Channel and Type [P (Posted), NP (Non-Posted), and Cpl (Completion)]. Fundamental Reset without cycling the supplied power. Copyright 2010 by PLX Technology, Inc. All Rights Reserved ix

10 Data Book Notations and Conventions PLX Technology, Inc. Data Book Notations and Conventions Notation / Convention Blue text PEX_XXXn[3:0] PEX_XXXp[3:0] # = Active-Low signals Program/code samples command_done Command/Status Parity Error Detected Description Indicates that the text is hyperlinked to its description elsewhere in the data book. Left-click the blue text to learn more about the hyperlinked information. This format is often used for register names, register bit and field names, register offsets, chapter and section titles, figures, and tables. When the signal name appears in all CAPS, with the primary port description listed first, field [3:0] indicates the number associated with the signal balls/pads assigned to a specific SerDes module/lane. The lowercase p = positive or n = negative suffix indicates the differential pair of signals, which are always used together. Unless specified otherwise, Active-Low signals are identified by a # appended to the term (for example, PEX_PERST#). Monospace font (program or code samples) is used to identify code samples or programming references. These code samples are case-sensitive, unless specified otherwise. Interrupt format. Register names. Register parameter [field] or control function. Upper Base Address[31:16] Specific Function in 32-bit register bounded by bits [31:16]. Number multipliers 1Fh 1010b k = 1,000 (10 3 ) is generally used with frequency response. K = 1,024 (2 10 ) is used for memory size references. KB = 1,024 bytes. M = meg. = 1,000,000 when referring to frequency (decimal notation) = 1,048,576 when referring to Memory sizes (binary notation) h = suffix which identifies hex values. Each prefix term is equivalent to a 4-bit binary value (nibble). Legal prefix terms are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. b = suffix which identifies binary notation (for example, 01b, 010b, 1010b, and so forth). Not used with single-digit values of 0 or 1. 0 through 9 Decimal numbers, or single binary numbers. byte LSB lsb MSB msb DWord Reserved Eight bits abbreviated to B (for example, 4B = 4 bytes) Least-Significant Byte. Least-significant bit. Most-Significant Byte. Most-significant bit. DWord (32 bits) is the primary register size in these devices. Do not modify reserved bits and words. Unless specified otherwise, these bits read as 0 and must be written as 0. x Copyright 2010 by PLX Technology, Inc. All Rights Reserved

11 Contents Chapter 1 Introduction Features PCI Express to PCI/PCI-X Bridge Introduction to PEX 8114 Operation Detailed Block Diagram Transaction Layer Data Link Layer Physical Layer Forward/Reverse Operating Modes Forward Transparent Bridge Mode Reverse Transparent Bridge Mode Applications PCI Express Adapter Board PCI Express Motherboard to PCI-X Expansion Slot PCI-X Host Supporting a PCI Express Expansion Slot PCI-X Add-In Board Created from PCI Express Native Silicon PCI-X Extender Board Chapter 2 Signal Ball Description Introduction Abbreviations Pull-Up Resistors PCI/PCI-X Bus Interface Signals PCI Express Interface Signals Hot Plug Signals Strapping Signals JTAG Interface Signals Serial EEPROM Interface Signals Power and Ground Signals Ball Assignments by Location Ball Assignments by Signal Name Physical Layout Chapter 3 Clock and Reset Introduction to PEX 8114 Clocking PCI/PCI-X Clock Generator Clocking of PCI and PCI-X Modules Clocking PCI and PCI-X Modules with External Clock Clocking PCI and PCI-X Modules with Internal Clock Generator Clocking External PCI/PCI-X Devices Determining PCI Bus and Internal Clock Initialization Bridge Mode and Clocking Functions Determining Bus Mode Capability and Maximum Frequency PCI Clock Master Mode Clock Master Forward Transparent Bridge Mode Clock Master Reverse Transparent Bridge Mode Copyright 2010 by PLX Technology, Inc. All Rights Reserved xi

12 Contents PLX Technology, Inc. 3.4 PCI Clock Slave Mode Clock Slave Forward Transparent Bridge Mode Clock Slave Reverse Transparent Bridge Mode Timing Diagrams Forward or Reverse Transparent Bridge Mode Resets Fundamental Reset (Power-On, Hard, Cold, Warm Reset) PEX_PERST# Fundamental Reset Forward Transparent Bridge Mode Fundamental Reset Reverse Transparent Bridge Mode Hot Reset Hot Reset Forward Transparent Bridge Mode Hot Reset Reverse Transparent Bridge Mode Secondary Bus Reset Secondary Bus Reset Forward Transparent Bridge Mode Secondary Bus Reset Reverse Transparent Bridge Mode Serial EEPROM Load Sequence Chapter 4 Data Path Internal Data Path Description PCI Express Credits Latency and Bandwidth Data Flow-Through Latency PCI Transaction Initial Latency and Cycle Recovery Time PCI-X Transaction Initial Latency and Cycle Recovery Time Arbitration Latency Chapter 5 Address Spaces Introduction Supported Address Spaces I/O Space Enable Bits I/O Base and Limit Registers ISA Mode VGA Mode Memory-Mapped I/O Space Enable Bits Memory-Mapped I/O Base and Limit Registers Prefetchable Space Enable Bits Prefetchable Base and Limit Registers Bit Addressing Base Address Register Addressing Chapter 6 Configuration Introduction Type 0 Configuration Transactions Type 1 Configuration Transactions Type 1-to-Type 0 Conversion Forward Transparent Bridge Mode Reverse Transparent Bridge Mode Type 1-to-Type 1 Forwarding Forward Transparent Bridge Mode Reverse Transparent Bridge Mode PCI Express Enhanced Configuration Mechanism xii Copyright 2010 by PLX Technology, Inc. All Rights Reserved

13 September, 2010 Contents 6.7 Configuration Retry Mechanism Forward Transparent Bridge Mode Reverse Transparent Bridge Mode Configuration Methods Configuration Methods Intent and Variations PCI Express Extended Configuration Method PCI Configuration Cycles BAR0/1 Device-Specific Register Memory-Mapped Configuration Address and Data Pointer Configuration Method Configuration Specifics Forward Transparent Bridge Mode Reverse Transparent Bridge Mode Chapter 7 Bridge Operations Introduction General Compliance PCI-to-PCI Express Transactions PCI-to-PCI Express Flow Control PCI-to-PCI Express PCI Posted Write Requests PCI-to-PCI Express PCI Non-Posted Requests PCI-to-PCI Express PCI Non-Posted Transactions until PCI Express Completion Returns PCI-to-PCI Express PCI Requests Do Not Contain Predetermined Lengths Memory Read Requests to Non-Prefetchable Space Memory Read Requests to Prefetchable Space Memory Read Line or Memory Read Line Multiple Credits PCI-to-PCI Express Disposition of Unused Prefetched Data PCI-to-PCI Express Pending Transaction Count Limits PCI-to-PCI Express PCI Write Transaction with Discontiguous Byte Enables PCI-to-PCI Express PCI Write Transactions Larger than Maximum Packet Size PCI-X-to-PCI Express Transactions PCI-X-to-PCI Express Flow Control PCI-X-to-PCI Express PCI-X Posted Requests PCI-X-to-PCI Express PCI-X Non-Posted Requests PCI-X-to-PCI Express PCI-X Read Requests Larger than Maximum Read Request Size PCI-X-to-PCI Express PCI-X Transfer Special Case PCI-X-to-PCI Express PCI-X Transactions that Require Bridge to Take Ownership PCI-X-to-PCI Express PCI-X Writes with Discontiguous Byte Enables PCI-X-to-PCI Express PCI-X Writes Larger than Maximum Packet Size PCI Express-to-PCI Transactions PCI Express-to-PCI Flow Control PCI Express-to-PCI PCI Express Posted Transactions PCI Express-to-PCI PCI Express Non-Posted Transactions PCI Express-to-PCI PCI Bus Retry PCI Express-to-PCI Transaction Request Size PCI Express-to-PCI Transaction Completion Size Copyright 2010 by PLX Technology, Inc. All Rights Reserved xiii

14 Contents PLX Technology, Inc. 7.6 PCI Express-to-PCI-X Transactions PCI Express-to-PCI-X Posted Writes PCI Express-to-PCI-X Non-Posted Transactions Non-Posted Writes Non-Posted Writes and Reads Transaction Concurrency Transaction Transfer Failures PCI Endpoint Fails to Retry Read Request PCI-X Endpoint Fails to Transmit Split Completion PCI-X Endpoint Allows Infinite Retries PCI Express Endpoint Fails to Return Completion Data Chapter 8 Error Handling Forward Transparent Bridge Error Handling Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) Received Poisoned TLP Received ECRC Error PCI/PCI-X Uncorrectable Data Errors PCI/PCI-X Address/Attribute Errors PCI/PCI-X Master Abort on Posted Transaction PCI/PCI-X Master Abort on Non-Posted Transaction PCI-X Master Abort on Split Completion PCI/PCI-X Target Abort on Posted Transaction PCI/PCI-X Target Abort on Non-Posted Transaction PCI-X Target Abort on Split Completion Completer Abort Unexpected Completion Receive Non-Posted Request Unsupported Link Training Error Data Link Protocol Error Flow Control Protocol Error Receiver Overflow Malformed TLP Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) Received PCI/PCI-X Errors Unsupported Request (UR) Completion Status Completer Abort (CA) Completion Status Split Completion Errors Forward Transparent Bridge Timeout Errors PCI Express Completion Timeout Errors PCI Delayed Transaction Timeout Errors Forward Transparent Bridge SERR# Forwarding Reverse Transparent Bridge Error Handling Reverse Transparent Bridge Forwarding System Errors and System Error Messages Root Port Error Forwarding Control Conventional PCI Type 1 Error Forwarding Control Bridge-Detected Error Reporting xiv Copyright 2010 by PLX Technology, Inc. All Rights Reserved

15 September, 2010 Contents Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) Received Poisoned TLP Received ECRC Error PCI/PCI-X Uncorrectable Data Errors PCI/PCI-X Address/Attribute Errors PCI/PCI-X Master Abort on Posted Transaction PCI/PCI-X Master Abort on Non-Posted Transaction PCI-X Master Abort on Split Completion PCI/PCI-X Target Abort on Posted Transaction PCI/PCI-X Target Abort on Non-Posted Transaction PCI-X Target Abort on Split Completion Unexpected Completion Received Received Request Unsupported Link Training Error Data Link Protocol Error Flow Control Protocol Error Receiver Overflow Malformed TLP Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Received PCI/PCI-X Errors Unsupported Request (UR) Completion Status Completer Abort Completion Status Split Completion Errors Reverse Transparent Bridge Timeout Errors PCI Express Completion Timeout Errors PCI Delayed Transaction Timeout Errors Reverse Transparent Bridge PCI Express Error Messages Chapter 9 Serial EEPROM Introduction Configuration Data Download Chapter 10 Interrupt Handler Introduction Interrupt Handler Features Events that Cause Interrupts INTx# Signaling Message Signaled Interrupts MSI Capability Structure MSI Operation Remapping INTA# Interrupts Chapter 11 PCI/PCI-X Arbiter Introduction Arbiter Key Features Functional Block Diagram Arbiter Usage External Bus Functional Description Detailed Functional Description Bus Parking Hidden Bus Arbitration Address Stepping Copyright 2010 by PLX Technology, Inc. All Rights Reserved xv

16 Contents PLX Technology, Inc. Chapter 12 Hot Plug Support Hot Plug Purpose and Capability Hot Plug Controller Capability Hot Plug Port External Signals Hot Plug Typical Hardware Configuration PCI Express Capability Registers for Hot Plug Hot Plug Interrupts Hot Plug Insertion and Removal Process Operator Actions for Hot Plug Insertion/Removal Hot Plug Insertion Hardware and Software Process Hot Plug Removal Hardware and Software Process Chapter 13 Power Management Power Management Capability Power Management Capability Summary General Power Management Capability Forward Bridge-Specific Power Management Capability Reverse Transparent Bridge-Specific Power Management Capability Device Power Management States D0 Device PM State D3hot Device PM State D3cold Device PM State Link Power Management States PCI Express Power Management Support Chapter 14 Registers Introduction Type 1 Register Map Register Descriptions Type 1 Configuration Space Header Registers Power Management Capability Registers Message Signaled Interrupt Capability Registers PCI-X Capability Registers PCI Express Capability Registers Device-Specific Indirect Configuration Mechanism Registers Device Serial Number Extended Capability Registers Power Budget Extended Capability Registers Virtual Channel Extended Capability Registers Device-Specific Registers Device-Specific Registers Error Checking and Debug Device-Specific Registers Physical Layer Device-Specific Registers Content-Addressable Memory Routing Device-Specific Registers Bus Number CAM Device-Specific Registers I/O CAM Device-Specific Registers Address-Mapping CAM Device-Specific Registers Transaction Layer Ingress Control Device-Specific Register I/O CAM Base and Limit Upper 16 Bits Device-Specific Registers Base Address Shadow Device-Specific Registers Ingress Credit Handler Ingress Credit Handler Threshold Virtual Channel Registers xvi Copyright 2010 by PLX Technology, Inc. All Rights Reserved

17 September, 2010 Contents Internal Credit Handler Virtual Channel and Type Threshold Registers ITCH VC&T Threshold Registers PCI Express Interface Device-Specific ITCH VC&T Threshold Registers PCI-X Interface Device-Specific PCI-X Device-Specific Registers Root Port Registers PCI-X-Specific Registers PCI Arbiter Registers Advanced Error Reporting Capability Registers Chapter 15 Test and Debug Physical Layer Loopback Operation Overview Loopback Test Modes Internal Loopback Analog Loopback Master Digital Loopback Master Analog Loopback Slave Digital Loopback Slave Pseudo-Random and Bit-Pattern Generation JTAG Interface IEEE and Test Access Port JTAG Instructions JTAG Boundary Scan JTAG Reset Input TRST# Chapter 16 Electrical Specifications Introduction Power-On Sequence Absolute Maximum Ratings Power Characteristics Digital Logic Interface Operating Characteristics SerDes/Lane Interface DC Characteristics SerDes Interface AC Specifications Chapter 17 Thermal and Mechanical Specifications Thermal Characteristics Package Specifications Mechanical Dimensions Appendix A Serial EEPROM Map A.1 Serial EEPROM Map Appendix B Sample C Code Implementation of CRC Generator Appendix C General Information C.1 Product Ordering Information C.2 United States and International Representatives and Distributors C.3 Technical Support Copyright 2010 by PLX Technology, Inc. All Rights Reserved xvii

18 Contents PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. xviii Copyright 2010 by PLX Technology, Inc. All Rights Reserved

19 Registers Type 1 Configuration Space Header Registers h Product Identification h PCI Command/Status h Class Code and PCI Revision ID Ch Miscellaneous Control h Base Address h Base Address h Bus Number Ch Secondary Status, I/O Limit, and I/O Base h Memory Base and Limit h Prefetchable Memory Base and Limit h Prefetchable Memory Base Upper 32 Bits Ch Prefetchable Memory Limit Upper 32 Bits h I/O Base and Limit Upper 16 Bits h New Capability Pointer h Expansion ROM Base Address Ch Bridge Control and Interrupt Signal Power Management Capability Registers h Power Management Capability h Power Management Status and Control Message Signaled Interrupt Capability Registers h Message Signaled Interrupt Capability Ch MSI Address h MSI Upper Address h MSI Data PCI-X Capability Registers h PCI-X Capability, Secondary Status Ch PCI-X Bridge Status h Upstream Split Transaction Control h Downstream Split Transaction Control PCI Express Capability Registers h PCI Express Capability List and Capability Ch Device Capability h Device Status and Control h Link Capability h Link Status and Control Ch Slot Capability h Slot Status and Control Device-Specific Indirect Configuration Mechanism Registers F8h Configuration Address Window FCh Configuration Data Window Device Serial Number Extended Capability Registers h Device Serial Number Extended Capability h Serial Number (Lower DW) h Serial Number (Higher DW) Copyright 2010 by PLX Technology, Inc. All Rights Reserved xix

20 Registers PLX Technology, Inc. Power Budget Extended Capability Registers h Power Budget Extended Capability Ch Data Select h Power Budget Data h Power Budget Capability Virtual Channel Extended Capability Registers h Virtual Channel Extended Capability Ch Port VC Capability h Port VC Capability h Port VC Status and Control h VC0 Resource Capability Ch VC0 Resource Control h VC0 Resource Status Device-Specific Registers Device-Specific Registers Error Checking and Debug C8h ECC Check Disable CCh Device-Specific Error 32-Bit Error Status D0h Device-Specific Error 32-Bit Error Mask E0h Power Management Hot Plug User Configuration E4h Egress Control and Status E8h Bad TLP Count ECh Bad DLLP Count F0h TLP Payload Length Count F8h ACK Transmission Latency Limit Device-Specific Registers Physical Layer h Phy User Test Pattern h Phy User Test Pattern h Phy User Test Pattern Ch Phy User Test Pattern h Physical Layer Command and Status h Port Configuration h Physical Layer Test h Physical Layer Port Command h SKIP Ordered-Set Interval h SerDes[0-3] Quad Diagnostics Data h SerDes Nominal Drive Current Select Ch SerDes Drive Current Level h SerDes Drive Equalization Level Select h Serial EEPROM Status and Control h Serial EEPROM Buffer Device-Specific Registers Content-Addressable Memory Routing Device-Specific Registers Bus Number CAM E8h Bus Number CAM Device-Specific Registers I/O CAM h I/O CAM_ Device-Specific Registers Address-Mapping CAM C8h AMCAM_8 Memory Limit and Base CCh AMCAM_8 Prefetchable Memory Limit and Base[31:0] D0h AMCAM_8 Prefetchable Memory Base[63:32] D4h AMCAM_8 Prefetchable Memory Limit[63:32] xx Copyright 2010 by PLX Technology, Inc. All Rights Reserved