1 PC Hardware Basics Microprocessors II PC Hardware Basics Fall 2008 Hadassah College Dr. Martin Land

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2 2 Basic Computer Ingredients Central Processing Unit (CPU) Usually a microprocessor Includes ALU, internal registers, control Cache Memory A copy of a small part of Main Memory Allows fast access to important memory data Main Memory Random Access Memory Stores data and program Bus Adapter Connects Memory Bus to I/O Bus I/O Controller Converts I/O bus data to peripheral device instructions

3 3 Simplified Workstation Layout אפיק זיכרון Memory Bus אפיק ק ל ט/פלט זי כ ר ו ן ר אשי זי כ ר ו ן מטמ ו ן cache memory י ה ידת ה ח ישו ב המ ר כז י Central Processing Unit (CPU) Main Memory (RAM) I/O Bus מתאם אפיק Bus Adapter בקר קלט/פ לט I/O Controller בקר קלט/פ לט I/O Controller בקר קלט/פ לט I/O Controller ממשק Disk משתמש רשת תקשורת communications network

4 4 Device Communication A device "writes" with OE = 1 and "reads" with IE = 1 Von Neumann controller distributes OE and IE signals to devices OE Device A Write IE Device B Read System Bus Write OE Device 2 Read Write IE OE Device 1 Read IE Bus: A vehicle for carrying many passengers Write OE Device 3 Read IE

5 5 Chipsets Collection of related hardware devices Designed to work together efficiently Based on a common Architecture (design plan) Hardware technology (circuit type) Perform I/O and support functions

6 6 Bus-Oriented Mechanical Organization Used in large server systems Separate circuit board (blade) for each function CPU board Memory board I/O board Support board I/O Controller I/O Controller I/O Controller Bus Adaptor Card Memory Card Memory Card CPU Card Central back-plane Usually passive bus Function boards plug into bus system Examples: mainframe computers Backplane

7 7 Single Board Computer Organization Specially designed to fit onto one circuit board Smaller Less flexible Designed for specific physical components Examples Cellular phones PDAs (palm tops) Laptops Special purpose hardware Routers Controllers Toys CPU Subsystem I/O Subsystem Power Supply Single Board Computer Memory Subsystem I/O Controller I/O Controller I/O Controller

8 8 PC is a Compromise Processor, memory, and support hardware on a single board (motherboard) Smaller but less flexible Peripherals plug into expansion bus More choice in choosing components for expansion CPU Subsystem I/O Subsystem Power Supply Motherboard Memory Subsystem I/O Controller Expansion Slot I/O Controller Expansion Slot I/O Controller Expansion Slot I/O Controller Expansion Slot I/O Controller Expansion Slot

9 9 PC Bus Types Address Bus Proprietary Fast Includes data, address, control signals Local Bus (front end bus) Processor data and address lines In this case, between processor and L2 cache I/O bus For expansion addition of peripheral devices Published standard Permit OEM hardware to work with computer OEM = Original Equipment Manufacturer

10 10 Basic Functions on I/O Bus Power to devices Address transfer Data transfer with data buffering for flow control Clock signal to devices for data transfer timing Arbitration for bus mastering (read/write permission) I/O Bus Power Address Data Clock Arbitration

11 11 IBM Proprietary Bus Designs PC bus IBM's original I/O bus Local bus 8-bit data transfer for 8088 AT bus (for 80286) Permits 16-bit data transfers Split 2-part connector Second connector for 8 new data bits First connector maintained compatibility with older cards

12 12 First Standardized Buses ISA Industry Standard Architecture IEEE standardization of the AT bus Standardizes support functions as well as I/O Permits a chipset to handle support and I/O in an integrated fashion EISA Enhanced Industry Standard Architecture Designed by consortium of clone OEMs Looking to block IBM market control Various improvements, such as 32-bit data bus

13 13 Local Bus Display Control Graphics bus connected directly to processor א פי ק זיכ ר ון Memory Bus זיכרון מטמון cache memory זיכרון ר א שי יהידת ה חישוב המ ר כזי Central Processing Unit (CPU) Main Memory (RAM) I/O Bus מת אם א פי ק Bus Adapter א פי ק קלט/פ לט בקר קלט/פ לט I/O Controller בקר קלט/פ לט I/O Controller בקר קלט/פ לט I/O Controller בקר מסך Video Controller רשת תקש ורת communications network ממשק Disk משתמש

14 14 Display Control Requirements Screen memory is (units/screen) (bytes/unit) First PCs used text-oriented screen memory 25 rows of 80 monochrome characters Character represented by one ASCII byte Video memory is = 2000 Bytes/screen Graphics-oriented screen memory Consider 1024 by 768 pixel resolution at 24 bit color = 786,432 pixels/screen Each pixel requires 3-bytes (24 bits) for color Need = 2,359,296 Bytes/screen

15 15 VESA Local Bus Standard VESA - Video Electronics Standards Association Local bus connector in-line with EISA Double-connector made for screen card Special Driver required for local bus access

16 16 PCI Peripheral Component Interface Intel standard PCI Bridge replaces the I/O Adapter Controls all processor accesses PCI brings standardization to the memory bus

17 17 PCI Layout אפיק זיכרון Memory Bus Host PCI Bridge זיכרון ראשי Main Memory (RAM) זיכרון מטמון cache memory PCI bus יהידת החישוב המרכזי Central Processing Unit (CPU) ISA/EISA bus adapter PCI Graphics Adapter בקר קלט/פלט I/O Controller ממשק משתמש רשת תקשורת communications network Disk

18 18 Overview of ISA Bus

19 19 ISA Block Diagram systems kernel memory subsystem cache bus controller ROM RAM CPU X-bus ISA subsystem expansion bus keyboard mouse controller DMA controller interrupt controller Real Time clock and timers etc controller audio controller graphics controller network controller

20 20 ISA Subsystems Kernel: processor, bus control logic, electrical interface circuitry Memory Subsystem: RAM and ROM ISA Subsystem: Expansion (I/O) slots System functions X-bus Real time clock PIC Programmable interrupt controller DMA controller IRQ interrupt controller Keyboard controller Each device has its own I/O address

21 21 Address bus Data bus Control bus CPU I/O Structures Read/write (direction) Timing (clock) 8 MHz Interrupts

22 22 PC-AT Memory Map Upper Memory Above KB boot ROM F0000 to FFFFF 64 KB option ROM E0000 to EFFFF 128 KB device ROM C0000 to DFFFF 128 KB video memory A0000 to BFFFF 640 KB DOS program memory to 9FFFF Extended Memory Conventional Memory

23 23 PC-XT Data Path 16-bit data transfers Processor addresses 2 bytes with one low order address Lower data path I/O lines D0 to D7 Transfer bytes to/from even memory address Upper data path I/O lines D8 to D15 Transfer bytes to/from odd memory address I/O Bus Power Even Odd Address Clock Arbitration Data Data

24 Data Path Addresses 2 32 B = 4 GB 32-bit address: A31 A30 A3 A2 A1 A0 Processor addresses 4 bytes at one time Processor uses only 30 address lines A31 to A2 Generates address A31 A30 A3 A2 0 0 Access address is always a multiple of 4 = Memory management unit provides 4 bytes from addresses: A31 A30 A3 A2 0 0 A31 A30 A3 A2 0 1 A31 A30 A3 A2 1 0 A31 A30 A3 A2 1 1

25 25 Multiplexed DRAM Organization Use n/2 address lines for an n-bit memory chip Send address to chip in two transfer cycles Saves money in making chips Permits large inexpensive RAM Longer access time Example: 16 MB chip needs 24 address bits Multiplexing uses 12 address lines First, send Upper 12 bits of address Second, send Lower 12 bits of address

26 26 Internal Memory Chip Function RAS Row Address Strobe (first) CAS Column Address Strobe (second) RAS activates all columns in a row CAS chooses one column from selected row Chip response time (latency) spread over entire row RAS CAS bit Address = h RAS = 002 h CAS = 004 h

27 27 Interleaved Memory Arrange memory as an array of RAM chips Divide memory into banks (columns) Addressing one bank prepares next bank Chip response time distributed over banks Called burst mode read access A 1 A A n A n-1... A 2

28 28 Basic RAM Technologies Static RAM (SRAM) Several transistors per memory bit One multi-transistor flip-flop per bit Stable Fast and Expensive Level-Sensitive Latch D Q Level Edge-Sensitive Latch D Q Dynamic RAM (DRAM) Capacitor and 1 transistor per memory bit Stored data leaks from capacitor Data refreshed periodically Slower and cheaper than SRAM Data I/O Write Enable CLK CMOS Transistor Capacitor

29 29 Square array of memory cells DRAM Organization Multiplexed addressing (RAS/CAS) 2-to-4 decoder RAS A0 A1 R/W Switch A2 A3 4-to-1 Multiplexor and Tri-State Latch CAS Data In/Out

30 30 Memory array 16 1-bit memory cells 4-bit address A0 A1 A2 A Multiplexed addressing (RAS/CAS) DRAM Read 1 2-to-4 decoder Read address 0110 RAS = 01 CAS = 10 R/W = R RAS A0 = 0 A1 = 1 R/W = R Switch A2 = 1 A3 = 0 4-to-1 Multiplexor and Tri-State Latch CAS Data In/Out

31 31 Read address 0110 RAS = 01 CAS = 10 R/W = R DRAM Read 2 2-to-4 decoder RAS = 01 enables 1 row 4 cells in row 01 RAS = 1 send bit to mux Multiplexor (mux) saves 4 bit values A0 = 0 A1 = 1 R/W = R Switch A2 = 1 A3 = 0 CAS = 0 4-to-1 Multiplexor and Tri-State Latch Data In/Out

32 32 Read address 0110 RAS = 01 CAS = 10 R/W = R DRAM Read 3 2-to-4 decoder CAS = 10 enables 1 column Mux provides 1 bit from 4 stored bits RAS = 0 A0 = 0 A1 = 1 11 R/W = R Switch A2 = 1 A3 = 0 CAS = 1 4-to-1 Multiplexor and Tri-State Latch Data In/Out

33 33 Read address 0111 RAS = 01 CAS = 11 R/W = R DRAM Read 4 2-to-4 decoder CAS = 11 enables 1 column Mux provides 1 bit from 4 stored bits RAS = 0 A0 = 0 A1 = 1 11 No latency on second bit read from row R/W = R A2 = 1 A3 = 1 CAS = Switch 4-to-1 Multiplexor and Tri-State Latch Data In/Out

34 34 Memory array 16 1-bit memory cells 4-bit address A0 A1 A2 A Multiplexed addressing (RAS/CAS) DRAM Write 1 2-to-4 decoder Write address 0110 RAS = 01 CAS = 10 R/W = W RAS A0 = 0 A1 = 1 R/W = W Switch A2 = 1 A3 = 0 4-to-1 Multiplexor and Tri-State Latch CAS Data In/Out

35 35 Write address 0110 RAS = 01 CAS = 10 R/W = W RAS = 01 enables 1 row 4 cells in row 01 RAS = 1 enabled for write A0 = 0 A1 = 1 DRAM Write 2 2-to-4 decoder Input 1 bit stored in mux R/W = W Switch A2 = 1 A3 = 0 CAS = 0 4-to-1 Multiplexor and Tri-State Latch Data In/Out

36 36 Write address 0110 RAS = 01 CAS = 10 R/W = W DRAM Write 3 2-to-4 decoder CAS = 10 enables 1 column Row enabled until R/W R Mux provides bit for write to enabled row RAS = 0 A0 = 0 A1 = 1 R/W = W Switch A2 = 1 A3 = 0 4-to-1 Multiplexor and Tri-State Latch CAS = 1 Data In/Out

37 37 Write address 0110 RAS = 01 CAS = 10 R/W = W DRAM Write 4 2-to-4 decoder CAS = 11 enables 1 column Mux provides another bit for write to enabled row RAS = 0 A0 = 0 A1 = 1 R/W = W Switch A2 = 1 A3 = 0 4-to-1 Multiplexor and Tri-State Latch CAS = 1 Data In/Out

38 38 DRAM Read To Read one memory cell MMU Control Circuit Sets Read direction Writes Row Number on DRAM Address Pins Sets RAS (row address select) pin DRAM Reads Row Address Connects selected Row to sense amplifiers (comparators) Latches contents of Row into selector (4-to-1 MUX) MMU Control Circuit Places Column Number on DRAM Address Pins Sets CAS (column address select) pin DRAM Reads Column Address Selector chooses one output according to CAS Output data presented on DRAM Data I/O pin

39 39 DRAM Write To Write one memory cell MMU Control Circuit DRAM Sets Write direction Input data presented to DRAM on Data I/O pin Writes Row Number on DRAM Address Pins Sets RAS (row address select) pin Reads Row Address Connects selected Row to selector (4-to-1 MUX) Latches Data I/O into selector MMU Control Circuit DRAM Places Column Number on DRAM Address Pins Sets CAS (column address select) pin Writes latched Data I/O to selected Column Address

40 40 DRAM Refresh On Read of any cell Entire row is Read and Refreshed (written back) On Write to any cell Entire row is Read Value Updated for Write cell Updated Row is written back in Refresh logic automates the periodic refresh Refresh every 64 ms or less

41 41 Multi-bit DRAM devices Four or eight bits (nibble or byte) per device Multiple storage arrays operating in parallel Each array attached to single Data I/O pin Multiple bits transferred on each read or write Equivalent to multiple one-bit DRAMs operating in tandem Uses less space All arrays share address and control pins 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder RAS RAS RAS RAS A0 A0 A0 A0 A1 A1 A1 A1 R/W Switch R/W Switch R/W Switch R/W Switch A2 A3 4-to-1 Multiplexor and Tri-State Latch A2 A3 4-to-1 Multiplexor and Tri-State Latch A2 A3 4-to-1 Multiplexor and Tri-State Latch A2 A3 4-to-1 Multiplexor and Tri-State Latch CAS Data In/Out CAS Data In/Out CAS Data In/Out CAS Data In/Out 16-cell 4-bit memory array

42 42 Advances on DRAM Fast Page Mode DRAM (1992) Automated interleaving Column counter increments across Row Extended Data Out (EDO) DRAM (1993) Fast Page Mode DRAM with pipelining New transfer started when current transfer active Synchronous Dynamic (SDRAM) RAM (1997) Internal DRAM operations are fully pipelined Synchronized to external clock Divided into multiple execution stages Transfers begun while current transfer active Performs one data transfer per clock cycle Pipelining cuts access latency

43 43 Double Data Rate (DDR) SDRAM Introduced to PC in 2000 DDR SDRAM performs two data transfers per clock cycle Transfers data on rising clock and falling clock Effectively doubles bandwidth without higher clock frequency Implemented by Data transfers buffered at I/O interface Internal pipelining of data accesses in DRAM Automated column interleaving Called prefetch DDR-II "Quad-Pumped Four data transfers per clock cycle Column Row I/O Buffer

44 44 Standard Speeds for DDR SDRAM Memory Clock (MHz) DDR2 (MB/s) DDR3 (MB/s)

45 45 Interrupts x86 has hardware/software interrupts 0 to 255 Software interrupts controlled by: Machine instruction INT int_number Fetches CS:IP vector from address int_number 4 Hardware interrupts controlled by: int_number on data bus signals D0 to D7 INTR (input control signal to processor) IRQ Interrupt Requests reserved for I/O hardware

46 46 Interrupt Controller Programmable Interrupt Controller (PIC) Pair of 8-input controllers in Master/Slave configuration Master controls Slave over Cascade Bus Master enables Slave outputs to processor data bus Receives 15 defined IRQs 8 interrupt inputs from Slave and 7 interrupt inputs from Master Translates IRQ into specific INTR, INT signals

47 47 Interrupt Controller Layout 8259 Master PIC IR 0 IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 INTR INT # INTR CPU D0 to D Slave PIC IR 0 IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 INTR INT # Cascade Bus

48 48 IRQ to CPU Hardware INT Table IRQ Line CPU Interrupt DOS Assignment 0 08 System Timer 1 09 Keyboard 2 0A (XT) cancelled (AT) 3 0B COM2/COM4 4 0C COM1/COM3 5 0D Reserved/Sound Card 6 0E Floppy Disk Controller 7 0F LPT 8 70 Real Time Clock Reserved Reserved PS/2 Mouse Math Co-Processor Hard Disk Drive Reserved

49 49 DMA Direct Memory Access Peripheral device accesses memory directly No need for CPU to execute IN/OUT or MOV instructions CPU can work systems kernel memory subsystem with cache at the same time cache Used for large bus controller ROM RAM CPU data transfers ISA subsystem X-bus expansion bus keyboard mouse controller DMA controller interrupt controller Real Time clock and timers etc controller audio controller graphics controller network controller

50 50 DMA Operation CPU sets up DMA transfer with instruction to DMA controller Start address Number of bytes to transfer DMA controller Becomes master of data path (X-Bus to Bus Controller to Memory Bus) Transfers data between RAM and peripheral device IRQ at end of transfer CPU takes back control of the bus

51 51 I/O Ports Parallel Port Assigned to device drivers LPT1 LPT4 Used for printer I/O 25-pin connector 9-bit input 12-bit output Serial Port Assigned to device drivers COM1 COM4 Used for mouse, modem, other bit-serial I/O 25-pin or 9-pin connector 1-bit data I/O 6-pin control I/O (RS-232C control signals)

52 52 I/O Ports Parallel Port CPU bus controller RAM Data Port Status 25 pin connector Port Control Serial Port Data Port Status Port Control Modem Status 9 or 25 pin connector Modem Control

53 53 Parallel Port Hardware port implemented in ISA chipset I/O Bus I/O data buffer Control hardware Driver Resources Device port base addresses LPT1: 0378h LPT2: 0278h Base+0: 8-bit I/O data port Base+1: Status port Base+2: Control port IRQ generally not used by Microsoft General Operation (Data Write) Host writes 8-bits to data port (base address) Host checks device not Busy (status port) Host asserts Strobe (control port) Host checks peripheral ACK (status port) Port Address = 0378 data Port Address = 0379 status Port Address = 037A control Parallel Interface Hardware Peripheral Device Controller Data Status Control Printer

54 54 Serial Port Hardware port implemented in ISA chipset Control hardware I/O data buffer FIFO buffer Universal Asynchronous Receiver / Transmitter (UART) Parallel-to-Serial output Serial-to-Parallel input UART Registers FIFO I/O bus UART Address Function Address Function Address Function Base+0 I/O byte Base+0* Bit Rate (L) Base+4 Modem Control Base+1 Interrupt Enable Base+1* Bit Rate (H) Base+5 Line Status Base+2 Interrupt ID (R) Base+2 FIFO (W) Base+6 Modem Status Base+3 Line Control Base+7 Scratch byte Port Base Address COM 1 03F8 4 COM 2 02F8 3 COM 3 03E8 4 COM 4 02E8 3 * DLAB bit (bit rate control) set in Line Control Register bits IRQ serial port

55 55 Serial Port and RS-232-C RS-232-C serial bit stream FIFO I/O bus byte UART control bits serial port MODEM telephone line RS-232-C defines signals between computer serial port and modem Control bits Data Terminal Ready DTR Computer is up and running Data Set Ready DSR MODEM is up and running Ring Indicator RI Incoming call to MODEM Carrier Detect RLSD MODEM is connected to destination Request To Send RTS Computer has data to send Clear to Send CTS Computer can send data

56 56 Overview of PCI Bus

57 57 Review of Bus Evolution In ISA standard CPU talks to cache via local bus Cache talks to memory via memory bus CPU talks to bus adapter via local bus In VESA (Local Bus) standard Extension of ISA: CPU talks directly to graphics controller via local bus In PCI CPU talks to bus controller via local bus Bus controller (PCI bridge) talks to memory Bus controller talks to main system bus

58 58 PCI Features PCI standardizes: Peripheral I/O bus Memory bus (via bridge) Interrupt and DMA functions provided in bridge PCI peripheral devices can become bus master Expansion bus Fast PCI slots Slower ISA slots (before Pentium 4)

59 59 PCI Bus Speeds Bytes/cycle Bus Clock Transfer Speed Rate PCI MHz 133 MB/s PCI MB/s 66 MHz MB/s MB/s 66 MHz MB/s PCI-X MB/s 133 MHz GB/s MHz GB/s MHz GB/s Memory bus can multiply PCI rate for faster speeds Peripheral I/O bus can divide PCI rate for slower speeds

60 60 Basic PCI Organization PCI Host-to-Bus Bridge (bus controller) ROM RAM CPU PCI (expansion) bus etc controller audio controller grap hics controller network controller ISA/EISA controller (Bridge) ISA/EISA bus ISA disk controller other ISA device

61 61 Accelerated Graphics Port (AGP) PCI Host-to-Bus Bridge (bus controller) ROM RAM Dedicated path from PCI Bridge to display card CPU etc controller audio controller PCI (expansion) bus graphics controller network controller ISA/EISA controller (Bridge) Provides 525 MB/s graphics path for a 133 MHz PCI bus AGP at 525 MB/s for 133 MHz PCI ISA disk controller ISA/EISA bus other ISA device

62 62 PCI Chipset Organization Bridge segmented as Memory Hub I/O Hub Memory hub RAM AGP I/O hub Hard disk drive IDE (Integrated Device Electronics) ATA AT Attachment SATA Serial ATA PCI Slots USB Port

63 63 Bus Segmentation PCI bus segments operate independently PCI-to-PCI bridge interconnects PCI segments Segments may operate with different speeds and other parameters Permits load balancing among devices PCI Host-to-Bus Bridge (bus controller) ROM RAM CPU PCI (expansion) bus PCI-to-PCI Bridge PCI (expansion) bus audio controller graphics controller network controller ISA/EISA controller (Bridge) controller controller controller AGP ISA (expansion) bus

64 64 Intel PCI Express Shared bus replaced by switch Non-blocking communication

65 65 System Boot Hardware system is started or reset Processor performs self-check Processor fetches instruction from address FFFF0h Address FFFF0h must point to ROM Address FFFF0h must contain a JMP instruction Target of JMP must be BIOS (in ROM) BIOS = BASIC INPUT/OUTPUT SYSTEM BIOS Locates keyboard, display, boot device Begins loading Operating System from boot device ROM = Read Only Memory E 2 PROM = Electrically Erasable Programmable ROM

66 66 Basic Input/Output System (BIOS) Specific to individual computer hardware Provided by Chipset manufacturer Contains default hardware-dependent drivers Console display and keyboard (CON) Line printer (PRN) Auxiliary device (AUX) Date and time (CLOCK$) Boot disk device (block device)

67 67 Device Drivers Software routines for hardware devices Devices are controlled by electrical signals Device controllers convert received digital codes to electrical signals Device drivers convert user instructions into digital codes Device driver provides user with a standard interface of instructions Operating System Instruction Driver Codes Device Controller Signals Device

68 68 Device Drivers User program makes call to OS example: read data from serial modem OS converts system call to instruction sequence Read data = disable interrupts, configure COM1, check device status, set RS-232C control status, enable FIFO interrupt, receive interrupt, while not empty FIFO {read byte from FIFO to software buffer}, reset FIFO interrupt Driver converts instruction sequence to code sequence Read byte = out 03f9,0000, Processor executes instruction sequence

69 69 Driver Types Resident Drivers built into the BIOS Installable Installed at System boot time Application run time Processes under UNIX/Linux DEVICE commands in CONFIG.SYS file (DOS) DLLs and VxDs under Windows

70 70 Hard Disk Physical Organization Track Concentric circle Sector Section of a track Usually 512 bytes platter 2 platter 1 platter 0 seek head 0 head 1 tracks sectors cylinder read/write heads rotate Side View read/write head platter rotate Cylinder Tracks read at head position Top View

71 71 Hard Disk Utilization Order Data write order Platter head track sector Fills track 0 (outer diameter) of disc 0 (bottom platter) head 0 Fills track 0 (outer diameter) of disc 0 (bottom platter) head 1 Fills track 0 (outer diameter) of disc 1 (next platter) head 0 Fills track 0 (outer diameter) of disc 1 (next platter) head 1... Fills track 0 (outer diameter) of top platter head 0 Fills track 0 (outer diameter) of top platter head 1 Fills track 1 (outer diameter) of disc 0 (bottom platter) head 0 Fills track 1 (outer diameter) of disc 0 (bottom platter) head 1...

72 72 Hard Disk Logical Organization Master Boot Record (MBR) First sector of a physical disk Defines logical partitions (volumes) on physical disk MBR maps start and stop sectors for each partition Each partition allocated logical drive letter or name MBR may also contain bootstrap code (to load OS) Allocation Units (Clusters) Collection of adjacent sectors OS allocates disk space by cluster (not sector) File Collection of clusters assigned a file name File Directory Table of file information Name, attributes, time, date, starting cluster, size File Allocation Table (FAT) Index = current cluster number Entry = next cluster number

73 73 Microsoft FAT File Systems FAT12 Used on floppy diskettes 512 byte clusters and 2,847 usable clusters (1,457,664 bytes) FAT16 Used on older (DOS/Win95) hard disks 16-bit cluster number up to 64 K clusters Up to 64 sectors per cluster 32 KB / cluster 64 K clusters 32 KB / cluster = 2 GB per partition A 1-byte file occupies 32 KB on disk FAT32 Available with Win98/2k/XP 32-bit cluster number (28-bit number implemented) Standard 4 KB / cluster disk size = = 2 40 B = 1 TB Practical partition size limit: maximum 4 M clusters / FAT 4 M clusters 32 KB / cluster = 128 GB

74 74 NTFS NT File System Available on WinNT/2k/XP Based on UNIX file system (not FAT) Sophisticated non-fat features Abstract organization for fast access File system records owner File quotas per user Access rights Encryption control

75 75 Overview of USB Universal Serial Bus Controlled by USB port hardware Attached through I/O bus BIOS support on newest machines Requires Operating System intervention USB Features Complex networking protocol Hierarchical tree topology Host Hub(s) Device(s) Plug n Play with Hot Swap USB Speeds High Speed (USB 2.0) 480 Mbps Full Speed 12 Mbps Low Speed 1.5 Mbps

76 76 USB Host Controller Interface Specifications USB 1.1 UHCI (Universal Host Controller Interface) Developed by Intel Puts more burden on software Simpler hardware OHCI (Open Host Controller Interface) Developed by Compaq, Microsoft and National Semiconductor Puts more burden on hardware Simpler software USB 2.0 EHCI (Enhanced Host Controller Interface)

77 77 Plug n Play Dynamically loadable and unloadable drivers User plugs device into bus Host Detects new device hardware Interrogates device Loads appropriate driver User not involved with IRQs and port addresses User disconnects Removes cable or device Host detects absence of hardware Unloads driver OS identifies driver using Descriptors stored in Device SNMP-type database hierarchy PID/VID (Product ID/Vendor ID) VID supplied by USB Implementer s forum at a cost

78 78 Connectors Device has upstream connection to Host Type A plugs face upstream Type A sockets on Hosts and Hubs Host has downstream connection to Device Type B plugs face downstream Type B sockets on devices Receptacle Type A Receptacle Type B Pin Number Cable Color Function Description 1 Red V BUS (5 volts) Provides power to Devices 2 White D- Non Return to Zero Invert 3 Green D+ (NRZI) encoded Data 4 Black Ground Reference

79 79 Low power bus Supplying Power to Device Draws all its power from V BUS Can draw up to one unit load (100mA) High power bus Draw all its power from bus Can draw up to one unit load before configuration During configuration may request up to 5 unit loads (500mA) Self power functions May draw up to one unit load from bus Derives most power from external source If external source fails, cannot draw more from bus

80 80 USB Protocol Overview Polling Host initiates all communications Host polls attached Devices on some schedule Socket-type protocol Address: Device attached to Host Endpoint: Buffer associated with a software function in Device Connection-oriented Pipe: Mapping of Host to Address:Endpoint Transaction oriented Host sends Token packet to set up communication channel (pipe) Determines source, destination, and message type Source (Host or Device) sends Data Packet Destination sends Status Packet (ACK/NACK/STALL)

81 81 USB Function Model Device has single Address Address contains one or more Endpoints Endpoint buffers I/O for a Function Element Endpoint is data source or destination in Device All Devices support EP0 for control and status

82 82 USB Descriptor Hierarchy

83 83 Enumeration Process of determining What Device has connected to bus What parameters it requires Power consumption Number Type of endpoint(s) Class of product Host Assigns Device address Enables configuration Allows Device to transfer data on bus

84 84 Standard Windows Enumeration Common to Windows 98SE/2000/XP Host Detects connection of new Device Waits 100ms for plug insertion and power to stabilize Issues reset placing Device in default state Device responds on default address zero Host requests first 64 bytes of Descriptor set Device starts sending Descriptors Host Issues another bus reset after receiving 8 bytes of Device Descriptor Issues a Set Address command Requests entire 18 bytes of the Device Descriptor Requests 9 bytes of Configuration Descriptor to determine overall size Requests 255 bytes of the Configuration Descriptor Requests String Descriptors Uses Descriptors to locate appropriate driver