INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

Transcription

1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 16 Title: - Technology, Organization and Summary: ; DRAM memories operation; Memory planes; Primary memory access optimization. 2010/2011 Nuno.Roma@ist.utl.pt

2 Architectures for Embedded Computing : Technology, Organization and Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 34 Previous Class In the previous class... Code optimization: Data access; Program access; Reduction of miss penalty with parallel techniques: Pre-Fetching; Non-blocking caches. Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 34

3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 34 Summary Today: : ; DRAM memories operation; Memory planes; Primary memory access optimization. Bibliography: Computer Architecture: a Quantitative Approach, Section 5.3 Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 34

4 Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 34 Interconnection Between the Processor and Memory Control Bus c Address Bus µp Memory m Data Bus n Memory Controller: manages the processor s interface with the memory system. Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 34

5 Memory Write Cycle Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 34 Memory Read Cycle Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 34

6 Access and Cycle Time Access time: amount of time between a read/write request and the instant when the requested word is read/written. Cycle time: minimum amount of time between two consecutive memory requests. Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 34 Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 34

7 Types of Memory RAM: Random Access Memory SRAM: static memory - 6 transistors per memory bit Advantage: fast and low consumption DRAM: dynamic memory - 1 transistor per memory bit Advantage: capacity and cost ROM: Read-Only Memory - 1 transistor per memory bit Advantage: non-volatile and cheap Flash: Flash memory - 1 transistor per memory bit Advantage: non-volatile and writable Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 34 Types of Memory Memory Price Time Read Write Access SRAM DRAM ROM Flash /850 When is DRAM used? When more memory is more important than better memory. Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 34

8 Types of Memory Static RAM - SRAM: Implemented with only 6 transistors; The state is kept while the power supply is on; Very fast memory: usually adopted by L1 caches, directly coupled with the processor. Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 34 Types of Memory L1 cache, implemented with SRAM technology, directly coupled with the processor. Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 34

9 Types of Memory Dynamic RAM - DRAM: Implemented with only 1 transistor; Needs to be periodically refreshed (8-64ms); Slower read and write cycles than SRAM memories; Advantages: More regular and simple Greater capacity; A lot cheaper!!! Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 34 DRAM Memory Structure Addresses are supplied in two halves: RAS, Row Access Strobe CAS, Column Access Strobe Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 34

10 DRAM Memory Structure Addresses are supplied in two halves: RAS, Row Access Strobe CAS, Column Access Strobe The memory cells are structured as an array (usually square); Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 34 DRAM Memory Structure Addresses are supplied in two halves: RAS, Row Access Strobe CAS, Column Access Strobe The memory cells are structured as an array (usually square); Sense Amplifier - distinguishes the logic level that is stored in each cell. Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 34

11 DRAM Memories Refresh 1 transistor per memory bit: The saved value vanishes with time; A read operations clears the data; Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 34 DRAM Memories Refresh The capacitor discharging effect implies the usage of refreshing mechanisms: Periodically, row-by-row (typically, within each 8ms, < 5%); A read operation discharges C: it is necessary to refresh the memory cell after each read operation; During the refresh, it is not possible to access the memory. Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 34

12 DRAM Memories Refresh The capacitor discharging effect implies the usage of refreshing mechanisms: Periodically, row-by-row (typically, within each 8ms, < 5%); A read operation discharges C: it is necessary to refresh the memory cell after each read operation; During the refresh, it is not possible to access the memory. Significant variations of the access/cycle times! Read and write cycles are slower than in SRAM memories. Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 34 DRAM Access Cell selection: RAS: Row Address Selection CAS: Column Address Selection Multiplexed address lines: RAS + CAS There is little to do, in what concerns the latency Alternative: improve the throughput Fast Page Mode: keeps the row address and changes the column address (Extended Data Output (EDO) DRAM is an optimization of this mode). Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 34

13 Synchronous DRAM (SDRAM) Synchronous DRAM (SDRAM): Synchronous access to the memory, i.e., the memory executes operations synchronously with a clock signal (e.g. PC133), allowing a pipeline operation, i.e., an operation can be started before the previous one has finished. Data bus with 8 bytes (64 bits) width. Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 34 Synchronous DRAM (SDRAM) Access cycle: t RCD - RAS to CAS delay CL - CAS latency Allows reading 2, 4 or 8 words in a single read operation, without needing to repeat the RAS/CAS sequence; Allows reading other columns (different CAS) of the same row (equal RAS). Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 34

14 Technology Evolution of SDRAM Memories Single Data Rate (SDR) SDRAMs: The data bus operating frequency defines the memory reading rate. Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 34 Technology Evolution of SDRAM Memories Single Data Rate (SDR) SDRAMs: The data bus operating frequency defines the memory reading rate. Double Data Rate (DDR1) SDRAMs: Data elements are transferred in both edges of the clock signal, by adopting the same operating frequency than the data bus. Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 34

15 Technology Evolution of SDRAM Memories DDR2 SDRAMs: The data bus operating frequency is doubled, and the data elements are transferred in both edges of the clock signal. Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 34 Technology Evolution of SDRAM Memories DDR2 SDRAMs: The data bus operating frequency is doubled, and the data elements are transferred in both edges of the clock signal. DDR3 SDRAMs: The data bus operating frequency is four times faster, and the data elements are transferred in both edges of the clock signal. Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 34

16 SDRAM Memory Nomenclature Example: DDR2-667 Clock Rate = 333 MHz Transfer Rate = Clock Rate 2 = 667 Mega transfers per second Bandwidth = 8 Bytes Transfer Rate = 5336 MB/sec DIMM name = PC5300 Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 34 Other Memories: FLASH Memory Non-volatile memory: does not need a power supply to keep its contents; Based on the same technology as EEPROMs; Can be erased and re-written multiple times; Relatively high access times (when compared with DDR SDRAM). Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 34

17 Other Memories: Solid State Disk (SSD) Non-volatile; Based on FLASH or SDRAM (with battery) memories; Have been replacing the magnetic discs; Mechanically much more resistant; Greater access times than SDRAM, but much smaller than a HDD. Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 34 Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 34

18 Usually, memory devices with the exact amount of needed cells are not available. Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 34 Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 34

19 Example: FFFFFh RAM F0000h... 1FFFFh RAM 10000h 07FFFh 00000h... ROM Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 34 Next Class Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 34

20 Cache-Memory Interconnect Optimization The processor is connected to the memory using a bus; Next Class Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 34 Cache-Memory Interconnect Optimization Next Class The processor is connected to the memory using a bus; The bus clock frequency is usually much lower than the processor internal operating frequency (about 10 times); Increase of the miss penalty!!! Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 34

21 Cache-Memory Interconnect Optimization Next Class The processor is connected to the memory using a bus; The bus clock frequency is usually much lower than the processor internal operating frequency (about 10 times); Increase of the miss penalty!!! Memory access cycle example: 1 clock cycle to send the address; 15 clock cycles to start each DRAM access; 1 clock cycle to send each word from memory. Considering a cache with 4 words per block, the miss penalty is given by: t p = = 65 bus cycles. Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 34 Cache-Memory Interconnect Optimization Next Class The processor is connected to the memory using a bus; The bus clock frequency is usually much lower than the processor internal operating frequency (about 10 times); Increase of the miss penalty!!! Memory access cycle example: 1 clock cycle to send the address; 15 clock cycles to start each DRAM access; 1 clock cycle to send each word from memory. Considering a cache with 4 words per block, the miss penalty is given by: t p = = 65 bus cycles. Alternatives: Wider bus to connect the memory; Interleaved memory banks. Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 34

22 Cache-Memory Interconnect Optimization Next Class Alternatives: Simple bus to connect the memory (1 word); Wider bus to connect the memory (several words); Interleaved memory banks. Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 34 Cache-Memory Interconnect Optimization Next Class Alternatives: Simple bus to connect the memory (1 word); Wider bus to connect the memory (several words); Interleaved memory banks. Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 34

23 Cache-Memory Interconnect Optimization Next Class Alternatives: Simple bus to connect the memory (1 word); Wider bus to connect the memory (several words); Interleaved memory banks. Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 34 Next Class Next Class Prof. Nuno Roma ACE 2010/11 - DEI-IST 33 / 34

24 Next Class Next Class Virtual Memory: Advantages of secondary memory; Segments vs Pages; Address translation: Hierarchy tables; Inverted tables. Prof. Nuno Roma ACE 2010/11 - DEI-IST 34 / 34