7. External Memory Interfaces in HardCopy IV Devices

Transcription

1 March 2012 HIII External Memory Interfaces in HardCopy IV evices HIV This chapter describes the hardware features that support high-speed memory interfacing for each double data rate (R) memory standard in HardCopy IV devices. HardCopy IV devices feature delay-locked loops (LLs), phase-locked loops (PLLs), dynamic on-chip termination (OCT), read-and-write leveling, and deskew circuitry. This chapter contains the following sections: Memory Interfaces Pin Support on page 7 4 HardCopy IV External Memory Interface Features on page 7 22 Similar to the Stratix IV I/O structure, the HardCopy IV I/O structure has been redesigned to provide flexible and high-performance support for existing and emerging external memory standards. These include high-performance R memory standards such as R3, R2, R SRAM, RII+, RII SRAM, and RLRAM II. HardCopy IV devices offer the same external memory interface features found in Stratix IV devices. These features include LLs, PLLs, dynamic OCT, trace mismatch compensation, read-and-write leveling, deskew circuitry, half data rate (HR) blocks, 4- to 3-bit group widths, and R external memory support on all sides of the HardCopy IV device. HardCopy IV devices provide an efficient architecture to quickly and easily fit wide external memory interfaces with the small modular I/O bank structure. 1 HardCopy IV devices are designed to support the same I/O standards and implementation guidelines for external memory interfaces as Stratix IV devices. In addition, the uartus II timing analysis tool (Timeuest Timing Analyzer) provides a complete solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT) variations. 1 PLL reconfiguration is not required for AltMEMPHY-based designs. The AltMEMPHY megafunction has an auto calibration feature so implementing PLL reconfiguration does not add value. f For more information about the ALTMEMPHY megafunction, refer to the External Memory Interface Handbook. Altera recommends enabling the PLL reconfiguration feature and the LL phase offset feature (LL reconfiguration) for HardCopy IV devices. Because HardCopy IV devices are mask programmed, they cannot be changed after the silicon is fabricated. By implementing these two features, you can perform timing adjustments to improve or resolve timing issues after the silicon is fabricated Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARCOPY, MAX, MEGACORE, NIOS, UARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Subscribe

2 7 2 Chapter 7: External Memory Interfaces in HardCopy IV evices f For information about the clock rate support for Hardcopy IV devices, refer to the System Performance Specifications section of the External Memory Interface Handbook. 1 Some HardCopy IV GX and E devices have I/O overhang and I/O adjacent to the PLLs which might affect I/O performance. For more information, refer to the HardCopy IV evice I/O Feature chapter. Figure 7 1 shows a package-bottom view for HardCopy IV E external memory support. Figure 7 2 shows a package-bottom view for HardCopy IV GX external memory support, PLLs, LLs, and I/O banks. The number of available I/O banks and PLLs depends on the device density. Figure 7 1. Package-Bottom View for HardCopy IV E evices (Note 1), (2), (3) PLL_L1 LL0 8A 8B 8C PLL_T1 PLL_T2 7C 7B 7A LL3 PLL_R1 1A A 1C C PLL_L2 PLL_R2 PLL_L3 PLL_R3 2C 5C 2A 5A PLL_L4 LL1 3A 3B 3C PLL_B1 PLL_B2 4C 4B 4A LL2 PLL_R4 Notes to Figure 7 1: (1) The number of I/O banks and PLLs available depend on the device density. (2) Not all HardCopy IV E devices support I/O banks 1B, 2B, 5B, and B. (3) There is only one PLL on each side of the HC4E21, HC4E31, and HC4E41 devices. These devices do not support I/O banks 3B, 4B, 7B, and 8B. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

3 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 3 Figure 7 2. Package-Bottom View for HardCopy IV GX evices (Note 1), (2), (3) LL0 8A 8B 8C PLL_T1 PLL_T2 7C 7B 7A LL3 1A A 1C C PLL_L1 PLL_R1 PLL_L2 PLL_R2 2C 5C 2A 5A LL1 3A 3B 3C PLL_B1 PLL_B2 4C 4B 4A LL2 Notes to Figure 7 2: (1) The number of I/O banks and PLLs available depend on the device density. (2) All HardCopy IV GX devices do not support 1B, 2B, 5B, and B I/O banks. (3) There are no right side PLLs in HC4GX15L devices. These devices do not support I/O banks 3B, 4B, 7B, and 8B. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

4 7 4 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Figure 7 3 shows the memory interface data path that uses all the HardCopy IV I/O element (IOE) features. Figure 7 3. External Memory Interface ata Path Overview (Note 1), (2), (3) HardCopy IV ASIC Memory LL S Logic Block S (Read) FIFO 4n Half ata Rate Input Registers 2n Alignment & Synchronization Registers 2n R Input Registers n (Read) Resynchronization Clock 4n 2n 2n n (Write) Half-Rate Resynchronization Clock Half ata Rate Output Registers Alignment Registers R Output Registers Clock Management & Reset Write Clock Half-Rate Clock Alignment Clock S Write Clock S (Write) Half ata Rate Output Registers Alignment Registers R Output Registers Notes to Figure 7 3: (1) You can bypass each register block. (2) The blocks for each memory interface may differ slightly. (3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read and write operations. Memory Interfaces Pin Support A typical memory interface requires data (,, or ), data strobe (S and Sn/Cn), address, command, and clock pins. Some memory interfaces use data mask (M) pins to enable write masking and VL pins to indicate that the read data is ready to be captured. This section describes how HardCopy IV devices support these pins. ata and ata Clock/Strobe Pins HardCopy IV R memory interface read data-strobes or clocks are called S pins. epending on the memory specifications, the S pins can be bidirectional single-ended signals (in R2 and R SRAM), bidirectional differential signals (R3 and R2 SRAM), unidirectional differential signals (in RLRAM II), or unidirectional complementary signals (RII+ and RII SRAM). Connect the unidirectional read-and-write data-strobes or clocks to HardCopy IV S pins. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

5 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 5 Memory Interfaces Pin Support HardCopy IV devices offer differential input buffers for differential read data-strobe/clock operations and provide an independent S logic block for each Cn pin for complementary read data-strobe/clock operations. In the HardCopy IV pin tables, the differential S pin-pairs are denoted as S and Sn pins; the complementary S signals are denoted as S and Cn pins. Sn and Cn pins are marked separately in the pin table. Each Cn pin connects to a S logic block and the shifted Cn signals go to the negative-edge input registers in the IOE registers. 1 Use differential S signaling for R2 SRAM interfaces running higher than 333 MHz. HardCopy IV R memory interface data pins are called pins. The pins can be bidirectional signals, as in R3, R2, and R SRAM, and RLRAM II common I/O (CIO) interfaces, or unidirectional signals, as in RII+, RII SRAM, and RLRAM II separate I/O (SIO) devices. Connect the unidirectional read data signals to HardCopy IV pins and the unidirectional write data signals to a S/ group other than the read S/ group. Furthermore, the write clocks must be assigned to the S/Sn pins associated with this write S/ group. o not use the S/Cn pin-pair for write clocks. 1 Using a S/ group for the write data signals minimizes output skew and allows access to the write leveling circuitry (for R3 SRAM interfaces). These pins also have access to deskewing circuitry that can compensate for delay mismatch between signals on the bus. Table 7 1 lists the pin connections between a HardCopy IV device and an external memory device. Table 7 1. Memory Interfaces Pin Utilization for HardCopy IV evices (Part 1 of 2) Pin escription Memory Standard HardCopy IV Pin Utilization Read ata All Write ata All (1) Parity, M, BWSn, NWSn, VL, ECC All (1), (2) Read Strobes/Clocks Write Clocks R3 SRAM R2 SRAM (with differential S signaling) (3) RLRAM II R2 SRAM (with single-ended S signaling) (3) R SRAM RII+ SRAM RII SRAM RII+ SRAM (4) RII SRAM (4) RLRAM II SIO ifferential S/Sn Single-ended S Complementary S/Cn Any unused S and Sn pin pairs (1) March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

6 7 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Table 7 1. Memory Interfaces Pin Utilization for HardCopy IV evices (Part 2 of 2) Pin escription Memory Standard HardCopy IV Pin Utilization Memory Clocks R3 SRAM R2 SRAM (with differential S signaling) R2 SRAM (with single-ended S signaling) R SRAM RLRAM II RII+ SRAM (4) RII SRAM (4) Any unused or S pins with IFFIO_RX capability for the mem_clk[0] and mem_clk_n[0] signals. Any unused or S pins with IFFOUT capability for the mem_clk[n:1] and mem_clk_n[n:1] signals (where n is greater than or equal to 1). Any IFFIO_RX pins for the mem_clk[0] and mem_clk_n[0] signals. Any unused IFFOUT pins for the mem_clk[n:1] and mem_clk_n[n:1] signals (where n is greater than or equal to 1). Any IFFOUT pins Any unused Sn pin pairs (1) Notes to Table 7 1: (1) If the write data signals are unidirectional including the data mask pins, connect them to a separate S/ group other than the read S/ group. Connect the write clock to the S and Sn pin-pair associated with that S/ group. o not use the S and Cn pin-pair as write clocks. (2) The BWSn, NWSn, and M pins must be part of the write S/ group. Parity, VL, and ECC pins must be part of the read S/ group. (3) R2 SRAM supports either single-ended or differential S signaling. (4) RII+/RII SRAM devices typically use the same clock signals for both write and memory clock pins (K/K# clocks) to latch data and address, and command signals. The clocks must be part of the S/ group in this case. The S and pin locations are fixed in the pin table. Memory interface circuitry is available in every HardCopy IV I/O bank. All memory interface pins support the I/O standards required to support R3, R2, R SRAM, RII+, RII SRAM, and RLRAM II devices. HardCopy IV devices support S and signals with bus modes of 4, 8/ 9, 1/ 18, or 32/ 3, although not all devices support S bus mode 32/ 3. When any of these pins are not used for memory interfacing, you can use them as user I/Os. In addition, you can use any Sn or Cn pin not used for clocking as (data) pins. Table 7 2 lists pin support per S/ bus mode, including the S and Sn/Cn pin pair. Table 7 2. S/ Bus Mode Pins for HardCopy IV evices (Part 1 of 2) (Note 1), (2), (3), (4), (5) Mode Sn Support Cn Support Parity or M (Optional) VL (Optional) Typical Number of ata Pins per Group Maximum Number of ata Pins per Group 4 Yes No No No 4 5 8/ 9 Yes Yes Yes Yes 8 or / 18 Yes Yes Yes Yes 1 or HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

7 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 7 Memory Interfaces Pin Support Table 7 2. S/ Bus Mode Pins for HardCopy IV evices (Part 2 of 2) (Note 1), (2), (3), (4), (5) Mode 32/ 3 Yes Yes Yes Yes 32 or 3 47 Notes to Table 7 2: Sn Support Cn Support Parity or M (Optional) VL (Optional) Typical Number of ata Pins per Group (1) The VL pin is not used in the ALTMEMPHY megafunction. (2) This represents the maximum number of pins (including parity, data mask, and VL pins) connected to the S bus network with single-ended S signaling. When you use differential or complementary S signaling, the maximum number of data per group decreases by one. This number may vary per S/ group in a particular device. Check the pin table for the accurate number per group. (3) Two 4 S/ groups are stitched to make a 8/ 9 group, so there are a total of 12 pins in this group. (4) Four 4 S/ groups are stitched to make a 1/ 18 group. (5) Eight 4 S/ groups are stitched to make a 32/ 3 group. You can also use S/Sn pins in some of the 4 groups as R UP /R N pins (listed in the pin table). You cannot use a 4 S/ group for memory interfaces if any of its pin members are being used as R UP and R N pins for OCT calibration. You may use the 8/ 9 group that includes this 4 S/ group, if either of the following circumstances apply: You are not using M pins with your differential S pins You are not using complementary or differential S pins Maximum Number of ata Pins per Group You can do this because a S/ 8/ 9 group is comprised of 12 pins, as the groups are formed by stitching two S/ groups in 4 mode with six total pins each (Table 7 2). A typical 8 memory interface contains 10 pins, consisting of one S, one M, and eight pins. If you choose your pin assignment carefully, you can use the two extra pins for R UP and R N. In a R3 SRAM interface, you must use differential S, which means that you only have one extra pin. In this case, pick different pin locations for the R UP and R N pins (for example, in the bank that contains the address and command pins). You cannot use the R UP and R N pins shared with S/ group pins when using 9 RII+/RII SRAM devices, as the R UP and R N pins have a dual purpose with the Cn pins. In this case, pick different pin locations for the R UP and R N pins to avoid conflict with memory interface pin placement. You have the choice of placing the R UP and R N pins in the data-write group or in the same bank as the address and command pins. There is no restriction for using 1/ 18 or 32/ 3 S/ groups that include the 4 groups in which the pin members are used as R UP and R N pins. These groups contain enough extra pins that they can be used as S pins. You must pick your S and pins manually for the 8/ 9, 1/ 18, or 32/ 3 S/ group in which the members are used for R UP and R N. Otherwise, the uartus II software might not be able to place these pins correctly if there are no specific pin assignments and might give you a no-fit error instead. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

8 7 8 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Table 7 3 lists the maximum number of S/ groups per side of the HardCopy IV E device. Table 7 3. Number of S/ Groups in HardCopy IV E evices per Side (Note 1) HC4E25W HC4E25F HC4E35L HC4E35F evice Package Side 4 8/ 9 1/ 18 32/ 3 Note to Table 7 3: 484-pin FineLIne BGA 780-pin FineLine BGA 484-pin FineLIne BGA 780-pin FineLine BGA 1152-pin FineLine BGA 1517-pin FineLine BGA Left Bottom Right Top Left Bottom Right Top Left Bottom Right Top Left Bottom Right Top Left Bottom Right Top Left Bottom Right Top (1) In some 4 groups, you can use the S/ pins as R UP /R N pins. You cannot use these 4 groups if the pins are used as R UP and R N pins for OCT calibration. Ensure that the S/ groups you chose are not also used for OCT calibration. Table 7 4 lists the maximum number of S/ groups per side of the HardCopy IV GX device. Table 7 4. Number of S/ Groups in HardCopy IV GX evices per Side (Part 1 of 2) evice Package Side 4 (2) 8/ 9 1/ 18 32/ 3 HC4GX15LA 780-pin FineLine BGA Left (1) Bottom Right Top HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

9 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 9 Memory Interfaces Pin Support Table 7 4. Number of S/ Groups in HardCopy IV GX evices per Side (Part 2 of 2) evice Package Side 4 (2) 8/ 9 1/ 18 32/ 3 HC4GX15L HC4GX25L HC4GX25L HC4GX25F HC4GX35F HC4GX35F 780-pin FineLine BGA 780-pin FineLine BGA 1152-pin FineLine BGA 1152-pin FineLine BGA 1517-pin FineLine BGA Left Bottom Right Top Left Bottom Right Top Left Bottom Right Top Left Bottom Right Top Left Bottom Right Top Notes to Table 7 4: (1) There are no S/ groups in the left side of the HC4GX25LF780 devices. (2) In some 4 groups, you can use the S/ pins as R UP /R N pins. You cannot use these 4 groups if the pins are used as R UP and R N pins for OCT calibration. Ensure that the S/ groups that you chose are not also used for OCT calibration. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

10 7 10 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Figure 7 4 through Figure 7 7 show the number of S/ groups available per bank in each HardCopy IV E device. These figures present the package-bottom view of the specified HardCopy IV E devices. Figure 7 4. Number of S/ Groups per Bank in HC4E25W evices in a 484-pin FineLine BGA Package (Note 1) I/O Bank 3C I/O Bank 4C LL 0 4=2 LL 3 I/O Bank 2A I/O Bank 5A I/O Bank 2C I/O Bank 1C 484-pin FineLine BGA I/O Bank 5C I/O Bank C I/O Bank 1A 8/x9=1 1/x18=0 I/O Bank A I/O Bank 8C I/O Bank 7C LL 1 4=2 LL 2 Note to Figure 7 4: (1) These devices do not support 32/ 3 mode. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

11 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 11 Memory Interfaces Pin Support Figure 7 5. Number of S/ Groups per Bank in HC4E25F evices in 780-pin FineLine BGA Package (Note 1) I/O Bank 8A (2) I/O Bank 8C I/O Bank 7C I/O Bank 7A (2) LL 0 4=2 LL 3 I/O Bank 1A (2) 8/ 9=2 I/O Bank A (2) 8/ 9=2 I/O Bank 1C 2 User I/Os (3) I/O Bank 2C 2 User I/Os (3) 780-pin FineLine BGA I/O Bank C 2 User I/Os (3) I/O Bank 5C 2 User I/Os (3) I/O Bank 2A (2) 8/x9=2 1/x18=1 I/O Bank 5A (2) 8/ 9=2 I/O Bank 3A (2) I/O Bank 3C I/O Bank 4C I/O Bank 4A (2) LL 1 4=2 LL 2 Notes to Figure 7 5: (1) These devices do not support 32/ 3 mode. (2) You can use the S/Sn pins in some of the 4 groups as R UP /R N pins. You cannot use a 4 group for memory interfaces if two pins in the group are used as R UP and R N pins for OCT calibration. You can still use the 1/ 18 groups, including the 4 groups. However, there are restrictions on using 8/ 9 groups that include these 4 groups. (3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n). March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

12 7 12 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Figure 7. Number of S/ Groups in HC4E35L and HC4E35F evices in 1152-pin FineLine BGA Package (Note 1) LL0 I/O Bank 8A (2) I/O Bank 8B 8/ 9=2 I/O Bank 8C I/O Bank 7C I/O Bank 7B 8/ 9=2 I/O Bank 7A (2) LL3 I/O Bank 1A (2) I/O Bank A (2) 48 User I/Os 4=7 48 User I/Os 4=7 I/O Bank 1C 42 User I/Os (3) I/O Bank C 42 User I/Os (3) I/O Bank 2C 42 User I/Os (3) 1152-pin FineLine BGA I/O Bank 5C 42 User I/Os (3) I/O Bank 2A (2) 48 User I/Os 4=7 I/O Bank 5A (2) 48 User I/Os 4=7 I/O Bank 3A (2) I/O Bank 3B I/O Bank 3C I/O Bank 4C I/O Bank 4B I/O Bank 4A (2) LL1 8/ 9=2 8/ 9=2 LL2 Notes to Figure 7 : (1) These devices do not support 32/ 3 mode. (2) You can use the S/Sn pins in some of the 4 groups as R UP /R N pins. You cannot use a 4 group for memory interfaces if two pins in the group are used as R UP and R N pins for OCT calibration. You can still use the 1/ 18 groups including the 4 groups. However, there are restrictions on using 8/ 9 groups that include these 4 groups. (3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n). HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

13 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 13 Memory Interfaces Pin Support Figure 7 7. Number of S/ Groups per Bank in HC4E35L and HC4E35F evices in a 1517-pin FineLine BGA Package LL0 I/O Bank 8A (1) 48 User I/Os 4=8 8/ 9=4 1/ 18=2 32/ 3=1 I/O Bank 8B I/O Bank 8C I/O Bank 7C I/O Bank 7B I/O Bank 7A (1) 48 User I/Os 4=8 8/ 9=4 1/ 18=2 32/ 3=1 32/ 3=0 32/ 3=0 48 User I/Os 4=8 8/ 9=4 1/ 18=2 32/ 3=1 48 User I/Os 4=8 8/ 9=4 1/ 18=2 32/ 3=1 LL3 I/O Bank 1A (1) I/O Bank A (1) 50 User I/Os (2) 4=7 32/ 3=0 50 User I/Os (2) 4=7 32/ 3=0 I/O Bank 1C 42 User I/Os (2) 32/ 3=0 I/O Bank C 42 User I/Os (2) 32/ 3=0 I/O Bank 2C 42 User I/Os (2) 32/ 3= Pin FineLine BGA I/O Bank 5C 42 User I/Os (2) 32/ 3=0 I/O Bank 2A (1) I/O Bank 5A (1) 50 User I/Os (2) 4=7 32/ 3=0 50 User I/Os (2) 4=7 32/ 3=0 I/O Bank 3A (1) I/O Bank 3B I/O Bank 3C I/O Bank 4C I/O Bank 4B I/O Bank 4A (1) LL1 48 User I/Os 4=8 8/ 9=4 1/ 18=2 32/ 3=1 48 User I/Os 4=8 8/ 9=4 1/ 18=2 32/ 3=1 32/ 3=0 32/ 3=0 48 User I/Os 4=8 8/ 9=4 1/ 18=2 32/ 3=1 48 User I/Os 4=8 x8/ 9=4 1/ 18=2 32/ 3=1 LL2 Notes to Figure 7 7: (1) You can use the S/Sn pins in some of the 4 groups as R UP /R N pins. You cannot use a 4 group for memory interfaces if two pins in the group are used as R UP and R N pins for OCT calibration. You can still use the 1/ 18 or 32/ 3 groups including the 4 groups. However, there are restrictions on using 8/ 9 groups that include these 4 groups. (2) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, and PLL_R1_CLKn) that can be used for data inputs. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

14 7 14 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Figure 7 8 through Figure 7 11 show the number of S/ groups available per bank in HardCopy IV GX device. These figures present the package-bottom view of the specified HardCopy IV GX devices. Figure 7 8. Number of S/ Groups per Bank in HC4GX15LA evices in a 780-pin FineLine BGA Package (Note 1) LL0 I/O Bank 8A (4) I/O Bank 8C 4=2 I/O Bank 7C I/O Bank 7A (4) LL3 I/O Bank 1A (2) 8/ 9=2 I/O Bank 1C (3) I/O Bank 2C (2) 780-pin FineLine BGA I/O Bank 2A (2) 8/ 9=2 LL1 I/O Bank 3A (4) I/O Bank 3C 4=2 I/O Bank 4C I/O Bank 4A (4) LL2 Notes to Figure 7 8: (1) These devices do not support 32/ 3 mode. (2) There are no 1A, 2A, and 2C banks in HC4GX15L devices. (3) There are no S/ groups, and 13 configuration pins in the bank 1C when migrating EP4SGX290 or EP4SGX30 prototype devices. (4) You can use the S/Sn pins in some of the 4 groups as R UP /R N pins. You cannot use a 4 group for memory interfaces if two pins in the group are used as R UP and R N pins for OCT calibration. You can still use the 1/ 18 groups, including the 4 groups. However, there are restrictions on using 8/ 9 groups that include these 4 groups. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

15 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 15 Memory Interfaces Pin Support Figure 7 9. Number of S/ Groups per Bank in HC4GX25L evices in a 780-pin FineLine BGA Package (Note 1), (2) LL0 I/O Bank 8A (2) I/O Bank 8B 8/ 9=2 I/O Bank 8C I/O Bank 7C I/O Bank 7B 8/ 9=2 I/O Bank 7A (2) LL3 I/O Bank 1C 13 User I/Os 4=0 8/ 9=0 780-pin FineLine BGA LL1 I/O Bank 3A (2) I/O Bank 3B 8/ 9=2 I/O Bank 3C I/O Bank 4C I/O Bank 4B 8/ 9=2 I/O Bank 4A (2) LL2 Notes to Figure 7 9: (1) These devices do not support 32/ 3 mode. (2) You can use the S/Sn pins in some of the 4 groups as R UP /R N pins. You cannot use a 4 group for memory interfaces if two pins in the group are used as R UP and R N pins for OCT calibration. You can still use the 1/ 18 groups, including the 4 groups. However, there are restrictions on using 8/ 9 groups that include these 4 groups. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

16 7 1 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Figure Number of S/ Groups per Bank in HC4GX25L, HC4GX25F and HC4GX35F evices in a 1152-pin FineLine BGA Package (Note 1), (2) LL0 I/O Bank 8A (2) I/O Bank 8B 8/ 9=2 I/O Bank 8C I/O Bank 7C I/O Bank 7B 8/ 9=2 I/O Bank 7A (2) LL3 I/O Bank 1A I/O Bank A 48 User I/Os 4=7 48 User I/Os 4=7 I/O Bank 1C I/O Bank C 1152-pin FineLine BGA LL1 I/O Bank 3A (2) I/O Bank 3B 8/ 9=2 I/O Bank 3C I/O Bank 4C I/O Bank 4B 8/ 9=2 I/O Bank 4A (2) LL2 Notes to Figure 7 10: (1) These devices do not support 32/ 3 mode. (2) You can use the S/Sn pins in some of the 4 groups as R UP /R N pins. You cannot use a 4 group for memory interfaces if two pins in the group are used as R UP and R N pins for OCT calibration. You can still use the 1/ 18 groups, including the 4 groups. However, there are restrictions on using 8/ 9 groups that include these 4 groups. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

17 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 17 Memory Interfaces Pin Support Figure Number of S/ Groups per Bank in HC4GX35L and HC4GX35F evices in a 1517-pin FineLine BGA Package (Note 1), (2) LL0 I/O Bank 8A (3) I/O Bank 8B 8/ 9=2 I/O Bank 8C I/O Bank 7C I/O Bank 7B 8/ 9=2 I/O Bank 7A (3) LL3 I/O Bank 1A I/O Bank A 48 User I/Os 4=7 48 User I/Os 4=7 I/O Bank 1C I/O Bank C I/O Bank 2C I/O Bank 2A 1517-pin FineLine BGA I/O Bank 5C I/O Bank 5A 48 User I/Os 4=7 48 User I/Os 4=7 LL1 I/O Bank 3A (3) I/O Bank 3B 8/ 9=2 I/O Bank 3C I/O Bank 4C I/O Bank 4B 8/ 9=2 I/O Bank 4A (3) LL2 Notes to Figure 7 11: (1) These devices do not support 32/ 3 mode. (2) You can use the S/Sn pins in some of the 4 groups as R UP /R N pins. You cannot use a 4 group for memory interfaces if two pins in the group are used as R UP and R N pins for OCT calibration. You can still use the 1/ 18 groups, including the 4 groups. However, there are restrictions on using 8/ 9 groups that include these 4 groups. The S and Sn pins are listed in the HardCopy IV pin tables as SXY and SnXY, respectively, where X denotes the S/ grouping number, and Y denotes whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the device. The corresponding pins are marked as XY, where X indicates which S group the pins belong to and Y indicates whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the device. For example, S1L indicates a S pin, located on the left side of the device, as shown in Figure The pins belonging to that group are shown as 1L in the pin table. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

18 7 18 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support Figure 7 12 and Figure 7 13 show how the S/ groups are numbered in a package-bottom view of the device. The numbering scheme starts from the top left side of the device going counter-clockwise. The top and bottom sides of the HardCopy IV E device can contain up to 38 4 S/ groups; the left and right sides of the device can contain up to 2 4 S/ groups.the top and bottom sides of the HardCopy IV GX device can contain up to 2 4 S/ groups; the left and right sides of the device can contain up to 2 4 S/ groups. The parity, M, BWSn, ECC, and VL pins are shown as pins in the pin table. When not used as memory interface pins, these pins are available as regular I/O pins. Figure S Pins in HardCopy IV E I/O Banks S38T S20T S19T S1T LL0 PLL_L1 S1L 1A PLL_T1 PLL_T2 8A 8B 8C 7C 7B 7A LL3 PLL_R1 S2R A S13L 1C C S14R PLL_L2 PLL_R2 PLL_L3 PLL_R3 S14L 2C 5C S13R 2A S2L PLL_L4 LL1 3A 3B 3C 4C 4B 4A PLL_B1 PLL_B2 5A S1R PLL_R4 LL2 S1B S19B S20B S38B HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

19 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 19 Memory Interfaces Pin Support Figure S Pins in HardCopy IV GX I/O Banks S2T S14T S13T S1T LL0 PLL_T1 PLL_T2 LL3 8A 8B 8C 7C 7B 7A S1L S2R 1A A 1C C S13L S14R PLL_L1 PLL_R1 PLL_L2 PLL_R2 S14L S13R 2C 5C 2A 5A S2L S1R 3A 3B 3C 4C 4B 4A LL1 PLL_B1 PLL_B2 LL2 S1B S13B S14B S2B The pin numbering is based on 4 mode. In 4 mode, there are up to eight S/ groups per I/O bank. Each 4 mode S/ group consists of a S pin, a Sn pin, and four pins. In 8/ 9 mode, the I/O bank combines two adjacent 4 S/ groups; one pair of S and Sn/Cn pins can drive all the and parity pins in the new combined group that consists of up to 10 pins (including parity or M and VL pins) and a pair of S and Sn/Cn pins. Similarly, in 1/ 18 mode, the I/O bank combines four adjacent 4 S/ groups to create a group with a maximum of 19 pins (including parity or M and VL pins) and a pair of S and Sn/Cn pins. In 32/ 3 mode, the I/O bank combines eight adjacent 4 S/ groups together to create a group with a maximum of 37 pins (including parity or M and VL pins) and a pair of S and Sn/Cn pins. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

20 7 20 Chapter 7: External Memory Interfaces in HardCopy IV evices Memory Interfaces Pin Support HardCopy IV modular I/O banks allow easy formation of the S/ groups. If all the pins in the I/O banks are user I/O pins and are not used for R UP /R N OCT calibration or PLL clock output pins, you can divide the number of I/O pins in the bank by six to get the maximum possible number of 4 groups. You can then divide that number by two, four, or eight to get the maximum possible number of 8/ 9, 1/ 18, or 32/ 3, respectively, as listed in Table 7 5. However, some of the pins in the I/O bank may be used for other functions. Table 7 5. /S Group in HardCopy IV Modular I/O Banks Modular I/O Bank Size (1) Maximum Possible Number of 4 Groups Maximum Possible Number of 8/ 9 Groups Maximum Possible Number of 1/ 18 Groups Maximum Possible Number of 32/ 3 Groups 24 pins 4 (2) pins 5 (3) pins pins Notes to Table 7 5: (1) This I/O pin count does not include dedicated clock inputs or the dedicated corner PLL clock inputs. (2) Some of the 4 groups may use the R UP and R N pins. You cannot use these groups if you use the HardCopy IV calibrated OCT feature. (3) The actual maximum number of 4 groups for an I/O bank with 32 pins is four in the HardCopy IV devices. Optional Parity, M, BWSn, ECC, and VL Pins You can use any pin from the same S/ group for data as parity pins in HardCopy IV devices. The HardCopy IV device family supports parity in the 8/ 9, 1/ 18, and 32/ 3 modes. There is one parity bit available per eight bits of data pins. Use any of the (or ) pins in the same S/ group as data for parity because parity bits are treated, set, and generated similar to a pin. M pins are only required when writing to R3, R2, R SRAM, and RLRAM II devices. RII+ and RII SRAM devices use the BWSn signal to select which byte to write into the memory. A low on the M or BWSn signals indicates the write is valid. If the M or BWSn signal is high, the memory masks the signals. If the system does not require write data masking, connect the memory M pins low to indicate every write data is valid. You can use any of the pins in the same S/ group as write data for the M or BWSn signals. Each group of S and signals in R3, R2, and R SRAM devices requires a M pin. There is one M pin per RLRAM II device and one BWSn pin per nine bits of data in 9, 18, and 3 RII+/RII SRAM. The 8 RII SRAM device has two BWSn pins per eight data bits, which are referred to as the NWSn pins. Generate the M or BWSn signals using pins and configure the signals similarly to the (or ) output signals. HardCopy IV devices do not support the M signal in 4 R3 SRAM or in 4 R2 SRAM interfaces with differential S signaling. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

21 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 21 Memory Interfaces Pin Support Some R3, R2, and R SRAM devices or modules support error correction coding (ECC), which is a method of detecting and automatically correcting errors in data transmission. In 72-bit R3, R2, or R SRAM interfaces, the typical eight ECC pins are used in addition to the 4 data pins. Connect the R3, R2, and R SRAM ECC pins to a HardCopy IV device S/ group. These signals are also generated similar to pins. The memory controller requires encoding and decoding logic for the ECC data. You can also use the extra byte of data for other error checking methods. VL pins are used in RLRAM II and RII+ SRAM interfaces to indicate the read data availability. There is one VL pin per memory device. A high on the VL pin indicates that the memory is outputting the data requested. Similar to inputs, this signal is edge-aligned with the read clock signals (C/Cn in RII+/RII SRAM and K/K# in RLRAM II) and is sent half-a-clock cycle before data starts from the memory. The VL pin is not used in the ALTMEMPHY solution for RII+ SRAM. For more information about the parity, ECC, and VL pins, and when these pins are treated as pins, refer to ata and ata Clock/Strobe Pins on page 7 4. Address and Control/Command Pins Address and control/command signals are typically sent at single data rate. The only exception is in RII SRAM burst-of-two devices, in which case the read address must be captured on the rising edge of the clock and the write address must be captured on the falling edge of the clock by the memory. There is no special circuitry required for the address and control/command pins. You can use any of the user I/O pins in the same I/O bank as the data pins. Memory Clock Pins In addition to S (and Cn) signals to capture data, R3, R2, R SRAM, and RLRAM II use an extra pair of clocks, called CK and CK# signals, to capture the address and control/command signals. The CK and CK# signals must be generated to mimic the write data-strobe using HardCopy IV R I/O registers (IOs) to ensure that the timing relationships between the CK, CK#, and S signals (tss in R3, R2, and R SRAM or tckk in RLRAM II) are met. RII+ and RII SRAM devices use the same clock (K/K#) to capture the data, address, and control/command signals. Memory clock pins in HardCopy IV devices are generated using a IO register going to differential output pins, marked in the pin table with IFFOUT, IFFIO_TX, and IFFIO_RX prefixes. For more information about which pins to use for memory clock pins, refer to Table 7 2 on page 7. March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

22 7 22 Chapter 7: External Memory Interfaces in HardCopy IV evices HardCopy IV External Memory Interface Features Figure 7 14 shows memory clock generation for HardCopy IV devices. Figure Memory Clock Generation Block iagram (Note 1) HardCopy HCells I/O Elements V CC CK or K or K (2) CK# or K# or K# (2) System Clock Notes to Figure 7 14: (1) For the pin location requirements for these pins, refer to Table 7 1 on page 7 5. (2) The mem_clk[0] and mem_clk_n[0] pins for R3, R2, and R SRAM interfaces use the I/O input buffer for feedback. For memory interfaces using a differential S input, the input feedback buffer is configured as differential input; for memory interfaces using a single-ended S input, the input buffer is configured as a single-ended input. Using a single-ended input feedback buffer requires that V REF is provided to that I/O bank s VREF pins. HardCopy IV External Memory Interface Features HardCopy IV devices are rich with features that allow robust high-performance external memory interfacing. The ALTMEMPHY megafunction allows you to set these external memory interface features and helps set up the physical interface (PHY) best suited for your system. This section describes each HardCopy IV device feature that is used in external memory interfaces from the S phase-shift circuitry, S logic block, leveling multiplexers, dynamic OCT control block, IOE registers, IOE features, and the PLL. 1 When using the Altera memory controller MegaCore functions, the PHY is instantiated for you. 1 The ALTMEMPHY megafunction and the Altera memory controller MegaCore functions can run at half the frequency of the I/O interface of the memory devices to allow better timing management in high-speed memory interfaces. HardCopy IV devices have built-in registers to convert data from full-rate (I/O frequency) to half-rate (controller frequency) and vice versa. You can bypass these registers if your memory controller is not running at half the rate of the I/O frequency. f For more information about the ALTMEMPHY megafunction, refer to the External Memory Interface Handbook. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

23 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 23 HardCopy IV External Memory Interface Features S Phase-Shift Circuitry The HardCopy IV phase-shift circuitry provides phase shift to the S and Cn pins on read transactions when the S and Cn pins are acting as input clocks or strobes to the HardCopy IV device. The S phase-shift circuitry consists of LLs that are shared between multiple S pins and the phase-offset module to further fine-tune the S phase shift for different sides of the device. Figure 7 15 shows how the S phase-shift circuitry is connected to the S and Cn pins in the device. Figure S and Cn Pins and S Phase-Shift Circuitry LL Reference Clock S Pin Cn Pin S Logic Blocks S Pin Cn Pin LL Reference Clock Δt Δt Δt Δt S Phase-Shift Circuitry to IOE to IOE to IOE to IOE S Phase-Shift Circuitry S Logic Blocks to IOE Δt Cn Pin S Pin Δt to IOE to IOE Δt S Pin Cn Pin Δt to IOE S Pin Δt to IOE to IOE Δt Cn Pin Cn Pin Δt to IOE to IOE Δt S Pin S Phase-Shift Circuitry to IOE to IOE to IOE to IOE S Phase-Shift Circuitry Δt Δt Δt Δt LL Reference Clock Cn Pin S Pin Cn Pin S Pin LL Reference Clock March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

24 7 24 Chapter 7: External Memory Interfaces in HardCopy IV evices HardCopy IV External Memory Interface Features The S phase-shift circuitry is connected to the S logic blocks that control each S or Cn pin. The S logic blocks allow the S delay settings to be updated concurrently at every S or Cn pin. LL S phase-shift circuitry uses a LL to dynamically measure the clock period required by the S/Cn pin. The LL, in turn, uses a frequency reference to generate dynamically controlled signals for the delay chains in each of the S and Cn pins, allowing it to compensate for PVT variations. The S delay settings are Gray-coded to reduce jitter when the LL updates the settings. The phase-shift circuitry requires a maximum of 1,280 clock cycles to calculate the correct input clock period. o not send data during these clock cycles because there is no guarantee that it will be captured properly. Because the settings from the LL may not be stable until this lock period has elapsed, anything using these settings (including the leveling delay system) may be unstable during this period. 1 You can still use the S phase-shift circuitry for any memory interfaces that are less than 100 MHz. The S signal is shifted by 2.5 ns. Even if the S signal is not shifted exactly to the middle of the valid window, the IOE must be able to capture the data in low frequency applications where a large amount of timing margin is available. There are four LLs in a HardCopy IV device, located in each corner of the device. These four LLs can support a maximum of four unique frequencies, with each LL running at one frequency. Each LL can have two outputs with different phase offsets, allowing one HardCopy IV device to have eight different LL phase shift settings. Figure 7 1 shows the LL and I/O bank locations in HardCopy IV E devices, from a package-bottom view. Figure 7 17 shows the LL and I/O bank locations in HardCopy IV GX devices. Altera recommends enabling the PLL reconfiguration feature and the LL phase offset feature (LL reconfiguration) for HardCopy IV devices. Because HardCopy IV devices are mask programmed, they cannot be changed after the silicon is fabricated. By implementing these two features, you can perform timing adjustments to improve or resolve timing issues after the silicon is fabricated. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

25 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 25 HardCopy IV External Memory Interface Features Figure 7 1. HardCopy IV E LL and I/O Bank Locations (Package-Bottom View) PLL_L1 8A 8B 8C PLL_T1 PLL_T2 7C 7B 7A PLL_R1 LL0 LL3 1A A 1C C PLL_L2 PLL_R2 PLL_L3 PLL_R3 2C 5C 2A 5A LL1 LL2 PLL_L4 3A 3B 3C PLL_B1 PLL_B2 4C 4B 4A PLL_R4 March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

26 7 2 Chapter 7: External Memory Interfaces in HardCopy IV evices HardCopy IV External Memory Interface Features Figure HardCopy IV GX LL and I/O Bank Locations (Package-Bottom View) 8A 8B 8C PLL_T1 PLL_T2 7C 7B 7A LL0 LL3 1A A 1C C PLL_L1 PLL_R1 HSSI HSSI PLL_L2 PLL_R2 2C 5C 2A 5A LL1 LL2 3A 3B 3C PLL_B1 PLL_B2 4C 4B 4A The LL can access the two adjacent sides from its location within the device. For example, LL0 on the top left of the device can access the top side (I/O banks 7A, 7B, 7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1C, 2A, and 2C). This means that each I/O bank is accessible by two LLs, giving more flexibility to create multiple frequencies and multiple-types interfaces. For example, you can design an interface spanning one side of the device or two sides adjacent to the LL. The LL outputs the same S delay settings for both sides of the device adjacent to the LL. 1 Interfaces that span across two sides of the device are not recommended for high-performance memory interface applications. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

27 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 27 HardCopy IV External Memory Interface Features Each bank can use settings from either or both LLs of the adjacent bank. For example, S1L can use phase-shift settings from LL0, and S2L can use phase-shift settings from LL1. Table 7 lists the LL location and supported I/O banks for HardCopy IV devices. 1 You can only have one memory interface in I/O banks with the same I/O bank number (such as I/O banks 1A and 1C) when you use the leveling delay chains because there is only one leveling delay chain shared by these I/O banks. Table 7. LL Location and Supported I/O Banks LL Location Accessible I/O Banks LL0 Top left corner 1A, 1C, 2A, 2C, 7A, 7B, 7C, 8A, 8B, 8C LL1 Bottom left corner 1A, 1C, 2A, 2C, 3A, 3B, 3C, 4A, 4B, 4C LL2 Bottom right corner 3A, 3B, 3C, 4A, 4B, 4C, 5A, 5C, A, C LL3 Top right corner 5A, 5C, A, C, 7A, 7B, 7C, 8A, 8B, 8C The reference clock for each LL may come from the PLL output clocks or any of the two dedicated clock input pins located in either side of the LL. Table 7 7 and Table 7 8 show the available LL reference clock input resources for HardCopy IV E devices. Table 7 7. LL Reference Clock Input for HC4E25W and HC4E25F evices LL CLKIN (Top/Bottom) CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right) LL0 CLK12P, CLK13P, CLK14P, CLK15P CLK0P, CLK1P, CLK2P, CLK3P PLL_T1 PLL_L2 LL1 CLK4P, CLK5P, CLKP, CLK7P CLK0P, CLK1P, CLK2P, CLK3P PLL_B1 PLL_L2 LL2 CLK4P, CLK5P, CLKP, CLK7P CLK8P, CLK9P, CLK10P, CLK11P PLL_B1 PLL_R2 LL3 CLK12P, CLK13P, CLK14P, CLK15P CLK8P, CLK9P, CLK10P, CLK11P PLL_T1 PLL_R2 Table 7 8. LL Reference Clock Input for HC4E35L and HC4E35F evices LL CLKIN (Top/Bottom) CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right) LL0 CLK12P, CLK13P, CLK14P, CLK15P CLK0P, CLK1P, CLK2P, CLK3P PLL_T1 PLL_L1, PLL_L2 LL1 CLK4P, CLK5P, CLKP, CLK7P CLK0P, CLK1P, CLK2P, CLK3P PLL_B1 PLL_L3, PLL_L4 LL2 CLK4P, CLK5P, CLKP, CLK7P CLK8P, CLK9P, CLK10P, CLK11P PLL_B2 PLL_R3, PLL_R4 LL3 CLK12P, CLK13P, CLK14P, CLK15P CLK8P, CLK9P, CLK10P, CLK11P PLL_T2 PLL_R1, PLL_R2 March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration

28 7 28 Chapter 7: External Memory Interfaces in HardCopy IV evices HardCopy IV External Memory Interface Features Table 7 9 through Table 7 11 list the available LL reference clock input resources for HardCopy IV GX devices. Table 7 9. LL Reference Clock Input for HC4GX15LA and HC4GX25L evices LL CLKIN (Top/Bottom) CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right) LL0 CLK12P, CLK13P, CLK14P, CLK15P CLK0P, CLK1P, CLK2P, CLK3P (1) PLL_T1 PLL_L1 (2) LL1 CLK4P, CLK5P, CLKP, CLK7P CLK0P, CLK1P, CLK2P, CLK3P (1) PLL_B1 LL2 CLK4P, CLK5P, CLKP, CLK7P PLL_B1 LL3 CLK12P, CLK13P, CLK14P, CLK15P PLL_T1 Notes to Table 7 9: (1) edicated clock inputs for LL0 and LL1 are not supported in the HC4GX15L devices. (2) PLL_L1 is not supported in the HC4GX15L devices. Table LL Reference Clock Input for HC4GX25L and HC4GX25F evices LL CLKIN (Top/Bottom) CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right) LL0 CLK12P, CLK13P, CLK14P, CLK15P CLK0P, CLK1P PLL_T1 PLL_L2 LL1 CLK4P, CLK5P, CLKP, CLK7P CLK0P, CLK1P PLL_B1 LL2 CLK4P, CLK5P, CLKP, CLK7P CLK11P, CLK10P PLL_B2 LL3 CLK12P, CLK13P, CLK14P, CLK15P CLK11P, CLK10P PLL_T2 PLL_R2 Table LL Reference Clock Input for HC4GX35L and HC4GX35F evices LL CLKIN (Top/Bottom) CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right) LL0 CLK12P, CLK13P, CLK14P, CLK15P CLK0P, CLK1P, CLK2P, CLK3P PLL_T1 PLL_L2 LL1 CLK4P, CLK5P, CLKP, CLK7P CLK0P, CLK1P, CLK2P, CLK3P PLL_B1 PLL_L3 LL2 CLK4P, CLK5P, CLKP, CLK7P CLK11P, CLK10P, CLK8P, CLK9P PLL_B2 PLL_R3 LL3 CLK12P, CLK13P, CLK14P, CLK15P CLK11P, CLK10P, CLK8P, CLK9P PLL_T2 PLL_R2 When you have a dedicated PLL that only generates the LL input reference clock, set the PLL mode to No Compensation; otherwise, the uartus II software changes it automatically. Because the PLL does not use any other outputs, it does not have to compensate for any clock paths. HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration March 2012 Altera Corporation

29 Chapter 7: External Memory Interfaces in HardCopy IV evices 7 29 HardCopy IV External Memory Interface Features Figure 7 18 shows a block diagram of the LL. The input reference clock goes into the LL to a chain of up to 1 delay elements. The phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock. The phase comparator then issues the upndn signal to the Gray-code counter. This signal increments or decrements a six-bit delay setting (S delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase. Figure Simplified iagram of the S Phase Shift Circuitry (Note 1) addnsub_a Phase offset settings from the core array LL Phase Offset Control Phase offset settings to S pins on top or bottom edge (3) Input Reference Clock (2) Phase Comparator upndn clock enable Up/own Counter addnsub_b Phase offset settings from the core array Phase Offset Control Phase offset settings to S pin on left or right edge (3) elay Chains S elay Settings (4) Notes to Figure 7 18: (1) All features of the S phase-shift circuitry are accessible from the ALTMEMPHY MegaWizard Plug-In Manager in the uartus II software. (2) For exact PLL and input clock pin information, the input reference clock for the S phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to Table 7 7 and Table (3) Phase offset settings can go only to the S logic blocks. (4) S delay settings can go to the core array, the S logic block, and the leveling circuitry. The LL can be reset from either the core array or a user I/O pin. Each time the LL is reset, you must wait for 1,280 clock cycles before you can capture the data properly. epending on the LL frequency mode, the LL can shift the incoming S signals by 0, 22.5, 30, 3, 45, 0, 7.5, 72, 90, 108, 120, 135, 144, or 180. The shifted S signal is then used as the clock for the IOE input registers. All S and Cn pins referenced to the same LL can have their input signal phase shifted by a different degree amount, but all must be referenced at one particular frequency. For example, you can have a 90 phase shift on S1T and a 0 phase shift on S2T referenced from a 200-MHz clock. However, not all phase-shift combinations are supported. The phase shifts on the S pins referenced by the same LL must all be a multiple of 22.5 (up to 90 ), a multiple of 30 (up to 120 ), a multiple of 3 (up to 144 ), or a multiple of 45 (up to 180 ). March 2012 Altera Corporation HardCopy IV evice Handbook Volume 1: evice Interfaces and Integration