External Memory Interfaces in Cyclone V Devices

Transcription

1 External Memory Interfaces in Cyclone V Devices..8 CV-5 Subscribe Feedback The Cyclone V devices provide an efficient architecture that allows you fit wide external memory interfaces support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are designed provide high-performance support for existing and emerging external memory standards. Table -: Supported External Memory Standards in Cyclone V Devices Memory Standard DDR SDRAM DDR SDRAM LPDDR SDRAM Hard Memory Controller Full rate Full rate Full rate Soft Memory Controller Half rate Half rate Half rate To estimate the external memory system performance specification, use Altera's External Memory Interface Spec Estimar ol. For more information, refer the External Memory Interface Spec Estimar page on the Altera website. For more information about the memory types supported, board design guidelines, timing analysis, simulation, and debugging information, refer the External Memory Interface Handbook. External Memory Performance Table -: External Memory Interface Performance in Cyclone V Devices Interface Voltage (V) Hard Controller (MHz) Soft Controller (MHz) DDR SDRAM DDR SDRAM.8 4 LPDDR SDRAM.. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconducr products current specifications in accordance with Altera's standard warranty, but reserves the right make changes any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed in writing by Altera. Altera cusmers are advised obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9:8 Registered Innovation Drive, San Jose, CA 954

2 - CV-5..8 HPS External Memory Performance Table -: HPS External Memory Interface Performance The hard processor system (HPS) is available in Cyclone V SoC FPGA devices only. Interface Voltage (V) HPS Hard Controller (MHz) DDR SDRAM DDR SDRAM LPDDR SDRAM. Memory Interface Support in Cyclone V Devices In the Cyclone V devices, the memory interface circuitry is available in every I/O bank that does not support transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations. The memory clock pins are generated with double data rate input/output (DDRIO) registers. For more information about which pins use for memory clock pins and pin location requirements, refer the Planning and FPGA Resources chapter of the External Memory Interface Handbook. Guideline: Using DQ/ s The following list provides guidelines on using the DQ/ pins: The devices support DQ and signals with DQ bus modes of x8 or x. Cyclone V devices do not support the x4 bus mode. You can use the n pins that are not used for clocking as DQ pins. If you do not use the DQ/ pins for memory interfacing, you can use these pins as user I/Os. However, unused HPS DQ/ pins on the Cyclone V SX and ST devices cannot be used as user I/Os. Some pins have multiple functions such as RZQ or DQ. If you need extra RZQ pins, you can use some of the DQ pins as RZQ pins instead. Note: For the x8 or x DQ/ groups whose members are used as RZQ pins, Altera recommends that you assign the DQ and pins manually. Otherwise, the Quartus II software might not be able place the DQ and pins, resulting in a no-fit error. Reading the Table For the maximum number of DQ pins and the exact number per group for a particular Cyclone V device, refer the pin table in the Cyclone V Device -Out Files page of the Altera website. In the pin tables, the and n pins denote the differential data strobe/clock pin pairs. The and n pins are listed respectively in the Cyclone V pin tables as XY and nxy. X indicates the DQ/ grouping number and Y indicates whether the group is located on the p (T), botm (B), left (L), or right (R) side of the device.

3 CV-5..8 DQ/ Bus Mode s for Cyclone V Devices The following table list the pin support per DQ/ bus mode, including the and n pin pairs. The maximum number of data pins per group listed in the table may vary according the following conditions: Single-ended signalingthe maximum number of DQ pins includes data mask connected the bus network. Differential or complementary signalingthe maximum number of data pins per group decreases by one. DDR and DDR interfaceseach x8 group of pins require one pin. You may also require one n pin and one DM pin. This further reduces the tal number of data pins available. Table -4: DQ/ Bus Mode s for Cyclone V Devices - Mode n Support Data Mask (Optional) Maximum Data s per Group x8 Yes Yes x Yes Yes

4 -4 DQ/ Groups in Cyclone V E CV-5..8 Table -5: Number of DQ/ Groups Per Side in Cyclone V E Devices This table lists the DQ/ groups for the soft memory controller. For the hard memory controller, you can get the DQ/ groups from the pin table of the specific device at Cyclone V Device -Out Files page. The numbers are preliminary before the devices are available. Member Code Package Side x8 x 5-pin FineLine BGA -pin Ultra FineLine BGA 4 A A4 8-pin Micro FineLine BGA pin Ultra FineLine BGA pin FineLine BGA

5 CV Member Code A5 A Package 8-pin Micro FineLine BGA Side x8 484-pin Ultra FineLine BGA 484-pin FineLine BGA 484-pin Micro FineLine BGA pin Ultra FineLine BGA pin FineLine BGA -pin FineLine BGA 89-pin FineLine BGA 5 8 x

6 - CV-5..8 Member Code A9 Package 484-pin Ultra FineLine BGA Side x8 484-pin FineLine BGA -pin FineLine BGA 89-pin FineLine BGA 5 8 x DQ/ Groups in Cyclone V GX Table -: Number of DQ/ Groups Per Side in Cyclone V GX Devices This table lists the DQ/ groups for the soft memory controller. For the hard memory controller, you can get the DQ/ groups from the pin table of the specific device at Cyclone V Device -Out Files page. The numbers are preliminary before the devices are available. Member Code C Package -pin Ultra FineLine BGA Side 484-pin Ultra FineLine BGA 484-pin FineLine BGA x x

7 CV Member Code C4 C5 C Package -pin Micro FineLine BGA 8-pin Micro FineLine BGA Side x8 484-pin Ultra FineLine BGA 484-pin FineLine BGA -pin FineLine BGA 484-pin Micro FineLine BGA pin Ultra FineLine BGA pin FineLine BGA -pin FineLine BGA 89-pin FineLine BGA 5 8 x

8 -8 CV-5..8 Member Code C9 Package 484-pin Ultra FineLine BGA Side x8 484-pin FineLine BGA -pin FineLine BGA 89-pin FineLine BGA 5-pin FineLine BGA x 4 4

9 CV-5..8 DQ/ Groups in Cyclone V GT -9 Table -: Number of DQ/ Groups Per Side in Cyclone V GT Devices This table lists the DQ/ groups for the soft memory controller. For the hard memory controller, you can get the DQ/ groups from the pin table of the specific device at Cyclone V Device -Out Files page. The numbers are preliminary before the devices are available. Member Code D5 Package -pin Micro FineLine BGA 8-pin Micro FineLine BGA Side x8 484-pin Ultra FineLine BGA 484-pin FineLine BGA -pin FineLine BGA 5 8 x

10 - CV-5..8 Member Code D D9 Package 484-pin Micro FineLine BGA Side x8 484-pin Ultra FineLine BGA pin FineLine BGA -pin FineLine BGA 89-pin FineLine BGA 484-pin Ultra FineLine BGA pin FineLine BGA -pin FineLine BGA 89-pin FineLine BGA 5-pin FineLine BGA x 4 4

11 CV-5..8 DQ/ Groups in Cyclone V SX - Table -8: Number of DQ/ Groups Per Side in Cyclone V SX Devices This table lists the DQ/ groups for the soft memory controller. For the hard memory controller, you can get the DQ/ groups from the pin table of the specific device at Cyclone V Device -Out Files page. The numbers are preliminary before the devices are available. Member Code C C4 C5 C Package -pin Ultra FineLine BGA Side 89-pin FineLine BGA x8 8 5 x DQ/ Groups in Cyclone V ST Table -9: Number of DQ/ Groups Per Side in Cyclone V ST Devices This table lists the DQ/ groups for the soft memory controller. For the hard memory controller, you can get the DQ/ groups from the pin table of the specific device at Cyclone V Device -Out Files page. The numbers are preliminary before the devices are available. Member Code Package Side x8 x D5 D 89-pin FineLine BGA 5 External Memory Interface Features in Cyclone V Devices UniPHY IP The Cyclone V I/O elements () provide built-in functionality required for a rapid and robust implementation of external memory interfacing. The following device features are available for external memory interfaces: phase-shift circuitry PHY Clock (PHYCLK) networks logic block Dynamic on-chip termination (OCT) control registers Delay chain Hard memory controllers The high-performance memory interface solution includes the self-calibrating UniPHY IP that is optimized take advantage of the Cyclone V I/O structure and the Quartus II software TimeQuest Timing Analyzer.

12 - CV-5..8 The UniPHY IP helps set up the physical interface (PHY) best suited for your system. This provides the tal solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT) variations. The UniPHY IP instantiates a generate related clocks for the memory interface. The UniPHY IP can also dynamically choose the number of delay chains that are required for the system. The amount of delay is equal the sum of the intrinsic delay of the delay element and the product of the number of delay steps and the value of the delay steps. The UniPHY IP and the Altera memory controller MegaCore functions can run at half the I/O interface frequency of the memory devices, allowing better timing management in high-speed memory interfaces. The Cyclone V devices contain built-in circuitry in the convert data from full rate (the I/O frequency) half rate (the controller frequency) and vice versa. For more information about the UniPHY IP, refer the Reference Material volume of the External Memory Interface Handbook. External Memory Interface Datapath The following figure shows an overview of the memory interface datapath that uses the Cyclone V I/O elements. In the figure, the DQ/ read and write signals may be bidirectional or unidirectional, depending on the memory standard. If the signal is bidirectional, it is active during read and write operations. You can bypass each register block. Figure -: External Memory Interface Datapath Overview for Cyclone V Devices FPGA Postamble Circuitry Memory Postamble Clock Postamble Enable Enable Control Circuit Delay Chain Enable Circuit (Read) 4n or n Read FIFO n DDR Input Registers n DQ (Read) 4n Half Data Rate Output Registers n DDR Output and Output Enable Registers n DQ (Write) Clock Management and Reset Full-Rate Clock DQ Write Clock Half-Rate Clock Write Clock 4 Half Data Rate Output Registers DDR Output and Output Enable Registers (Write) Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements. Phase-Shift Circuitry The Cyclone V provides phase shift the pins on read transactions if the pins are acting as input clocks or strobes the FPGA.

13 CV-5..8 The following figures show how the s are connected the pins in the various Cyclone V variants. The reference clock for each may come from adjacent s. Figure -: s and s in Cyclone V E (A and A4) Devices - Reference Clock Logic Blocks Reference Clock Logic Blocks Logic Blocks Reference Clock Logic Blocks Reference Clock

14 -4 Figure -: s and s in Cyclone V GX (C) Devices CV-5..8 Reference Clock Logic Blocks Reference Clock Logic Blocks Transceiver Blocks Reference Clock

15 CV-5..8 Figure -4: s and s in Cyclone V E (A5, A, and A9), GX (C4, C5, C, and C9), GT (D5, D, and D9) Devices -5 Reference Clock Logic Blocks Reference Clock Logic Blocks Transceiver Blocks Reference Clock Logic Blocks Reference Clock

16 - Figure -5: s and s in Cyclone V SX (C, C4, C5, and C) and ST (D5 and D) Devices CV-5..8 Reference Clock HPS I/O Logic Blocks HPS HPS Block Transceiver Blocks Logic Blocks Reference Clock Logic Blocks Reference Clock Delay-Locked Loop The delay-locked loop () uses a frequency reference dynamically generate control signals for the delay chains in each of the pins, allowing the delay compensate for process, voltage, and temperature (PVT) variations. The delay settings are Gray-coded reduce jitter if the updates the settings. There are a maximum of four s, located in each corner of the Cyclone V devices. You can clock each using different frequencies. The s can access the two adjacent sides from its location in the device. You can have two different interfaces with the same frequency on the two sides adjacent a, where the controls the delay settings for both interfaces. I/O banks between two s have the flexibility create multiple frequencies and multiple-type interfaces. These banks can use settings from either or both adjacent s. For example, R can get its phase-shift settings from _TR, while R can get its phase-shift settings from _BR. The reference clock for each may come from the output clocks or clock input pins. Note: If you have a dedicated that only generates the input reference clock, set the mode Direct Compensation achieve better performance (or the Quartus II software aumatically

17 CV-5..8 changes it). Because the does not use any other outputs, it does not have compensate for any clock paths. - Reference Clock Input for Cyclone V Devices Table -: Reference Clock Input from s for Cyclone V E (A, A4, A5, A, and A9), GX (C4, C5, C, and C9), and GT (D5, D, and D9) DevicesPreliminary _TL pllout _TR pllout _BL pllout _BR pllout Table -: Reference Clock Input from s for Cyclone V GX (C) DevicePreliminary _TL pllout _TR pllout _BL _BR pllout Table -: Reference Clock Input from s for Cyclone V SX C, C4, C5, and C Devices, and Cyclone V ST D5 and D DevicesPreliminary _TL pllout _TR _BL pllout _BR pllout Phase-Shift The can shift the incoming signals by or 9. The shifted signal is then used as the clock for the DQ input registers, depending on the number of delay chains used.

18 -8 All pins, referenced the same, can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency. However, not all phase-shift combinations are supported. The phase shifts on the pins referenced by the same must all be a multiple of 9. The -bit delay settings from the vary with PVT implement the phase-shift delay. For example, with a shift, the signal bypasses both the and logic blocks. The Quartus II software aumatically sets the DQ input delay chains, so that the skew between the DQ and pins at the DQ registers is negligible if a shift is implemented. You can feed the delay settings the logic block and logic array. The shifted signal goes the bus clock the input registers of the DQ pins. The signal can also go in the logic array for resynchronization if you are not using read FIFO for resynchronization. For Cyclone V SoC FPGAs, you can feed the hard processor system (HPS) delay settings the HPS logic block only. The following figure shows a simple block diagram of the in the Cyclone V devices. All features of the phase-shift circuitry are accessible from the UniPHY megafunction in the Quartus II software. Figure -: Simplified Diagram of the Phase-Shift Circuitry CV-5..8 aload Input Reference Clock clk Phase Comparar upndnin upndninclkena Up/Down Counter delay settings can go the logic array and logic block This clock can come from a output clock or an input clock pin Delay Chains delayctrlout [:] Delay Settings dqsupdate The input reference clock goes in the a chain of up eight delay elements. The phase comparar compares the signal coming out of the end of the delay chain block the input reference clock. The phase comparar then issues the upndn signal the Gray-code counter. This signal increments or decrements a -bit delay setting ( delay settings) that increases or decreases the delay through the delay element chain bring the input reference clock and the signals coming out of the delay element chain in phase. The can be reset from either the logic array or a user I/O pin. Each time the is reset, you must wait for,5 clock cycles for the lock before you can capture the data properly. The phase comparar requires,5 clock cycles lock and calculate the correct input clock period. For the frequency range of each frequency mode, refer the Cyclone V Device Datasheet. PHY Clock (PHYCLK) Networks The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a high-performance external memory interface. The p and botm sides of the Cyclone V devices have up four PHYCLK networks each. There are up two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one I/O bank and is driven by one of the s located adjacent the I/O bank. The following figures show the PHYCLK networks available in the Cyclone V devices.

19 I/O Bank PHYCLK Networks I/O Bank CV-5..8 Figure -: PHYCLK Networks in Cyclone V E A and A4 Devices -9 I/O Bank 8 I/O Bank PHYCLK Networks FPGA Device PHYCLK Networks I/O Bank 5 I/O Bank PHYCLK Networks I/O Bank I/O Bank 4 Figure -8: PHYCLK Networks in Cyclone V GX C Devices I/O Bank 8 I/O Bank PHYCLK Networks Transceiver Banks FPGA Device PHYCLK Networks I/O Bank 5 I/O Bank PHYCLK Networks I/O Bank I/O Bank 4

20 - Figure -9: PHYCLK Networks in Cyclone V E A, A5, and A9 Devices, Cyclone V GX C4, C5, C, and C9 Devices, and Cyclone V GT D5, D, and D9 Devices CV-5..8 I/O Bank 8 I/O Bank PHYCLK Networks Transceiver Banks FPGA Device PHYCLK Networks I/O Bank 5 I/O Bank PHYCLK Networks I/O Bank I/O Bank 4 Figure -: PHYCLK Networks in Cyclone V SX C, C4, C5, and C Devices, and Cyclone V ST D5 and D Devices I/O Bank 8 PHYCLK Networks I/O Bank Transceiver Banks FPGA Device HPS HPS Block HPS PHYCLK Networks PHYCLK Networks HPS I/O I/O Bank 5 PHYCLK Networks I/O Bank I/O Bank 4 Logic Block Each /CQ/CQn/QK# pin is connected a separate logic block, which consists of the update enable circuitry, delay chains, and postamble circuitry.

21 CV-5..8 The following figure shows the logic block. Figure -: Logic Block in Cyclone V Devices - The dqsenable signal can also come from the FPGA fabric Postamble Enable Postamble Circuitry Enable Control Circuit dqsenablein D Q D Q zerophaseclk (Postamble clock) dqsdisablen enaphasetransferreg dqsin levelingclk (Read-leveled postamble clock) D D Q Q D Q Enable PRE dqsenable dqsenableout <delay dqs enable> Applicable only if the delay settings come from a side with two s Core Logic delay settings from the delay settings from the delayctrlin [:] Bypass delayctrlin [:] D Q This clock can come from a output clock or an input clock pin Delay Chain dqsin dqsupdateen Input Reference Clock <dqs delay chain bypass> Update Enable Circuitry dqsbusout Update Enable Circuitry The update enable circuitry enables the registers allow enough time for the delay settings travel from the phase-shift circuitry or core logic all the logic blocks before the next change. Both the delay settings and the phase-offset settings pass through a register before going in the delay chains. The registers are controlled by the update enable circuitry allow enough time for any changes in the delay setting bits arrive at all the delay elements, which allows them be adjusted at the same time. The circuitry uses the input reference clock or a user clock from the core generate the update enable output. The UniPHY intellectual property (IP) uses this circuit by default. Figure -: Update Enable Waveform This figure shows an example waveform of the update enable circuitry output. Counter Update (Every 8 cycles) Counter Update (Every 8 cycles) System Clock Delay Settings Updated every 8 cycles Update Enable Circuitry Output bit Delay Chain delay chains consist of a set of variable delay elements allow the input signals be shifted by the amount specified by the phase-shift circuitry or the logic array. There are two delay elements in the delay chain that have the same characteristics: Delay elements in the logic block Delay elements in the The pin is shifted by the delay settings.

22 - CV-5..8 The number of delay chains required is transparent because the UniPHY IP aumatically sets it when you choose the operating frequency. In Cyclone V E, GX, and GT devices, if you do not use the control the delay chains, you can input your own Gray-coded bit settings using the delayctrlin[..] signals available in the UniPHY IP. In the Cyclone V SE, SX, and ST devices, the delay chain is controlled by the phase-shift circuitry only. Postamble Circuitry There are preamble and postamble specifications for both read and write operations in DDR and DDR SDRAM. The postamble circuitry ensures that data is not lost if there is noise on the line during the end of a read operation that occurs while is in a postamble state. The Cyclone V devices contain dedicated postamble registers that you can control ground the shifted signal that is used clock the DQ input registers at the end of a read operation. This function ensures that any glitches on the input signal during the end of a read operation and occurring while is in a postamble state do not affect the DQ registers. For preamble state, the is low, just after a high-impedance state. For postamble state, the is low, just before it returns a high-impedance state. For external memory interfaces that use a bidirectional read strobe (DDR and DDR SDRAM), the signal is low before going or coming from a high-impedance state. Half Data Rate Block The Cyclone V devices contain a half data rate (HDR) block in the postamble enable circuitry. The HDR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock divider circuit. There is an AND gate after the postamble register outputs avoid postamble glitches from a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for dqsenable assertion and zero latency for dqsenable deassertion. Using the HDR block as the first stage capture register in the postamble enable circuitry block is optional. Altera recommends using these registers if the controller is running at half the frequency of the I/Os. Figure -: Avoiding Glitch on a Non-Consecutive Read Burst Waveform This figure shows how avoid postamble glitches using the HDR block. Postamble glitch Postamble Preamble Postamble Enable dqsenable Delayed by /T logic

23 CV-5..8 Dynamic OCT Control The dynamic OCT control block includes all the registers that are required dynamically turn the on-chip parallel termination (R T OCT) on during a read and turn R T OCT off during a write. Figure -4: Dynamic OCT Control Block for Cyclone V Devices - OCT Control Path OCT Control D Q DFF D Q DFF OCT Control D Q DFF D Q DFF OCT Enable OCT Half-Rate Clock Write Clock The full-rate write clock comes from the. The DQ write clock and write clock have a 9 offset between them For more information about dynamic OCT control, refer the I/O Features in Cyclone V Devices chapter. Registers The registers are expanded allow source-synchronous systems have faster register--fifo transfers and resynchronization. All p, botm, and right s have the same capability. Input Registers The input path consists of the DDR input registers and the read FIFO block. You can bypass each block of the input path. There are three registers in the DDR input registers block. Registers A and B capture data on the positive and negative edges of the clock while register C aligns the captured data. Register C uses the same clock as Register A. The read FIFO block resynchronizes the data the system clock domain and lowers the data rate half rate. The following figure shows the registers available in the Cyclone V input path. For DDR and DDR SDRAM interfaces, the and n signals must be inverted. If you use Altera s memory interface IPs, the and n signals are aumatically inverted.

24 - Figure -5: Input Registers for Cyclone V Devices CV-5..8 DQ Double Data Rate Input Registers D Q datain [] dataout[..] To core The input clock can be from the logic block or from a global clock line. /CQ DDFF Q Input Reg A D Q DFF Input Reg B D Q DFF Input Reg C datain [] wrclk Read FIFO rdclk This half-rate or full-rate read clock comes from a through the clock network Half-rate or full-rate clock Output Registers The Cyclone V output and output-enable path is divided in the HDR block, and output and output-enable registers. The device can bypass each block of the output and output-enable path. The output path is designed route combinarial or registered single data rate (SDR) outputs and full-rate or half-rate DDR outputs from the FPGA core. Half-rate data is converted full-rate with the HDR block, clocked by the half-rate clock from the. The output-enable path has a structure similar the output pathensuring that the output-enable path goes through the same delay and latency as the output path.

25 CV-5..8 Figure -: Output and Output-Enable Path Registers for Cyclone V Devices -5 The following figure shows the registers available in the Cyclone V output and output-enable paths. Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode From Core From Core Half Data Rate Single Data Rate Output-Enable Registers D D DFF DFF Q Q D DFF Q OE Reg A OE D DFF Q Double Data Rate Output-Enable Registers OR OE Reg B OE From Core (wdata) Half Data Rate Single Data Rate Output Registers D DFF Q D Q DFF Double Data Rate Output Registers TRI DQ or From Core (wdata) D Q OE Reg A O DFF From Core (wdata) D Q DFF D DFF Q From Core (wdata) D Q OE Reg B O DFF Half-Rate Clock from Write Clock The full-rate write clock can come from the. The DQ write clock have a 9 offset the write clock. Delay Chain The Cyclone V devices contain run-time adjustable delay chains in the I/O blocks and the logic blocks. You can control the delay chain setting through the I/O or the configuration block output. Every I/O block contains a delay chain between the following elements: The output registers and output buffer The input buffer and input register The output enable and output buffer The R T OCT enable-control register and output buffer You can bypass the delay chain achieve a phase shift.

26 - Figure -: Delay Chains in an I/O Block CV-5..8 OCT Enable Output Enable D5 OCT delay chain D5 output-enable delay chain DQ or D5 Delay delay chain D Delay delay chain Each logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input. Figure -8: Delay Chains in the Input Path Enable dqsin dqsenable delay chain D4 delay chain dqsbusout T delay chain Enable Control I/O and Configuration Blocks The I/O and configuration blocks are shift registers that you can use dynamically change the settings of various device configuration bits. The shift registers power-up low. Every I/O pin contains one I/O configuration register. Every pin contains one configuration block in addition the I/O configuration register.

27 CV-5..8 Figure -9: Configuration Block (I/O and ) - This figure shows the I/O configuration block and the configuration block circuitry. MSB bit bit bit datain update ena rankselectread rankselectwrite dataout clk For details about the I/O and configuration block bit sequence, refer the ALTDQ_ Megafunction User Guide. Hard Memory Controller The Cyclone V devices feature dedicated hard memory controllers. You can use the hard memory controllers for LPDDR, DDR, and DDR SDRAM interfaces. Compared the memory controllers implemented using core logic, the hard memory controllers allow support for higher memory interface frequencies with shorter latency cycles. The hard memory controllers use dedicated I/O pins as data, address, command, control, and clock pins for the SDRAM interface. If you do not use the hard memory controllers, you can use these dedicated pins as regular I/O pins. The hard memory controller is functionally similar the High-Performance Controller II (HPC II). For more information, refer the Functional DescriptionHPC II Controller chapter of the External Memory Interface Handbook. For detailed information about application of the hard memory interface, refer the Functional DescriptionHard Memory Interface chapter of the External Memory Interface Handbook. Features of the Hard Memory Controller Table -: Features of the Cyclone V Hard Memory Controller Feature Description Memory Interface Data Width Memory Density Memory Burst Length 8,, and bit data bit data + 8 bit ECC bit data + 8bit ECC The controller supports up four gigabits density parts and two chip selects. DDRBurst length of 8 and burst chop of 4 DDRBurst lengths of 4 and 8 LPDDRBurst lengths of, 4, 8, and

28 -8 CV-5..8 Feature Command and Data Reordering Starvation Control User-Configurable Priority Support Avalon -MM Data Slave Local Interface Bank Management Streaming Reads and Writes Bank Interleaving Predictive Bank Management Multiport Interface Built-in Burst Adapr Run-time Configuration of the Controller On-Die Termination User-Controlled Refresh Timing Low Power Modes Partial Array Self-Refresh Description The controller increases efficiency through the support for out-of-order execution of DRAM commandswith address collision detection-and in-order return of results. A starvation counter ensures that all requests are served after a predefined time-out period. This function ensures that data with low priority access are not left behind when reordering data for efficiency. When the controller detects a high priority request, it allows the request bypass the current queuing request. This request is processed immediately and thus reduces latency. By default, the controller supports the Avalon Memory-Mapped procol. By default, the controller provides closed-page bank management on every access. The controller intelligently keeps a row open based on incoming traffic. This feature improves the efficiency of the controller especially for random traffic. The controller can issue reads or writes continuously sequential addresses every clock cycle if the bank is open. This function allows for very high efficiencies with large amounts of data. The controller can issue reads or writes continuously 'random' addresses. The controller can issue bank management commands early so that the correct row is open when the read or write occurs. This increases efficiency. The interface allows you connect up six data masters access the memory controller through the local interface. You can update the multiport scheduling configuration without interrupting traffic on a port. The controller can accept bursts of arbitrary sizes on its local interface and map these bursts efficient memory commands. This feature provides support for updates the timing parameters without requiring reconfiguration of the FPGA, apart from the standard compile-time setting of the timing parameters. The controller controls the on-die termination (ODT) in the memory, which improves signal integrity and simplifies your board design. You can optionally control when refreshes occurallowing the refreshes avoid clashing of important reads or writes with the refresh lock-out time. You can optionally request the controller put the memory in the self-refresh or deep power-down modes. You can select the region of memory refresh during self-refresh through the mode register save power.

29 CV Feature Description ECC Additive Latency Write Acknowledgment Standard Hamming single error correction, double error detection (SECDED) error correction code (ECC) support: bit data + 8 bit ECC bit data + 8 bit ECC With additive latency, the controller can issue a READ/WRITE command after the ACTIVATE command the bank prior t RCD increase the command efficiency. The controller supports write acknowledgment on the local interface. User Control of Memory Controller Initialization The controller supports initialization of the memory controller under the control of user logicfor example, through the software control in the user system if a processor is present. Controller Bonding Support You can bond two controllers achieve wider data width for higher bandwidth applications. Multi-Port Front End The multi-port front end (MPFE) and its associated fabric interface provide up six command ports, four read-data ports and four write-data ports, through which user logic can access the hard memory controller. Figure -: Simplified Diagram of the Cyclone V Hard Memory Interface This figure shows a simplified diagram of the Cyclone V hard memory interface with the MPFE. Hard Memory Controller FPGA FPGA Core Logic MPFE Memory Controller PHY Memory Avalon-MM Interface AFI Bonding Support You can bond two hard memory controllers support wider data widths. When you bond two hard memory controllers, the data going out of the controllers the user logic is synchronized. However, the data going out of the controllers the memory is not synchronized. The bonding controllers are not synchronized and remain independent with two separate address buses and two independent command buses. These buses are calibrated separately. If you require ECC support for a bonded interface, you must implement the ECC logic external the hard memory controllers. Note: A memory interface that uses the bonding feature has higher average latency. Bonding through the core fabric will also cause a higher latency.

30 - CV-5..8 Figure -: Hard Memory Controllers Bonding Support in Cyclone V E A, A5, and A9 Devices, Cyclone V GX C4, C5, C, and C9 Devices, and Cyclone V GT D5, D, and D9 Devices This figure shows the bonding of two opposite hard memory controllers through the core fabric. The botm hard memory controller is not supported in the Cyclone V GX C5 device for the./. V configuration. Bank 8A Bank A Hard Memory Controller Bonding (Core Routing) Hard Memory Controller Bank A Bank B Bank 4A

31 CV-5..8 Figure -: Hard Memory Controllers in Cyclone V SX C, C4, C5, and C Devices, and Cyclone V ST D5 and D Devices This figure shows hard memory controllers in the SoC FPGAs. There is no bonding support. - Bank 8A HPS I/O HPS Block HPS Hard Memory Controller Bank 5 HPS I/O -bit DDR Interface Hard Memory Controller Bank A Bank B Bank 4A -bit Interface For more information about the dedicated pins, refer the Cyclone V Device Family Connection Guidelines. Hard Memory Controller Width for Cyclone V E Table -4: Hard Memory Controller Width Per Side in Cyclone V E DevicesPreliminary Member Code Package A A4 A5 A A9 M8 M484 F5 U U484 F F F

32 - Hard Memory Controller Width for Cyclone V GX CV-5..8 Table -5: Hard Memory Controller Width Per Side in Cyclone V GX DevicesPreliminary Member Code Package C C4 C5 C C9 M M8 M484 U U484 F F F F5 4 4 Hard Memory Controller Width for Cyclone V GT Table -: Hard Memory Controller Width Per Side in Cyclone V GT DevicesPreliminary Member Code Package D5 D D9 M M8 M484 U484 F F F F5 4 4

33 CV-5..8 Hard Memory Controller Width for Cyclone V SX - Table -: Hard Memory Controller Width Per Side in Cyclone V SX DevicesPreliminary Member Code Package C C4 C5 C U F Hard Memory Controller Width for Cyclone V ST Table -8: Hard Memory Controller Width Per Side in Cyclone V ST DevicesPreliminary Member Code Package D5 D F Document Revision Hisry Date December Version..8 Changes Reorganized content and updated template. Added a list of supported external memory interface standards using the hard memory controller and soft memory controller. Added performance information for external memory interfaces and the HPS external memory interfaces. Separated the DQ/ groups tables in separate pics for each device variant for easy reference. Updated the DQ/ numbers and device packages for the Cyclone V E, GX, GT, SX, and ST variants. Moved the PHYCLK networks pin placement guideline the Planning and FPGA Resources chapter of the External Memory Interface Handbook. Moved information from the "Design Considerations" section in relevant pics. Removed the "DDR SDRAM Interface" and "DDR SDRAM DIMM" sections. Refer the relevant sections in the External Memory Interface Handbook for the information. Added the I/O and configuration blocks pic. Updated the term "Multiport logic" "multi-port front end" (MPFE). Added information about the hard memory controller interface widths for the Cyclone V E, GX, GT, SX, and ST variants.

34 -4 CV-5..8 Date June February November Ocber Version.... Changes Updated for the Quartus II software v. release: Restructured chapter. Updated Design Considerations, Postamble Circuitry, and Registers sections. Added SoC devices information. Added Figure 5, Figure, and Figure. Updated Figure. Minor text edits. Updated Table. Added Figure. Initial release.