CS152 / Kubiatowicz Lec23.1. Capacity Access Time Cost. CPU Registers 100s Bytes <10s ns. Cache K Bytes ns $ /bit

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1 Recap: Set Associative Cache CS152 Computer Architecture and Engineering Lecture 23 Virtual (cont) es and #1 April 17, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) Valid N-way set associative: N entries for each Cache Index N direct mapped caches operates in parallel Example: Two-way set associative cache Cache Index selects a set from the cache The two tags in the set are compared to the input in parallel Data is selected based on the tag result Cache Tag Cache Data Cache Block 0 : : : Cache Index Cache Data Cache Block 0 : Cache Tag Valid : : lecture slides: Adr Tag Compare 1 Sel1 Mux 0 Sel0 Compare Lec23.1 OR Cache Block Hit Lec23.2 Recap: A Summary on Sources of Cache Misses Recall: Levels of the Hierarchy Compulsory (cold start or process migration, first reference): first access to a block Cold fact of life: not a whole lot you can do about it Note: If you are going to run billions of instruction, Compulsory Misses are insignificant Conflict (collision): Multiple memory locations mapped to the same cache location Solution 1: increase cache size Solution 2: increase associativity Capacity: Cache cannot contain all blocks access by the program Solution: increase cache size Coherence (Invalidation): other process (e.g., ) updates memory Lec23.3 Capacity Access Time Cost CPU Registers 100s Bytes <10s ns Cache K Bytes ns $ /bit Main M Bytes 100ns-1us $ Registers Cache Instr. Operands Blocks Pages Disk G Bytes Disk ms cents Files Tape infinite sec-min 10-6 Tape Staging Xfer Unit prog./compiler 1-8 bytes cache cntl bytes OS 512-4K bytes user/operator Mbytes Upper Level faster Larger Lower Level Lec23.4

2 Virtual Address Space What is virtual memory? Physical Address Space Virtual Address V page no. Page Table Base Reg index into page table Virtual memory => treat memory as a cache for the disk Terminology: blocks in this cache are called Pages Typical size of a page: 1K 8K Page table maps virtual page numbers to physical frames PTE = Page Table Entry Page Table V Access Rights 10 offset PA table located in physical memory P page no. offset 10 Physical Address Lec23.5 Three Advantages of Virtual Translation: Program can be given consistent view of memory, even though physical memory is scrambled Makes multithreading reasonable (now used a lot!) Only the most important part of program ( Working Set ) must be in physical memory. Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later. Protection: Different threads (or processes) protected from each other. Different pages can be given special behavior - (Read Only, Invisible to user programs, etc). Kernel data protected from User programs Very important for protection from malicious programs => Far more viruses under Microsoft Windows Sharing: Can map same physical page to multiple users ( Shared memory ) Lec23.6 Issues in Virtual System Design How big is the translation (page) table? What is the size of information blocks that are transferred from secondary to main storage (M)? Ÿ page size (Contrast with physical block size on disk, I.e. sector size) Virtual Page Number Page Offset Which region of M is to hold the new block Ÿ placement policy How do we find a page when we look for it? Ÿ block identification Block of information brought into M, and M is full, then some region of M must be released to make room for the new block Ÿ replacement policy What do we do on a write? Ÿ write policy Missing item fetched from secondary memory only on the occurrence of a fault Ÿ demand load policy reg cache mem frame disk pages Lec23.7 Simplest way to implement fully associative lookup policy is with large lookup table. Each entry in table is some number of bytes, say 4 With 4K pages, 32- bit address space, need: 2 32 /4K = 2 20 = 1 Meg entries x 4 bytes = 4MB With 4K pages, 64-bit address space, need: 2 64 /4K = 2 52 entries = BIG! Can t keep whole page table in memory! Lec23.8

3 Large Address Spaces Inverted Page Tables Two-level Page Tables 32-bit address: P1 index P2 index page offest 1K PTEs 4KB IBM System 38 (AS400) implements 64-bit addresses. 48 bits translated start of object contains a 12-bit tag Virtual Page hash V.Page P. Frame 4 bytes 2 GB virtual address space 4 MB of PTE2 paged, holes 4 KB of PTE1 = What about a bit address space? 4 bytes Lec23.9 => TLBs or virtually addressed caches are critical Lec23.10 Virtual Address and a Cache: Step backward??? CPU VA PA miss Translation Cache data hit Main Virtual memory seems to be really slow: Must access memory on load/store -- even cache hits! Worse, if translation not completely in memory, may need to go to disk before hitting in cache! Solution: Caching! (surprise!) Keep track of most common translations and place them in a Translation Lookaside Buffer (TLB) Making address translation practical: TLB Virtual memory => memory acts like a cache for the disk Page table maps virtual page numbers to physical frames Translation Look-aside Buffer (TLB) is a cache translations Virtual Address Space Physical Space virtual address page off Page Table TLB frame page physical address page off Lec23.11 Lec23.12

4 TLB organization: include protection Virtual Address Physical Address Dirty Ref Valid Access ASID 0xFA00 0x0003 Y N Y R/W 34 0x0040 0x0010 N Y Y R 0 0x0041 0x0011 N Y Y R 0 TLB usually organized as fully-associative cache Lookup is by Virtual Address Returns Physical Address + other info Dirty => Page modified (Y/N)? Ref => Page touched (Y/N)? Valid => TLB entry valid (Y/N)? Access => Read? Write? ASID => Which User? Lec23.13 What is the replacement policy for TLBs? On a TLB miss, we check the page table for an entry. Two architectural possibilities: Hardware table-walk (Sparc, among others) - Structure of page table must be known to hardware Software table-walk (MIPS was one of the first) - Lots of flexibility - Can be expensive with modern operating systems. What if missing Entry is not in page table? This is called a Page Fault Ÿ requested virtual page is not in memory Operating system must take over (CS162) - pick a page to discard (possibly writing it to disk) - start loading the page in from disk - schedule some other process to run Note: possible that parts of page table are not even in memory (I.e. paged out!) The root of the page table always pegged in memory Lec23.14 Page Replacement: Not Recently Used (1-bit LRU, Clock) Page Replacement: Not Recently Used (1-bit LRU, Clock) Set of all pages in Tail pointer: Mark pages as not used recently Freelist Associated with each page is a used flag such that used flag = 1 if the page has been referenced in recent past = 0 otherwise -- if replacement is necessary, choose any page frame such that its used bit is 0. This is a page that has not been referenced recently page table entry dirty used 1 0 page table entry Tail pointer Head pointer Head pointer: Place pages on free list if they are still marked as not used. Schedule dirty pages for writing to disk Free Pages Lec23.15 Or search for the a page that is both not recently referenced AND not dirty. Architecture part: support dirty and used bits in the page table => may need to update PTE on any instruction fetch, load, store How does TLB affect this design problem? Software TLB miss? Lec23.16

5 Reducing translation time further As described, TLB lookup is in serial with cache lookup: Virtual Address V page no. 10 offset TLB Lookup 32 Overlapped TLB & Cache Access If we do this in parallel, we have to be careful, however: TLB assoc lookup index 4K Cache 1 K V Access Rights PA P page no. Physical Address Machines with TLBs go one step further: they overlap TLB lookup with cache access. Works because lower bits of result (offset) available early offset 10 Lec23.17 Hit/ Miss FN 20 page # 10 2 disp 00 What if cache size is increased to 8KB? = 4 bytes FN Data Hit/ Miss Lec23.18 Problems With Overlapped TLB Access Overlapped access only works as long as the address bits used to index into the cache do not change as the result of VA translation This usually limits things to small caches, large page sizes, or high n-way set associative caches if you want a large cache Example: suppose everything the same except that the cache is increased to 8 K bytes instead of 4 K: 11 2 cache index This bit is changed by VA translation, but is needed for cache virt page # disp lookup Solutions: go to 8K byte page sizes; go to 2 way set associative cache; or SW guarantee VA[13]=PA[13] 1K way set assoc cache Lec23.19 Another option: Virtually Addressed Cache CPU VA hit Translation Cache data Only require address translation on cache miss! synonym problem: two different virtual addresses map to same physical address => two different cache entries holding data for the same physical address! nightmare for update: must update all cache entries with same physical address or memory becomes inconsistent determining this requires significant hardware, essentially an associative lookup on the physical address tags to see if you have multiple hits. (usually disallowed by fiat) PA Main Lec23.20

6 Cache Optimization: Alpha Administrivia Separate Instr & Data TLB & Caches TLBs fully associative TLB updates in SW ( Priv Arch Libr ) Caches 8KB direct mapped, write thru Critical 8 bytes first Prefetch instr. stream buffer 2 MB L2 cache, direct mapped, WB (off-chip) 256 bit path to main memory, 4 x 64-bit modules Victim Buffer: to give read priority over write 4 entry write buffer between D$ & L2$ Stream Buffer Instr Data Write Buffer Midterm II: Tuesday 5/1 Review session Sunday 4/29 5:30 8:30 in 277 Cory - Pizza afterwards Topics - Pipelining - Caches/ systems - es and - Power Tomorrow: demonstrate lab 6 to TAs in 119 Cory Important: Lab 7. Design for Test You should be testing from the very start of your design Consider adding special monitor modules at various points in design => I have asked you to label trace output from these modules with the current clock cycle # The time to understand how components of your design should work is while you are designing! 4/17/01 Victim UCB Buffer Spring 2001 Lec23.21 Lec23.22 Administrivia II Computers in the news: Pentium 4 Major organizational options: 2-way superscalar (18 points) Original Pentium 2-way multithreading (20 points) 2-way multiprocessor (18 points) out-of-order execution (22 points) Deep Pipelined (12 points) Pentium II/III Test programs will include multiprocessor versions Both multiprocessor and multithreaded must implement synchronizing Test and Set instruction: Pentium 4 Normal load instruction, with special address range: - Addresses from 0xFFFFFFF0 to 0xFFFFFFFF - Only need to implement 16 synchronizing locations Reads and returns old value of memory location at specified address, while setting the value to one (stall memory stage for Many pipeline stages one extra cycle). Even pipelining for wires! For multiprocessor, this instruction must make sure that all updates to this address are suspended during operation. Branch prediction, data prediction For multithreaded, switch to other processor if value is already Trace-cache 4/17/01 non-zero (like a cache miss). UCB Spring 2001 Lec23.23 Lec23.24

7 Pentium 4 study Bert McComas InQuest Marketing Research Summary: Pentium 4 rated at 54.7 Watts, but peaks out at 72.9 W - Thermal limiter kicks in if you run too hot - Reduces internal clock rate to ½ normal rate - So, while you can read at 1.5Ghz, other operations work at an effective rate of 750Mhz Pentium 4 uses 4 times as much memory bandwidth as Pentium 3 on SpecInt Vortex benchmark Pentium 4: Weird Anomalies: Excess bandwidth Uses almost 4 times as much memory bandwidth as P3 Longer cache line size insufficient temporal locality? Adds 33% to miss penalty Lec23.25 Lec23.26 Pentium 4: Weird Anomalies: Only 3.5% performance gain? What is a bus? A Is: shared communication link single set of wires used to connect multiple subsystems Processor Control Datapath Input Output Clock rate and high memory bandwidth don t buy much! Why bother? AMD Athlon processor has better performance/mhz A is also a fundamental tool for composing large, complex systems systematic means of abstraction Lec23.27 Lec23.28

8 es Advantages of es Processer Device Device Device Versatility: New devices can be added easily Peripherals can be moved between computer systems that use the same bus standard Low Cost: A single set of wires is shared in multiple ways Lec23.29 Lec23.30 Disadvantage of es The General Organization of a Control Lines Data Lines Processer Device Device It creates a communication bottleneck The bandwidth of that bus can limit the maximum throughput The maximum bus speed is largely limited by: The length of the bus The number of devices on the bus The need to support a range of devices with: - Widely varying latencies - Widely varying data transfer rates Device Lec23.31 Control lines: Signal requests and acknowledgments Indicate what type of information is on the data lines Data lines carry information between the source and the destination: Data and Addresses Complex commands Lec23.32

9 Master versus Slave Master Master issues command Data can go either way A bus transaction includes two parts: Issuing the command (and address) request Transferring the data action Master is the one who starts the bus transaction by: issuing the command (and address) Slave is the one who responds to the address by: Sending data to the master if the master ask for data Receiving data from the master if the master wants to send data Slave Lec23.33 What is DMA (Direct Access)? Typical devices must transfer large amounts of data to memory of processor: Disk must transfer complete block (4K? 16K?) Large packets from network Regions of frame buffer DMA gives external device ability to write memory directly: much lower overhead than having processor request one word at a time. Processor (or at least memory system) acts like slave Issue: Cache coherence: What if devices write data that is currently in processor Cache? - The processor may never see new data! Solutions: - Flush cache on every operation (expensive) - Have hardware invalidate cache lines (remember Coherence cache misses?) Lec23.34 Types of es Processor- (design specific) Short and high speed Only need to match the memory system - Maximize memory-to-processor bandwidth Connects directly to the processor Optimized for cache block transfers (industry standard) Usually is lengthy and slower Need to match a wide range of devices Connects to the processor-memory bus or backplane bus Backplane (standard or proprietary) Backplane: an interconnection structure within the chassis Allow processors, memory, and devices to coexist Cost advantage: one bus for all components Lec23.35 Example: Pentium System Organization Processor/ PCI ses Lec23.36

10 A Computer System with One : Backplane A Two- System Processor Backplane Processor Adaptor Processor Adaptor Adaptor Devices A single bus (the backplane bus) is used for: Processor to memory communication Communication between devices and memory Advantages: Simple and low cost Disadvantages: slow and the bus can become a major bottleneck Example: IBM PC - AT Lec23.37 buses tap into the processor-memory bus via bus adaptors: Processor-memory bus: mainly for processor-memory traffic buses: provide expansion slots for devices Apple Macintosh-II Nu: Processor, memory, and a few selected devices SCCI : the rest of the devices Lec23.38 A Three- System (+ backside cache) Main componenets of Intel Chipset: Pentium II/III Backside Cache bus Processor L2 Cache Adaptor Processor Adaptor Adaptor A small number of backplane buses tap into the processor-memory bus Processor-memory bus is only used for processor-memory traffic buses are connected to the backplane bus Advantage: loading on the processor bus is greatly reduced Lec23.39 Northbridge: Handles memory Graphics Southbridge: PCI bus Disk controllers USB controlers Audio Serial Interrupt controller Timers Lec23.40

11 What defines a bus? Transaction Protocol Timing and Signaling Specification Bunch of Wires Electrical Specification Physical / Mechanical Characterisics the connectors Synchronous and Asynchronous Synchronous : Includes a clock in the control lines A fixed protocol for communication that is relative to the clock Advantage: involves very little logic and can run very fast Disadvantages: - Every device on the bus must run at the same clock rate - To avoid clock skew, they cannot be long if they are fast Asynchronous : It is not clocked It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol Lec23.41 Lec23.42 ses so far Transaction Master Slave Control Lines Address Lines Data Lines Arbitration: Who gets the bus Request: What do we want to do Action: What happens in response Master: has ability to control the bus, initiates transaction Slave: module activated by the transaction Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Transfers: sequence relative to common clock. Lec23.43 Lec23.44

12 Arbitration: Obtaining Access to the Master Control: Master initiates requests Data can go either way One of the most important issues in bus design: How is the bus reserved by a device that wishes to use it? Chaos is avoided by a master-slave arrangement: Only the bus master can control access to the bus: It initiates and controls all bus requests A slave responds to read and write requests The simplest system: Processor is the only bus master All bus requests must be controlled by the processor Major drawback: the processor is involved in every transaction Slave Lec23.45 Multiple Potential Masters: the Need for Arbitration arbitration scheme: A bus master wanting to use the bus asserts the bus request A bus master cannot use the bus until its request is granted A bus master must signal to the arbiter after finish using the bus arbitration schemes usually try to balance two factors: priority: the highest priority device should be serviced first Fairness: Even the lowest priority device should never be completely locked out from the bus arbitration schemes can be divided into four broad classes: Daisy chain arbitration Centralized, parallel arbitration Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. Distributed arbitration by collision detection: Each device just goes for it. Problems found after the fact. Lec23.46 The Daisy Chain Arbitrations Scheme Centralized Parallel Arbitration Device 1 Highest Priority Device 2 Device N Lowest Priority Device 1 Device 2 Device N Arbiter Grant Grant Grant Release Request Arbiter Grant Req wired-or Advantage: simple Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed Lec23.47 Used in essentially all processor-memory busses and in high-speed busses Lec23.48

13 Simplest bus paradigm Simple Synchronous Protocol BReq BG All agents operate synchronously All can source / sink data at same rate => simple protocol just manage the source and target R/W Address Data Cmd+Addr Data1 Data2 Even memory busses are more complex than this memory (slave) may take time to respond it may need to control data rate Lec23.49 Lec23.50 BReq BG R/W Address Wait Typical Synchronous Protocol Data Cmd+Addr Data1 Data1 Slave indicates when it is prepared for data xfer Actual transfer goes at bus rate Data2 Lec23.51 Increasing the Bandwidth Separate versus multiplexed address and data lines: Address and data can be transmitted in one bus cycle if separate address and data lines are available Cost: (a) more bus lines, (b) increased complexity Data bus width: By increasing the width of the data bus, transfers of multiple words require fewer bus cycles Example: SPARCstation 20 s memory bus is 128 bit wide Cost: more bus lines Block transfers: Allow the bus to transfer multiple words in back-to-back bus cycles Only one address needs to be sent at the beginning The bus is not released until the last word is transferred Cost: (a) increased complexity (b) decreased response time for request Lec23.52

14 Increasing Transaction Rate on Multimaster Overlapped arbitration perform arbitration for next transaction during current transaction parking master can holds onto bus and performs multiple transactions as long as no other master makes request Overlapped address / data phases (prev. slide) requires one of the above techniques Split-phase (or packet switched) bus completely separate address and data phases arbitrate separately for each address phase yield a tag which is matched with data phase All of the above in most modern buses Lec MP Server Survey: GTL revolution M Summit Challenge XD Originator Sun HP SGI Sun Clock Rate (MHz) Address lines muxed Data lines (parity) Data Sizes (bits) Clocks/transfer 4 5 4? Peak (MB/s) 320(80) Master Multi Multi Multi Multi Arbitration Central Central Central Central Slots ses/system Length 13 inches 12? inches 17 inches Lec23.54 Asynchronous Handshake Read Transaction Write Transaction Address Data Read Req Ack Master Asserts Address Master Asserts Data Next Address Address Data Read Req Ack Master Asserts Address Slave Data Next Address t0 t1 t2 t3 t4 t5 t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target. t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack Lec23.55 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target. t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack Lec23.56

15 1993 Backplane/IO Survey S TurboChannel MicroChannel PCI Originator Sun DEC IBM Intel Clock Rate (MHz) async 33 Addressing Virtual Physical Physical Physical Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64 Master Multi Single Multi Multi Arbitration Central Central Central Central 32 bit read (MB/s) Peak (MB/s) (222) Max Power (W) Lec23.57 PCI Read/Write Transactions All signals sampled on rising edge Centralized Parallel Arbitration overlapped with previous transaction All transfers are (unlimited) bursts Address phase starts by asserting FRAME# Next cycle initiator asserts cmd and address Data transfers happen on when IRDY# asserted by master when ready to transfer data TRDY# asserted by target when ready to transfer data transfer when both asserted on rising edge FRAME# deasserted when master intends to complete only one more data transfer Lec23.58 PCI Read Transaction PCI Write Transaction Turn-around cycle on any signal driven by more than one agent Lec23.59 Lec23.60

16 PCI Optimizations Push bus efficiency toward 100% under common simple usage like RISC Parking retain bus grant for previous master until another makes request granted master can start next transfer without arbitration Arbitrary Burst length initiator and target can exert flow control with xrdy target can disconnect request with STOP (abort or retry) master can disconnect by deasserting FRAME arbiter can disconnect by deasserting GNT Delayed (pended, split-phase) transactions free the bus after request to slow device Lec23.61 Summary #1 / 2: Virtual VM allows many processes to share single memory without having to swap all processes to disk Translation, Protection, and Sharing are more important than memory hierarchy Page tables map virtual address to physical address TLBs are a cache on translation and are extremely important for good performance Special tricks necessary to keep TLB out of critical cache-access path TLB misses are significant in processor performance: - These are funny times: most systems can t access all of 2nd level cache without TLB misses! Lec23.62 Summary #2 / 2 es are an important technique for building largescale systems Their speed is critically dependent on factors such as length, number of devices, etc. Critically limited by capacitance Tricks: esoteric drive technology such as GTL Important terminology: Master: The device that can initiate new transactions Slaves: Devices that respond to the master Two types of bus timing: Synchronous: bus includes clock Asynchronous: no clock, just REQ/ACK strobing Direct Access (dma) allows fast, burst transfer into processor s memory: Processor s memory acts like a slave Probably requires some form of cache-coherence so that DMA ed memory can be invalidated from cache. Lec23.63