Recap: Making address translation practical: TLB. CS152 Computer Architecture and Engineering Lecture 24. Busses (continued) Queueing Theory Disk IO

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1 Recap: Making address translation practical: TLB CS152 Computer Architecture and Engineering Lecture 24 Virtual memory => memory acts like a cache for the disk Page table maps virtual page numbers to physical frames Translation Look-aside Buffer (TLB) is a cache translations ses (continued) ing Theory Disk IO Virtual Address Space Physical Memory Space virtual address page off Page Table 2 November 28, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: TLB frame page physical address page off Lec24.1 Lec24.2 Recap: Overlapped TLB & Cache Access Recap: A Three- System (+ backside cache) If we do this in parallel, we have to be careful, however: Processor Processor Memory Memory 32 Hit/ Miss TLB FN assoc lookup 20 page # index 10 2 disp 00 = 4K Cache 4 bytes 1 K FN Data Hit/ Miss Backside Cache bus L2 Cache Adaptor Adaptor Adaptor I/O I/O A small number of backplane buses tap into the processor-memory bus Processor-memory bus is only used for processor-memory traffic I/O buses are connected to the backplane bus Advantage: loading on the processor bus is greatly reduced What if cache size is increased to 8KB? Lec24.3 Lec24.4

2 Recap: Main components of Intel Chipset: Pentium II/III Northbridge: Handles memory Graphics Southbridge: I/O PCI bus Disk controllers USB controlers Audio Serial I/O Interrupt controller Timers Recap: Synchronous and Asynchronous Synchronous : Includes a clock in the control lines A fixed protocol relative to the clock Advantage: little logic and very fast Disadvantages: - Every device on the bus must run at the same clock rate - To avoid clock skew, they cannot be long if they are fast Asynchronous : It is not clocked It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol Lec24.5 Lec24.6 Multiple Potential Masters: the Need for Arbitration arbitration scheme: A bus master wanting to use the bus asserts the bus request A bus master cannot use the bus until its request is granted A bus master must signal to the arbiter after finish using the bus arbitration schemes usually try to balance two factors: priority: the highest priority device should be serviced first Fairness: Even the lowest priority device should never be completely locked out from the bus arbitration schemes can be divided into four broad classes: Daisy chain arbitration Centralized, parallel arbitration Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. Distributed arbitration by collision detection: Each device just goes for it. Problems found after the fact. Arbitration: Obtaining Access to the Master Control: Master initiates requests Data can go either way One of the most important issues in bus design: How is the bus reserved by a device that wishes to use it? Chaos is avoided by a master-slave arrangement: Only the bus master can control access to the bus: It initiates and controls all bus requests A slave responds to read and write requests Slave The simplest system: Processor is the only bus master All bus requests must be controlled by the processor Major drawback: the processor is involved in every transaction Lec24.7 Lec24.8

3 The Daisy Chain Arbitrations Scheme Centralized Parallel Arbitration Device 1 Highest Priority Device 2 Device N Lowest Priority Device 1 Device 2 Device N Arbiter Grant Grant Grant Release Request Arbiter Grant Req wired-or Advantage: simple Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed Used in essentially all processor-memory busses and in high-speed I/O busses Lec24.9 Lec24.10 Increasing the Bandwidth Separate versus multiplexed address and data lines: Address and data can be transmitted in one bus cycle if separate address and data lines are available Cost: (a) more bus lines, (b) increased complexity Data bus width: By increasing the width of the data bus, transfers of multiple words require fewer bus cycles Example: SPARCstation 20 s memory bus is 128 bit wide Cost: more bus lines Block transfers: Allow the bus to transfer multiple words in back-to-back bus cycles Only one address needs to be sent at the beginning The bus is not released until the last word is transferred Cost: (a) increased complexity (b) decreased response time for request Increasing Transaction Rate on Multimaster Overlapped arbitration perform arbitration for next transaction during current transaction parking master can holds onto bus and performs multiple transactions as long as no other master makes request Overlapped address / data phases (prev. slide) requires one of the above techniques Split-phase (or packet switched) bus completely separate address and data phases arbitrate separately for each address phase yield a tag which is matched with data phase All of the above in most modern buses Lec24.11 Lec24.12

4 What is DMA (Direct Memory Access)? Typical I/O devices must transfer large amounts of data to memory of processor: Disk must transfer complete block Large packets from network Regions of frame buffer DMA gives external device ability to access memory directly: much lower overhead than having processor request one word at a time. Issue: Cache coherence: What if I/O devices write data that is currently in processor Cache? - The processor may never see new data! Solutions: - Flush cache on every I/O operation (expensive) - Have hardware invalidate cache lines (remember Coherence cache misses?) Lec24.13 Administrivia Get going on Lab 7! Status update due Monday in Section Talk with Tas about the state of your project Midterm II on Friday 5:30 8:30 in 277 Cory - Pizza afterwards Topics - Pipelining - Caches/Memory systems - es and I/O (Disk equation) - Power - ing theory? Can bring 1 page of notes - Handwitten, double-sided - CLOSED BOOK! Lec24.14 I/O System Design Issues Performance Expandability Resilience in the face of failure I/O Device Examples Device Behavior Partner Data Rate (KB/sec) Keyboard Input Human 0.01 Processor Cache interrupts Memory - I/O Mouse Input Human 0.02 Line Printer Output Human 1.00 Floppy disk Storage Machine Laser Printer Output Human Optical Disk Storage Machine Main Memory I/O Controller I/O Controller I/O Controller Magnetic Disk Storage Machine 5, Network-LAN Input or Output Machine 20 1, Disk Disk Graphics Network Graphics Display Output Human 30, Lec24.15 Lec24.16

5 I/O System Performance Simple Producer-Server Model I/O System performance depends on many aspects of the system ( limited by weakest link in the chain ): The CPU The memory system: - Internal and external caches - Main Memory The underlying interconnection (buses) The I/O controller The I/O device The speed of the I/O software (Operating System) The efficiency of the software s use of the I/O devices Two common performance metrics: Throughput: I/O bandwidth Response time: Latency Lec24.17 Producer Throughput: The number of tasks completed by the server in unit time In order to get the highest possible throughput: - The server should never be idle - The queue should never be empty Response time: Begins when a task is placed in the queue Ends when it is completed by the server In order to minimize the response time: - The queue should be empty - The server will be idle Server Lec24.18 Throughput versus Respond Time Throughput Enhancement Response Time (ms) 300 Server 200 Producer Server % 40% 60% 80% 100% Percentage of maximum throughput In general throughput can be improved by: Throwing more hardware at the problem reduces load-related latency Response time is much harder to reduce: Ultimately it is limited by the speed of light (but we re far from it) Lec24.19 Lec24.20

6 Technology Trends Today: Processing Power Doubles Every 18 months Today: Memory Size Doubles Every 18 months(4x/3yr) Today: Disk Capacity Doubles Every 18 months Disk Capacity now doubles every 18 months; before 1990 every 36 months The The I/O I/O GAP GAP Storage Technology Drivers Driven by the prevailing computing paradigm 1950s: migration from batch to on-line processing 1990s: migration to ubiquitous computing - computers in phones, books, cars, video cameras, - nationwide fiber optical network with wireless tails Effects on storage industry: Embedded storage - smaller, cheaper, more reliable, lower power Data utilities - high capacity, hierarchically managed storage Disk Positioning Rate (Seek + Rotate) Doubles Every Ten Years! Lec24.21 Lec24.22 Disk History Disk History Data density Mbit/sq. in. Capacity of Unit Shown Megabytes 1973: 1. 7 Mbit/sq. in 140 MBytes 1979: 7. 7 Mbit/sq. in 2,300 MBytes source: New York Times, 2/23/98, page C3, Makers of disk drives crowd even mroe data into even smaller spaces 1989: 63 Mbit/sq. in 60,000 MBytes 1997: 1450 Mbit/sq. in 2300 MBytes source: New York Times, 2/23/98, page C3, Makers of disk drives crowd even more data into even smaller spaces 1997: 3090 Mbit/sq. in 8100 MBytes Lec24.23 Lec24.24

7 MBits per square inch: DRAM as % of Disk over time 40% 35% 30% 25% 20% 15% 10% 5% 0.2 v. 1.7 Mb/si 9 v. 22 Mb/si 0% source: New York Times, 2/23/98, page C3, Makers of disk drives crowd even more data into even smaller spaces 470 v Mb/si Nano-layered Disk Heads Special sensitivity of Disk head comes from Giant Magneto-Resistive effect or (GMR) IBM is leader in this technology Same technology as TMJ-RAM breakthrough we described in earlier class. Coil for writing Lec24.25 Lec24.26 Organization of a Hard Magnetic Disk Magnetic Disk Characteristic Track Sector Platters Track Sector Typical numbers (depending on the disk size): 500 to 2,000 tracks per surface 32 to 128 sectors per track - A sector is the smallest unit that can be read or written Traditionally all tracks have the same number of sectors: Constant bit density: record more sectors on the outer tracks Recently relaxed: constant bit size, speed varies with track location Lec24.27 Cylinder: all the tacks under the head at a given point on all surface Read/write data is a three-stage process: Seek time: position the arm over the proper track Rotational latency: wait for the desired sector to rotate under the read/write head Transfer time: transfer a block of bits (sector) under the read-write head Average seek time as reported by the industry: Typically in the range of 8 ms to 12 ms (Sum of the time for all possible seek) / (total # of possible seeks) Due to locality of disk reference, actual average seek time may: Only be 25% to 33% of the advertised number Head Cylinder Platter Lec24.28

8 Typical Numbers of a Magnetic Disk Average seek time as reported by the industry: Typically in the range of 8 ms to 12 ms Due to locality of disk reference may only be 25% to 33% of the advertised number Rotational Latency: Most disks rotate at 3,600 to 7200 RPM Approximately 16 ms to 8 ms per revolution, respectively An average latency to the desired information is halfway around the disk: 8 ms at 3600 RPM, 4 ms at 7200 RPM Head Track Sector Cylinder Platter Disk I/O Performance Request Rate Processor O Disk Controller Disk Disk Access Time = Seek time + Rotational Latency + Transfer time + Controller Time + ing Delay P Service Rate Disk Controller Disk Transfer Time is a function of : Transfer size (usually a sector): 1 KB / sector Rotation speed: 3600 RPM to RPM Recording density: bits per inch on a track Diameter typical diameter ranges from 2.5 to 5.25 in Typical values: 2 to 40 MB per second Lec24.29 Estimating Length: Utilization = U = Request Rate / Service Rate= O / P Mean Length = U / (1 - U) As Request Rate -> Service Rate - Mean Length -> Infinity Lec24.30 Disk Device Terminology Example 512 byte sector, rotate at 5400 RPM, advertised seeks is 12 ms, transfer rate is 4 MB/sec, controller overhead is 1 ms, queue idle so no service time Disk Access Time = Seek time + Rotational Latency + Transfer time + Controller Time + ing Delay Disk Access Time = 12 ms / 5400 RPM KB / 4 MB/s + 1 ms + 0 Disk Latency = ing Time + Controller time + Seek Time + Rotation Time + Xfer Time Order of magnitude times for 4K byte transfers: Average Seek: 8 ms or less Rotate: rpm Disk Access Time = 12 ms / 90 RPS / 1024 s + 1 ms + 0 Disk Access Time = 12 ms ms ms + 1 ms + 0 ms Disk Access Time = 18.6 ms If real seeks are 1/3 advertised seeks, then its 10.6 ms, with rotation delay at 50% of the time! Xfer: rpm Lec24.31 Lec24.32

9 Reliability and Availability Simple Producer-Server Model Two terms that are often confused: Reliability: Is anything broken? Availability: Is the system still available to the user? Producer Server Availability can be improved by adding hardware: Example: adding ECC on memory Reliability can only be improved by: Better environmental conditions Building more reliable components Building with fewer components - Improve availability may come at the cost of lower reliability Lec24.33 Throughput: The number of tasks completed by the server in unit time In order to get the highest possible throughput: - The server should never be idle - The queue should never be empty Response time: Begins when a task is placed in the queue Ends when it is completed by the server In order to minimize the response time: - The queue should be empty - The server will be idle Lec24.34 Disk I/O Performance Introduction to ing Theory Metrics: Response Time Throughput latency goes as T ser u/(1-u) u = utilization Proc Response Time (ms) Throughput (% total BW) Response time = + Device Service time 0 0% IOC Device 100% Arrivals Black Box ing System Departures ing Theory applies to long term, steady state behavior Ÿ Arrival rate = Departure rate Little s Law: Mean number tasks in system = arrival rate x mean reponse time Observed by many, Little was first to prove Simple interpretation: you should see the same number of tasks in queue when entering as when leaving. Applies to any system in equilibrium, as long as nothing in black box is creating or destroying tasks Lec24.35 Lec24.36

10 A Little Queuing Theory: Notation A Little Queuing Theory: Use of random distributions System server Proc IOC Device System server Proc IOC Device Avg. Queuing models assume state of equilibrium: input rate = output rate Notation: O average number of arriving customers/second T ser average time to service a customer (tradtionally µ = 1/ T ser ) u server utilization (0..1): u = O x T (or u = O / µ ) ser average time/customer in queue T sys average time/customer in system: T sys = +T ser L q average length of queue: L q = O x L sys average length of system: L sys = O xt sys Little s Law: L sys = O x T sys (Mean number customers = arrival rate x mean service time) Lec24.37 Server spends a variable amount of time with customers Weighted mean m1 = (f1 x T1 + f2 x T fn x Tn)/F = 6 p(t)xt variance = (f1 x T1 2 + f2 x T fn x Tn 2 )/F m1 2 = 6 p(t)xt 2 -m1 2 Squared coefficient of variance: C = variance/m1 2 - Unitless measure (100 ms 2 vs. 0.1 s 2 ) Exponential distribution C = 1 : most short relative to average, few others long; 90% < 2.3 x average, 63% < average Hypoexponential distribution C < 1 : most close to average, C=0.5 => 90% < 2.0 x average, only 57% < average Hyperexponential distribution C > 1 : further from average C=2.0 => 90% < 2.8 x average, 69% < average 0 Avg. Lec24.38 A Little Queuing Theory: Variable Service Time System server Proc IOC Device Disk response times C 1.5 (majority seeks < average) Yet usually pick C = 1.0 for simplicity Avg. Memoryless, exponential dist Many complex systems well described by memoryless distribution! Another useful value is average time 0 Time must wait for server to complete current task: m1(z) Not just 1/2 x m1 because doesn t capture variance Can derive m1(z) = 1/2 x m1 x (1 + C) No variance Ÿ C= 0 => m1(z) = 1/2 x m1 Exponential Ÿ C= 1 => m1(z) = m1 A Little Queuing Theory: Average Wait Time Calculating average wait time in queue : If something at server, it takes to complete on average m1(z) Chance server is busy = u; average delay is u x m1(z) All customers in line must complete; each avg T ser = uxm1(z)+ L q x T s er = u x m1(z) + O x x T Little s Law ser = u x m1(z) + u x Defn of utilization (u) x (1 u) = m1(z) x u = m1(z) x u/(1-u) = T s er x {1/2 x (1+C)} x u/(1 u)) Notation: O average number of arriving customers/second T ser average time to service a customer u server utilization (0..1): u = O x T ser average time/customer in queue L q average length of queue:l q = O x m1(z) average residual wait time = T s er x {1/2 x (1+C)} Lec24.39 Lec24.40

11 Assumptions so far: System in equilibrium Time between two successive arrivals in line are random Server can start on next customer immediately after prior finishes No limit to the queue: works First-In-First-Out Afterward, all customers in line must complete; each avg T ser Described memoryless or Markovian request arrival (M for C=1 exponentially random), General service distribution (no restrictions), 1 server: M/G/1 queue When Service times have C = 1, M/M/1 queue = T ser x u / (1 u) T ser u A Little Queuing Theory: M/G/1 and M/M/1 average time to service a customer server utilization (0..1): u = O xt ser average time/customer in queue Processor sends 10 x 8KB disk I/Os per second, requests & service exponentially distrib., avg. disk service = 20 ms This number comes from disk equation: Service time = Ave seek + ave rot delay + transfer time + ctrl overhead On average, how utilized is the disk? What is the number of requests in the queue? What is the average time spent in the queue? What is the average response time for a disk request? Notation: O average number of arriving customers/second = 10 T ser average time to service a customer = 20 ms (0.02s) u server utilization (0..1): u = O xt ser = 10/s x.02s = 0.2 average time/customer in queue = T ser x u / (1 u) = 20 x 0.2/(1-0.2) = 20 x 0.25 = 5 ms (0.005s) T sys L q A Little Queuing Theory: An Example average time/customer in system: T sys = +T ser = 25 ms average length of queue:l q = O x = 10/s x.005s = 0.05 requests in queue L sys average # tasks in system: L sys = O x T sys = 10/s x.025s = 0.25 Lec24.41 Lec24.42 Memory System I/O Performance? Request Rate Pipelined with queue at controller? Time to transfer request ueue = ing Delay+service time Time to transfer data DRAM has DETERMINISTIC service time T ser = t RAC + (n-1) * t PC + t precharge = m1(z) x u/(1-u) = T ser x {1/2 x (1+C)} x u/(1 u)) with C=0 O Processor Memory Controller P DRAM Service Rate? Lec24.43 Summary es are an important technique for building largescale systems Their speed is critically dependent on factors such as length, number of devices, etc. Critically limited by capacitance Tricks: esoteric drive technology such as GTL Important terminology: Master: The device that can initiate new transactions Slaves: Devices that respond to the master Two types of bus timing: Synchronous: bus includes clock Asynchronous: no clock, just REQ/ACK strobing Direct Memory Access (DMA) allows fast, burst transfer into processor s memory: Processor s memory acts like a slave Probably requires some form of cache-coherence so that DMA ed memory can be invalidated from cache. Lec24.44

12 I/O Summary: I/O performance limited by weakest link in chain between OS and device ing theory is important 100% utilization means very large latency Remember, for M/M/1 queue (exponential source of requests/service) - queue size goes as u/(1-u) - latency goes as T ser u/(1-u) For M/G/1 queue (more general server, exponential sources) - latency goes as m1(z) x u/(1-u) = T ser x {1/2 x (1+C)} x u/(1-u) Three Components of Disk Access Time: Seek Time: advertised to be 8 to 12 ms. May be lower in real life. Rotational Latency: 4.1 ms at 7200 RPM and 8.3 ms at 3600 RPM Transfer Time: 2 to 12 MB per second I/O device notifying the operating system: Polling: it can waste a lot of processor time I/O interrupt: similar to exception except it is asynchronous Delegating I/O responsibility from the CPU: DMA, or even IOP Lec24.45