CS 152 Computer Architecture and Engineering. Lecture 11 - Virtual Memory and Caches

Transcription

1 CS 152 Computer Architecture and Engineering Lecture 11 - Virtual Memory and Caches Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley Last time in Lectures 10 Modern page-based virtual memory systems provide: Translation» to avoid memory fragmentation and provide each user with own virtual address space Protection» to protect users from each other, and to protect operating system from users Virtual memory» to allow main memory to act as a cache of a larger disk memory, equivalent Translation and protection information stored in page tables, held in main memory Translation and protection information cached in translation lookaside buffer () to provide single cycle translation+protection check in common case 3/6/2008 CS152-Spring!08 2

2 Today is a review Many of you had questions about virtual memory and interaction with caches Going to go back over core of last two lectures with some more interactive explanation 3/6/2008 CS152-Spring!08 3 Simple Base and Bound Translation Segment Length Bound Register! Bounds Violation? Load X Effective Address + Physical Address current segment Main Memory Program Address Space Base Register Base Physical Address Base and bounds registers are visible/accessible only when processor is running in the supervisor mode 3/6/2008 CS152-Spring!08 4

3 Separate Areas for Program and Load X Program Address Space Bound Register Effective Addr Register Base Register Program Bound Register Program Counter Program Base Register! +! + Bounds Violation? Bounds Violation? data segment program segment Main Memory What is an advantage of this separation? (Scheme used on all Cray vector supercomputers prior to X1, 2002) 3/6/2008 CS152-Spring!08 5 Memory Fragmentation user 1 user 2 user 3 OS Space 16K 24K 24K 32K Users 4 & 5 arrive user 1 user 2 user 4 user 3 OS Space 16K 24K 16K 8K 32K Users 2 & 5 leave user 1 user 4 user 3 OS Space 16K 24K 16K 8K 32K free 24K user 5 24K 24K As users come and go, the storage is fragmented. Therefore, at some stage programs have to be moved around to compact the storage. 3/6/2008 CS152-Spring!08 6

4 Paged Memory Systems Processor generated address can be interpreted as a pair <page number, offset> page number offset A page table contains the physical address of the base of each page Address Space of User of User Page tables make it possible to store the pages of a program non-contiguously. 3/6/2008 CS152-Spring!08 7 Private Address Space per User User 1 VA1 Physical Memory OS pages User 2 VA1 User 3 VA1 free Each user has a page table Page table contains an entry for each user page 3/6/2008 CS152-Spring!08 8

5 s in Physical Memory PT User 1 VA1 User 1 PT User 2 VA1 User 2 3/6/2008 CS152-Spring!08 9 Linear Entry (PTE) contains: A bit to indicate if a page exists (physical page number) for a memory-resident page DPN (disk page number) for a page on the disk Status bits for protection and usage OS sets the Base Register whenever active user process changes DPN DPN DPN DPN DPN Offset VPN Pages word PT Base Register VPN Offset Virtual address 3/6/2008 CS152-Spring!08 10

6 Size of Linear With 32-bit addresses, 4-KB pages & 4-byte PTEs: " 2 20 PTEs, i.e, 4 MB page table per user " 4 GB of swap needed to back up full virtual address space Larger pages? Internal fragmentation (Not all memory in a page is used) Larger page fault penalty (more time to read from disk) What about 64-bit virtual address space??? Even 1MB pages would require byte PTEs (35 TB!) What is the saving grace? sparsity of virtual address usage 3/6/2008 CS152-Spring!08 11 Hierarchical Virtual Address p1 p2 offset 10-bit L1 index Root of the Current 10-bit L2 index p1 p2 offset (Processor Register) Level 1 page in primary memory page in secondary memory Level 2 s PTE of a nonexistent page Pages 3/6/2008 CS152-Spring!08 12

7 Address Translation & Protection Kernel/User Mode Virtual Address Virtual Page No. (VPN) offset Read/Write Protection Check Address Translation Exception? Physical Address Physical Page No. () offset Every instruction and data access needs address translation and protection checks A good VM design needs to be fast (~ one cycle) and space efficient 3/6/2008 CS152-Spring!08 13 Translation Lookaside Buffers Address translation is very expensive! In a two-level page table, each reference becomes several memory accesses Solution: Cache translations in hit miss " Single Cycle Translation " Walk to refill virtual address VPN offset V R W D tag (VPN = virtual page number) ( = physical page number) hit? physical address offset 3/6/2008 CS152-Spring!08 14

8 Designs Typically entries, usually fully associative Each entry maps a large page, hence less spatial locality across pages! more likely that two entries conflict Sometimes larger s ( entries) are 4-8 way set-associative Random or FIFO replacement policy Reach: Size of largest virtual address space that can be simultaneously mapped by Example: 64 entries, 4KB pages, one page per entry Reach =? 64 entries * 4 KB = 256 KB (if contiguous) 3/6/2008 CS152-Spring!08 15 Address Translation in CPU Pipeline PC Inst Inst. Cache D Decode E M + Cache W miss? Page Fault? Protection violation? miss? Page Fault? Protection violation? Software handlers need restartable exception on fault Handling a miss needs a hardware or software mechanism to refill Need mechanisms to cope with the additional latency of a : slow down the clock pipeline the and cache access virtual address caches parallel /cache access 3/6/2008 CS152-Spring!08 16

9 Handling a Miss Software (MIPS, Alpha) miss causes an exception and the operating system walks the page tables and reloads. A privileged untranslated addressing mode used for walk Hardware (SPARC v8, x86, PowerPC) A memory management unit (MMU) walks the page tables and reloads the If a missing (data or PT) page is encountered during the reloading, MMU gives up and signals an exception for the original instruction 3/6/2008 CS152-Spring!08 17 Virtual Memory More than just translation and protection Use disk to extend apparent size of main memory Treat DRAM as cache of disk contents Only need to hold active working set of processes in DRAM, rest of memory image can be swapped to disk Inactive processes can be completely swapped to disk (except usually the root of the page table) Combination of hardware and software used to implement this feature (ATLAS was first implementation of this idea) 3/6/2008 CS152-Spring!08 18

10 Page Fault Handler When the referenced page is not in DRAM: The missing page is located (or created) It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from disk If no free pages are left, a page is swapped out Pseudo-LRU replacement policy Since it takes a long time to transfer a page (msecs), page faults are handled completely in software by the OS Untranslated addressing mode is essential to allow kernel to access page tables 3/6/2008 CS152-Spring!08 19 Caching vs. Demand Paging secondary memory CPU cache primary memory CPU primary memory Caching Demand paging cache entry page frame cache block (~32 bytes) page (~4K bytes) cache miss rate (1% to 20%) page miss rate (<0.001%) cache hit (~1 cycle) page hit (~100 cycles) cache miss (~100 cycles) page miss (~5M cycles) a miss is handled a miss is handled in hardware mostly in software 3/6/2008 CS152-Spring!08 20

11 Address Translation: putting it all together Restart instruction miss Virtual Address Lookup hit hardware hardware or software software Walk Page Fault (OS loads page) Update Protection Check the page is # memory $ memory denied permitted Protection Fault SEGFAULT Physical Address (to cache) 3/6/2008 CS152-Spring!08 21 Protection and Translation These have been combined in a modern virtual memory system, but are really separate functions Question, does translation itself provide enough protection? 3/6/2008 CS152-Spring!08 22

12 CS152 Administrivia Tuesday Mar 18, Quiz 3 Virtual memory hierarchy lectures Lab /6/2008 CS152-Spring!08 23 Address Translation in CPU Pipeline PC Inst Inst. Cache D Decode E M + Cache W miss? Page Fault? Protection violation? miss? Page Fault? Protection violation? Software handlers need restartable exception on fault Handling a miss needs a hardware or software mechanism to refill Need mechanisms to cope with the additional latency of a : slow down the clock pipeline the and cache access virtual address caches parallel /cache access 3/6/2008 CS152-Spring!08 24

13 Virtual Address Caches CPU VA Physical Cache PA Primary Memory Alternative: place the cache before the CPU VA Virtual Cache (StrongARM) one-step process in case of a hit (+) cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) aliasing problems due to the sharing of pages (-) maintaining cache coherence (-) (see later in course) PA Primary Memory 3/6/2008 CS152-Spring!08 25 Aliasing in Virtual-Address Caches Tag VA 1 Pages VA 1 1st Copy of at PA PA VA 2 2nd Copy of at PA VA 2 Two virtual pages share one physical page Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General Solution: Disallow aliases to coexist in cache Software (i.e., OS) solution for direct-mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in directmapped cache (early SPARCs) 3/6/2008 CS152-Spring!08 26

14 Concurrent Access to & Cache VA VPN L b Virtual Index PA k Page Offset Direct-map Cache 2 L blocks 2 b -byte block Tag hit? = Physical Tag Index L is available without consulting the " cache and accesses can begin simultaneously Tag comparison is made after both accesses are completed Cases: L + b = k L + b < k L + b > k 3/6/2008 CS152-Spring!08 27 Virtual-Index Physical-Tag Caches: Associative Organization VA VPN a L = k-b b 2 a Virtual Index k Direct-map 2 L blocks Direct-map 2 L blocks PA Page Offset Phy. Tag Tag = hit? 2 a = After the is known, 2 a physical tags are compared Is this scheme realistic? 3/6/2008 CS152-Spring!08 28

15 Concurrent Access to & Large L1 The problem with L1 > Page size VA VPN a Page Offset b Virtual Index L1 PA cache Direct-map VA 1 a VA 2 a PA Page Offset b Tag = hit? Can VA 1 and VA 2 both map to PA? 3/6/2008 CS152-Spring!08 29 A solution via Second Level Cache CPU RF L1 Instruction Cache L1 Cache Unified L2 Cache Memory Memory Memory Memory Usually a common L2 cache backs up both Instruction and L1 caches L2 is inclusive of both Instruction and caches 3/6/2008 CS152-Spring!08 30

16 Anti-Aliasing Using L2: MIPS R10000 VA Virtual Index VPN a Page Offset b L1 PA cache Direct-map into L2 tag VA 1 VA 2 a a PA Page Offset b Tag = hit? Suppose VA1 and VA2 both map to PA and VA1 is already in L1, L2 (VA1 % VA2) After VA2 is resolved to PA, a collision will be detected in L2. VA1 will be purged from L1 and L2, and VA2 will be loaded " no aliasing! PA a 1 Direct-Mapped L2 3/6/2008 CS152-Spring!08 31 Virtually-Addressed L1: Anti-Aliasing using L2 VA VPN Page Offset b Virtual Index & Tag VA 1 VA 2 PA Page Offset b L1 VA Cache Tag Physical Index & Tag Physically-addressed L2 can also be used to avoid aliases in virtuallyaddressed L1 PA VA 1 Virtual Tag L2 PA Cache L2 contains L1 3/6/2008 CS152-Spring!08 32

17 Variable-Sized Page Support Virtual Address p1 p2 offset 10-bit L1 index Root of the Current 10-bit L2 index p1 p2 offset (Processor Register) Level 1 page in primary memory large page in primary memory page in secondary memory PTE of a nonexistent page Level 2 s Pages 3/6/2008 CS152-Spring!08 33 Variable-Size Page Some systems support multiple page sizes. virtual address VPN offset V R WD Tag L hit? physical address offset 3/6/2008 CS152-Spring!08 34

18 Atlas Revisited One PAR for each physical page PAR s contain the VPN s of the pages resident in primary memory Advantage: The size is proportional to the size of the primary memory PAR s VPN What is the disadvantage? 3/6/2008 CS152-Spring!08 35 Hashed : Approximating Associative Addressing PID VPN d Virtual Address Offset hash + PA of PTE Base of Table Hashed is typically 2 to 3 times larger than the number of s to reduce collision probability It can also contain DPN s for some non-resident pages (not common) If a translation cannot be resolved in this table then the software consults a data structure that has an entry for every existing page VPN PID VPN PID DPN VPN PID Primary Memory 3/6/2008 CS152-Spring!08 36

19 Acknowledgements These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) MIT material derived from course UCB material derived from course CS252 3/6/2008 CS152-Spring!08 37