Why FPGAs will win the Accelerator Battle: Building Computers that Minimize Data Movement

Transcription

1 Why FPGAs will win the Accelerator Battle: Building Computers that Minimize Data Movement Allan Cantle President & Founder

2 Overview» Commercial Realities For HPC» A View From Berkeley» Two Fundamental Computing Architectures» Centric Data is brought to the» Data Centric s are built around the Data» Mixing /Data Centric Architectures» Data Centric Computing Architectures» Integrating & Data Centric Architectures» Summary 2

3 Commercial Realities for HPC Code base readily Available and portable between Architecture generations FPGAs 6 GPUs (as graphics accelerator) unviable Viable $M Market Size* ,000 10,000 GPGPUs Cell Clearspeed Code base NOT readily Available and NOT portable between Architecture generations = Single Source Vendor = Multi Source Vendors *Market size based on processor chip revenues only 3

4 SWEPT Efficiency Size, Weight, Energy, Performance, Time Reconfigurable s e.g. Clearspeed & GPU s Cell / Multi Core Commercial Realities - Technology Battleground FPGA Polymorphic 1993 to 1998 Growing FPGA Families Distributed Memory Multipliers/DSPs Gb Serial I/O A processor that is capable of morphing itself into the most efficient implementation for any given computing problem Bit Level Vector/Streaming Application Data Types 4

5 SWEPT Efficiency Size, Weight, Energy, Performance, Time Reconfigurable s e.g. Clearspeed & GPU s Cell/Multi-Core Technologies parallelising Hardware & Software Simultaneously Commercial Realities - Technology Battleground FPGA Technologies building software on an inherently parallel architecture FPGA Incumbent Technologies building parallel architectures that can still support inherently serial software 1993 to 1998 Growing FPGA Families Distributed Memory Multipliers/DSPs Gb Serial I/O Bit Level Vector/Streaming Application Data Types 5

6 Commercial Realities - The Changing Face of HPC» HPC s traditional markets» Scientific Modelling Largest in CFD / FEA» Typically Symmetrical problems» Non Real Time ( Non Deterministic)» Growing HPC Markets» Triple Play Voice, Video & Data» Internet» Centralisation of Application Servers Back to the Mainframe» Virtualisation» Deterministic & Real Time e.g. VOIP» Some of the new HPC challenges have already been solved in HPEC world 6

7 A View from Berkeley 7

8 Two Fundamental Computing Models» Centric HPC World» Von Neumann & Harvard Architectures» Invented when the processor was the bottleneck» Hub and Spoke approach» Data Centric HPEC World» System Level Data Centric» Chip Level Data Centric» Distributed processing approach» Minimise Data Movement 8

9 Today s Centric Architecture (Intel) 8.5 GB/s FSB 8.5 GB/s FSB SDRAM Memory DIMMs MCH / Northbridge Chipset Southbridge Chipset 21 GB/s Leads to High Latency & hence the need for fully decoupled accelerators & I/O OS Dependent & Non Deterministic Storage I/O USB I/O 1394 I/O Graphics I/O Wireless I/O Network I/O Accelerators 9

10 SWEPT Efficiency Size, Weight, Energy, Performance, Time Mixing /Data Centric Architectures = Centric = Data Centric = 33% = 66% Are Data Centric Architectures the future of Computing?! Parallelised Bit level processors Parallelised Vector / Streaming processors Parellised processors Bit level processor Vector / Streaming processors processor Bit Level Vector/Streaming Application Data Types 10

11 SWEPT Efficiency Size, Weight, Energy, Performance, Time Mixing /Data Centric Architectures» Cell, ClearSpeed, others have a 1-2 year code base» Complex Heterogeneous Architectures will provide significant challenges on code portability» FPGA code very portable» X86 Architectures where we are inherently porting from Parallelised Bit level processors Bit level processor FPGA VHDL Code Base 10+ Years Parallelised Vector / Streaming processors Vector / Streaming processors Parellised processors X86 Code Base 25+ Years Bit Level Vector/Streaming Application Data Types 11

12 The FPGA can effectively concatenate functions» Minimises Memory Thrashing» Critical Bottleneck in today s Architectures» Requires Data to be ordered» The Micropocessor almost becomes the Coprocessor» When viewed from a Data Centric Perspective FPGA Internet Infrastructure Ethernet protocol Decrypt Data Un Compress XML Decode Function Hot Spot Ethernet protocol Encrypt Data Compress Data XML Encode uprocesso r Main Algorithmic Function FSB System Memory FSB/PCI 12

13 A Generic Data Centric Computing Architecture System Partitioned to minimise comms bandwidth X86 X86 FPGA Data Centric FPGA Data Centric FPGA Data Centric FPGA Data Centric Internet X86 X86 Main & Co-?! or Peer s? Multimedia 13

14 I/O s I/O s I/O I/O We are entering a Gigabit serial comms world!» All I/O will be Gigabit serial» Phy layer will be compatible across memory, system interconnect and I/O» Software Configurable» Possibility to choose your architecture that best suits your application. Memory Memory Memory Storage Storage Storage Workstation Database Search Network processing = 4 x 5Gb bidirectional serial llinks 14

15 X86 Architecture Migration 8.5 GB/s FSB 8.5 GB/s FSB SDRAM Memory DIMMs MCH / Northbridge Chipset Southbridge Chipset 21 GB/s Interfaces already Gbit Serial Storage I/O USB I/O 1394 I/O Graphics I/O Wireless I/O Network I/O Accelerators Geneseo extensions resolving Latency, Determinism, small & large packet Bandwidth issues (2010) 15

16 Intel & Nallatech Bringing processor & Data Centric Architectures together 8.5 GB/s FSB 8.5 GB/s FSB SDRAM Memory DIMMs MCH / Northbridge Chipset 21 GB/s Southbridge Chipset 16

17 Intel & Nallatech Bringing processor & Data Centric Architectures together Up to 5+5 GB/s Virtex 5 Quad FPGA Core LXT110 - LXT GB/s FSB 8.5 GB/s FSB SDRAM Memory DIMMs MCH / Northbridge Chipset 21 GB/s Nallatech s Data Centric FPGA Computing Platform DIME-II Southbridge Chipset Intel s Centric MP Platform 17

18 Summary» Only Two Fundamental Computing Approaches» Centric 6 Microprocessor» Data Centric FPGAs» HPC Can Learn from HPEC» FPGAs are by far the best all round accelerator» Commericial viability» Multi Vendor» application Flexibility» extremely complementary Microprocessors» Nallatech & Intel working together to deliver balanced FPGA/6 architectures in early Q1/

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