A 101 Guide to Heterogeneous, Accelerated, Data Centric Computing Architectures

Transcription

1 A 101 Guide to Heterogeneous, Accelerated, Centric Computing Architectures Allan Cantle President & Founder, Nallatech Join the Conversation #OpenPOWERSummit 2016 OpenPOWER Foundation

2 Buzzword & Acronym Overload OpenPOWER Foundation

3 Centric Evolution Von Neumann Bottleneck coined by John Backus circa Year Laser Focus Intel 386 adds external cache memory To circumvent this bottleneck circa 1985 Surely there must be a less primitive way of making big changes in the store than by pushing vast numbers of words back and forth through the von Neumann bottleneck. Not only is this tube a literal bottleneck for the data traffic of a problem, but, more importantly, it is an intellectual bottleneck that has kept us tied to word-at-a-time thinking instead of encouraging us to think in terms of the larger conceptual units of the task at hand. Thus programming is basically planning and detailing the enormous traffic of words through the von Neumann bottleneck, and much of that traffic concerns not significant data itself, but where to find it. John Backus 1977 ACM Turing Award 3

4 Centric Evolution 30+ Year Laser Focus Increasing Relative Distance +++ OS & software virtualization overhead +++ After 30 Years the Von Neuman of fighting Bottleneck 4

5 PCIe A millisecond in the life of your data MB L4 Cache MB L4 Cache CPU is efficient when working out of L1 Cache but distant from primary data store 4GByte 2.5D L3 Cache L2 Cache L1 Cache 4GByte 2.5D NIC To wider Cluster & 100 s TBytes to Petabytes NAS Via TOR Switch CPU CPU TByte PCIe Flash Storage 4GByte 2.5D 4GByte 2.5D RAID SATA/SAS MB L4 Cache MB L4 Cache Disk Disk 10 s TBytes Path of your data in today s CPUs Multiple Copies for Performance & Coherency 5

6 Centric Legacy we live with today Increasing Distance CPU + L1 Cache = Low Power +++ OS & software virtualization overhead +++ Memory copying & data movement = wasted power NV = Zero Power 6

7 Inexorable shift to a centric World Increasing Distance Circumvention Strategies DPDK CPU + L1 Cache = Low Power REDUCE +++ OS & software virtualization overhead +++ NV = Zero Power MAP Google Led the Centric Focused Evolution Essentially, today we re living in a Centric Computing world that is being adapted for data centric applications, without completely breaking the traditional programming model 7

8 What about Heterogeneous Accelerators? Accelerators offer Application Specific architectural tweaks that Increase Ops/Flops and/or Keep data local to the compute for longer Typical & Optimized <-> Accelerator Flows Increasing Distance +++ OS & software virtualization overhead +++ FPGA Peer to Peer L1 Cache L1 Cache s Traditional FLOP Amplification FPGAs Centric Deep Pipelines 8

9 What about Heterogeneous Accelerators? Accelerators offer Application Specific architectural tweaks that Increase Ops/Flops and/or Keep data local to the compute for longer Typical & Optimized <-> Accelerator Flows s & Accelerators are blurring/becoming Peer s FPGA Increasing Distance +++ OS & software virtualization overhead +++ FPGA L1 Cache Streaming L1 Cache 2016 OpenPOWER Foundation 9

10 What about Heterogeneous Accelerators? Accelerators offer Application Specific architectural tweaks that Increase Ops/Flops and/or Keep data local to the compute for longer Typical & Optimized <-> Accelerator Flows s & Accelerators are blurring/becoming Peer s We re on a journey of invention toward the Polymorphic FPGA Polymorphic name given by DARPA Circa 1998 Increasing Distance +++ OS & software virtualization overhead +++ FPGA L1 Cache Streaming L1 Cache 10

11 OpenPOWER Taking Centric to the next level Opened POWER Architecture at chip level Enabling collaborative Polymorphic processor Innovation Opened POWER Architecture at the System Level Enabling Centric System Architecture innovation Changing the game on how s, Accelerators, Memory, Storage & Networking interact Allowing Centric Computing experts like Nallatech to have a voice and be heard 11

12 Nallatech OpenPOWER FPGA Accelerators Network Acceleration Storage Acceleration Compute Acceleration Single FPGA + 10/40 GbE Applications Compression Encryption FSI IDS Single FPGA + 2TB Flash Applications In-Memory base Inline compression CAPI SNAP In-storage Algorithm acceleration Dual FPGA + 290GB/s Memory BW Applications O&G Migration Machine Learning H265 Encoding Bioinformatics 12

13 Centric Exascale Architecture Prediction DOE Target <20MW Exascale Computer Commercially Achievable in less than 5 years SSD Polymorphic DRAM Polymorphic Polymorphic In Storage Compute In Memory Compute Raw Compute 13