A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing
|
|
- Luke Floyd
- 5 years ago
- Views:
Transcription
1 A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing Second International Workshop on HyperTransport Research and Application (WHTRA 2011) University of Heidelberg Computer Architecture Group, Sven Kapferer, Alexander Giese, Holger Fröning, Ulrich Brüning
2 Outline Motivation HyperTransport Board Architecture HT3 Implementation Measurements Conclusion & Outlook 2
3 Accelerated Computing Most accelerated computing implementations focus on GPUs usage GPUs are mass market product providing a huge amount of parallel processing units FPGAs lead to higher costs Optimized and easy programming support FPGA usage is more difficult 3
4 FPGA Advantages FPGAs evolving in a remarkable way providing different advantages Flexibility and complete reconfigurability Enable usage of large amounts of memory Fine grain access to and from a host system Higher efficiency measured in GFLOPs/Watt 4
5 HyperTransport HyperTransport is the easiest and best way to connect a device to a processor The only public specification Free for academic use Low latency communication without bridges or protocol conversion HT link frequencies HT200 (2bit/200MHz) up to HT 3200 (32bit/3.2GHz) Theoretical maximum unidirectional bandwidth of 12.8 GB/s HT3 begins at HT1200 5
6 HT3 Block Diagram HT3 introduces fault detection and recovery mechanisms for higher reliability during high speed operation Periodic CRC window => per packet CRC Link training Link deskewing necessary Retry protocol Stomping 6
7 Altera Ulysses Rev 2 HTX Connector with 16bit transceiver based bidirectional interface Altera Stratix IV GX 230 (F1517 footprint) 256 MB DDR memory 2 CX4 connectors routed to FPGA transceivers Marvel 88E1111 Ethernet solution USB2 connectivity via Cypress CY7C68013A High-Speed USB Additional external connectivity with Stratix LVDS interfaces 7
8 Ulysses Extension Options Extension possibilities for usage as Prototype Development Platform SEAF connector (Samtec) 500 pins Single-ended signaling up to 9.5 GHz (114) Differential pair signaling up to 10.5 GHz (55) Three QTH connectors (Samtec) 3x120 pins 9GHz single-ended capability 8 GHz differential pair capability Up to 108 differential pairs plus sideband signals 8
9 HT3 Implementation - Requirements Porting HT3 Core onto the Altera Ulysses Board has two major requirements HW has to be capable of high speed signals Special design methodology H-Spice simulations Physical Interface Development 9
10 Simulation Setup HT tracks between Opteron processor and Stratix IV HSpice model of FPGA high speed serial transceiver (Altera) Opteron processor IBIS models (AMD) HTX connector Spice model (Samtec) Cadence tool chain extracts design specific data 10
11 HT3.1 channel data eye specification Parameter Min Max Unit Description TCH-EYE 0.55 UI Eye width Gbps TCH-EYE UI Eye width Gbps TCH-CLK-TJ 0.1 UI Jitter additive to CLK VCH-EYE-DC 140 mv Eye height for Gbps VCH-EYE-DC mv Eye height for Gbps Unit Interval (UI) : 2.4 Gbps is 416 ps 6.4 Gbps is156 ps 11
12 HTX Track Simulated at HT1200 Eye width: 0.55 UI at 2.4Gbps = 229 ps 375 ps > 229 ps Eye height: Range 531 mv to 998mV above 170mV 12
13 Critical HTX Track at HT3200 Eye width: 0.65 UI at 6.4Gbps = 101 ps 107 ps > 101 ps Eye height: 224mV above 140mV 13
14 PHY challenges PHY must support both HT1 and HT3 Two inherently different operation modes: HT1 is source synchronous, a link clock is transmitted HT3 uses CDR to recover the embedded clock Both low speed (200 MHz) and high speed (3200 MHz) links must be supported LVDS too slow for HT3 Stratix IV transceivers must be used PHY must support frequency switching 14
15 Stratix IV Transceivers 15
16 HT1 operation HT200 data rate is below the minimum supported rate of Stratix IV transceivers 5 time oversampling is used No scrambling or 8b10b encoding, therefore no CDR Lock to reference clock to create sampling points TX link clock treated as data channel Simply created by applying a clock pattern Transceivers in PMA mode to provide deterministic latency 90 degree clock shift by padding clock data 16
17 HT3 operation Reconfiguration of transceiver logic for switch Bypass oversampling Switch to CDR Enable elastic buffers to compensate for phase differences on the lanes Inter-lane skew will be handled in HT3 core logic No support for error detection in PHY Signal integrity issues detected by HT3 core Link reliability features are defined by HT3 protocol 17
18 Measurements Round trip single PIO access to device is 655 ns Slower latency than old HT1 System More pipeline stages for decoding Serializer must be used within FPGA Several clock domain crossings Less than half of the available bandwidth Caused by credit starvation Credit Redistribution => 2GB/s DMA write and 1.6 GB/s DMA read => This improvement shows that full HT utilization can only be achieved by using a device with higher performance than an FPGA 18
19 Stratix IV GX 230 Resources Used Total Percent Combinational ALUTs 42, , % Memory ALUTs 49 91,200 < 1 % Dedicated logic registers 40, , % Logic utilization 34 % Total block memory bits 739,154 14,625,792 5 % Total PLLs % 19
20 Conclusion & Outlook HT1200 and HT1600 (8 bit) implementations are stable Higher link speeds hard to achieve because of HW complexity HT3 platform for rapid prototyping and high performance reconfigurable computing was a successful development Ideal environment for developments and research in the areas of coprocessors or FPGA accelerators Extension connectors enable realization of adapter cards like a network search engine 20
21 Thank you for your attention! Questions? 21
22 Back-up Slides 22
23 NSE Design 23
24 HT3 Xilinx Board XC5VLX330T & 2x FX70T 16bit wide HT3 link 2 CX-4 connectors (IB, 10GE) SO-DIMM connector HT3 PHY design Based on GTPs (up to 4GBit/s) 24
Building blocks for custom HyperTransport solutions
Building blocks for custom HyperTransport solutions Holger Fröning 2 nd Symposium of the HyperTransport Center of Excellence Feb. 11-12 th 2009, Mannheim, Germany Motivation Back in 2005: Quite some experience
More informationOptimal Management of System Clock Networks
Optimal Management of System Networks 2002 Introduction System Management Is More Challenging No Longer One Synchronous per System or Card Must Design Source-Synchronous or CDR Interfaces with Multiple
More informationAn FPGA based Verification Platform for HyperTransport 3.x
An FPGA based Verification Platform for HyperTransport 3.x Heiner Litz Holger Froening Maximilian Thuermer Ulrich Bruening University of Heidelberg Computer Architecture Group Germany {heiner.litz, holger.froening,
More informationCBMnet as FEE ASIC Backend
CBMnet as FEE ASIC Backend 17th CBM Collaboration Meeting P2 FEE/DAQ/FLES University of Heidelberg Computer Architecture Group, Ulrich Brüning 05.04.2011 Outline Motivation Front-end ASIC CBMnet implementation
More informationFlexible Architecture Research Machine (FARM)
Flexible Architecture Research Machine (FARM) RAMP Retreat June 25, 2009 Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan Bronson Christos Kozyrakis, Kunle Olukotun Motivation Why CPUs + FPGAs make sense
More informationSpaceWire-RT. SpaceWire-RT Status SpaceWire-RT IP Core ASIC Feasibility SpaceWire-RT Copper Line Transceivers
SpaceWire-RT SpaceWire-RT Status SpaceWire-RT IP Core ASIC Feasibility SpaceWire-RT Copper Line Transceivers 1 Overview of SpaceWire-RT Project Aims The SpaceWire-RT research programme aims to: Conceive
More informationSpaceWire-RT Update. EU FP7 Project Russian and European Partners. SUAI, SubMicron, ELVEES University of Dundee, Astrium GmbH
SpaceWire-RT Update EU FP7 Project Russian and European Partners SUAI, SubMicron, ELVEES University of Dundee, Astrium GmbH 1 Contents SpaceWire-RT project SpaceWire-RT protocols Oversampled SpaceFibre
More informationArria V GX Transceiver Starter Kit
Page 1 of 4 Arria V GX Transceiver Starter Kit from Altera Ordering Information Transceiver Starter Kit Contents Starter Board Photo Related Links The Altera Arria V GX Transceiver Starter Kit provides
More informationAN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices
AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 AN-610-1.0 This application note describes how to implement deterministic latency for Common Public Radio
More informationDesign Guidelines for Intel FPGA DisplayPort Interface
2018-01-22 Design Guidelines for Intel FPGA DisplayPort Interface AN-745 Subscribe The design guidelines help you implement the Intel FPGA DisplayPort IP core using Intel FPGA devices. These guidelines
More informationArria V GX Video Development System
Arria V GX Video Development System Like Sign Up to see what your friends like. The Arria V GX FPGA Video Development System is an ideal video processing platform for high-performance, cost-effective video
More informationECE 485/585 Microprocessor System Design
Microprocessor System Design Lecture 16: PCI Bus Serial Buses Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture based on materials
More informationAltera Product Overview. Altera Product Overview
Altera Product Overview Tim Colleran Vice President, Product Marketing Altera Product Overview High Density + High Bandwidth I/O Programmable ASSP with CDR High-Speed Product Term Embedded Processor High
More information40-Gbps and 100-Gbps Ethernet in Altera Devices
40-Gbps and 100-Gbps Ethernet in Altera Devices Transceiver Portfolio Workshops 2009 Agenda 40/100 GbE standards 40/100 GbE IP in Altera devices Stratix IV GT FPGA features and advantages Altera standards
More informationImplementing 9.8G CPRI in Arria V GT and ST FPGAs
03..06 AN 686 Subscribe This application note describes the implementation of 9.8304 Gbps Common Public Radio Interface (CPRI) using the Arria V GT and Arria V ST FPGA transceivers. The hard physical coding
More informationSGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices
SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices May 2008, version 1.0 Application Note 518 Introduction Stratix III device family are one of the most architecturally advanced,
More informationA (Very Hand-Wavy) Introduction to. PCI-Express. Jonathan Heathcote
A (Very Hand-Wavy) Introduction to PCI-Express Jonathan Heathcote Motivation Six Week Project Before PhD Starts: SpiNNaker Ethernet I/O is Sloooooow How Do You Get Things In/Out of SpiNNaker, Fast? Build
More informationSection I. Stratix II GX Device Data Sheet
Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture,
More informationQPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004
Application Note QPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004 Copyrights and Trademarks Copyright 2004 Samtec,
More informationS2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
More informationInterfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices
Interfacing RLDRAM II with Stratix II, Stratix,& Stratix GX Devices November 2005, ver. 3.1 Application Note 325 Introduction Reduced latency DRAM II (RLDRAM II) is a DRAM-based point-to-point memory device
More informationOptimizing latency in Xilinx FPGA Implementations of the GBT. Jean-Pierre CACHEMICHE
Optimizing latency in Xilinx FPGA Implementations of the GBT Steffen MUSCHTER Christian BOHM Sophie BARON Jean-Pierre CACHEMICHE Csaba SOOS (Stockholm University) (Stockholm University) (CERN) (CPPM) (CERN)
More informationMulti-Gigabit Transceivers Getting Started with Xilinx s Rocket I/Os
Multi-Gigabit Transceivers Getting Started with Xilinx s Rocket I/Os Craig Ulmer cdulmer@sandia.gov July 26, 2007 Craig Ulmer SNL/CA Sandia is a multiprogram laboratory operated by Sandia Corporation,
More informationInterfacing FPGAs with High Speed Memory Devices
Interfacing FPGAs with High Speed Memory Devices 2002 Agenda Memory Requirements Memory System Bandwidth Do I Need External Memory? Altera External Memory Interface Support Memory Interface Challenges
More informationASNT_MUX64 64Gbps 2:1 Multiplexer
ASNT_MUX64 64Gbps 2:1 Multiplexer 105ps data phase shift capability for both data inputs VCO s from 20GHz to 32.1GHz User selectable clock divide by 2 to 512 sync output for scope triggering 17ps Rise/Fall
More informationMaintaining Cache Coherency with AMD Opteron Processors using FPGA s. Parag Beeraka February 11, 2009
Maintaining Cache Coherency with AMD Opteron Processors using FPGA s Parag Beeraka February 11, 2009 Outline Introduction FPGA Internals Platforms Results Future Enhancements Conclusion 2 Maintaining Cache
More informationThe Benefits of FPGA-Enabled Instruments in RF and Communications Test. Johan Olsson National Instruments Sweden AB
The Benefits of FPGA-Enabled Instruments in RF and Communications Test Johan Olsson National Instruments Sweden AB 1 Agenda Introduction to FPGAs in test New FPGA-enabled test applications FPGA for test
More informationUnderstanding JESD204B High-speed inter-device data transfers for SDR
Understanding JESD204B High-speed inter-device data transfers for SDR Lars-Peter Clausen Introduction JESD204 Standard Designed as high-speed serial data link between converter (ADC, DAC) and logic device
More information10 Gigabit XGXS/XAUI PCS Core. 1 Introduction. Product Brief Version April 2005
1 Introduction Initially, network managers use 10 Gigabit Ethernet to provide high-speed, local backbone interconnection between large-capacity switches. 10 Gigabit Ethernet enables Internet Service Providers
More informationWhite Paper Low-Cost FPGA Solution for PCI Express Implementation
White Paper Introduction PCI Express is rapidly establishing itself as the successor to PCI, providing higher performance, increased flexibility, and scalability for next-generation systems, as well as
More informationInterlaken IP datasheet
Key words:interlaken, MAC, PCS, SERDES Abstract:Interlaken MAC/PCS implementation per Interlaken protocol v1.2 All rights reserved Table of Contents 1. Introduction...4 2. Specification...4 3. Architecture...4
More informationPeter Alfke, Xilinx, Inc. Hot Chips 20, August Virtex-5 FXT A new FPGA Platform, plus a Look into the Future
Peter Alfke, Xilinx, Inc. Hot Chips 20, August 2008 Virtex-5 FXT A new FPGA Platform, plus a Look into the Future FPGA Evolution Moore s Law: Double density every other year New process technology, smaller
More information8. Migrating Stratix II Device Resources to HardCopy II Devices
8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy II devices and Stratix II devices are both manufactured on a 1.2-V, 90-nm process technology and
More informationLeveraging HyperTransport for a custom high-performance cluster network
Leveraging HyperTransport for a custom high-performance cluster network Mondrian Nüssle HTCE Symposium 2009 11.02.2009 Outline Background & Motivation Architecture Hardware Implementation Host Interface
More informationSV3C DPRX MIPI D-PHY Analyzer. Data Sheet
SV3C DPRX MIPI D-PHY Analyzer Data Sheet Table of Contents Table of Contents Table of Contents... 1 List of Figures... 2 List of Tables... 2 Introduction... 3 Overview... 3 Key Benefits... 3 Applications...
More informationCS/ECE 217. GPU Architecture and Parallel Programming. Lecture 16: GPU within a computing system
CS/ECE 217 GPU Architecture and Parallel Programming Lecture 16: GPU within a computing system Objective To understand the major factors that dictate performance when using GPU as an compute co-processor
More information2. Arria GX Architecture
2. Arria GX Architecture AGX51002-2.0 Transceivers Arria GX devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix II GX device family. Arria GX transceivers
More informationDecember 2002, ver. 1.1 Application Note For more information on the CDR mode of the HSDI block, refer to AN 130: CDR in Mercury Devices.
Using HSDI in Source- Synchronous Mode in Mercury Devices December 2002, ver. 1.1 Application Note 159 Introduction High-speed serial data transmission has gained increasing popularity in the data communications
More informationField Programmable Gate Array (FPGA) Devices
Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs
More informationExtending HyperTransport Technology to 8.0 Gb/s in 32-nm SOI-CMOS Processors
Extending HyperTransport Technology to 8.0 Gb/s in 32-nm SOI-CMOS Processors Bruce Doyle, Alvin Loke, Sanjeev Maheshwari, Charles Wang, Dennis Fischette, Jeffrey Cooper, Sanjeev Aggarwal, Tin Tin Wee,
More informationni.com High-Speed Digital I/O
High-Speed Digital I/O Interfacing with Digital I/O Design Verification & Validation Production Characterization Protocol communication Parametric testing DUT control Limit testing Stress testing BERT
More informationMIPI D-PHY Bandwidth Matrix Table User Guide
FPGA-UG-02041 Version 1.1 May 2018 Contents Acronyms in This Document... 4 1. Introduction... 5 2. Video Format... 6 2.1. Video Resolution and Pixel Clock... 7 2.2. Color Depth... 8 3. MIPI CSI-2/DSI Interfaces...
More informationMIPI D-PHY Bandwidth Matrix and Implementation Technical Note
MIPI D-PHY Bandwidth Matrix and Implementation FPGA-TN-02090 Version 1.1 January 2019 Contents Acronyms in This Document... 4 1. Introduction... 5 2. Video Format... 6 2.1. Video Resolution and Pixel Clock...
More information6. I/O Features in Stratix IV Devices
6. I/O Features in Stratix IV Devices September 2012 SIV51006-3.4 SIV51006-3.4 This chapter describes how Stratix IV devices provide I/O capabilities that allow you to work in compliance with current and
More informationJESD204B Xilinx/IDT DAC1658D-53D interoperability Report
[Interoperability Report] Rev 0.4 Page 1 of 14 JESD204B Xilinx/IDT DAC1658D-53D interoperability Report [Interoperability Report] Rev 0.4 Page 2 of 14 CONTENTS INTRODUCTION... 3 SCOPE... 3 HARDWARE...
More informationLow Latency 40G Ethernet Example Design User Guide
Low Latency 40G Ethernet Example Design User Guide Subscribe UG-20025 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Quick Start Guide...1-1 Directory Structure... 1-2 Design Components...
More informationHigh-speed I/O test: The ATE paradigm must change
High-speed I/O test: The ATE paradigm must change 2005 VLSI Test Symposium Session 4C Burnie West May 2005 Outline The brave new world Test methodology PHY testing Functional testing ATE specifications
More informationSerialLite II IP Core User Guide
SerialLite II IP Core User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.1 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents SerialLite II IP Core Overview...1-1 General
More informationRaj Kumar Nagpal, R&D Manager Synopsys. Enabling Higher Data Rates and Variety of Channels with MIPI D-PHY
Raj Kumar Nagpal, R&D Manager Enabling Higher Data Rates and Variety of Channels with MIPI D-PHY Agenda Design motivation MIPI D-PHY evolution Summary of MIPI D-PHY specification MIPI channel evolution
More informationLVDS applications, testing, and performance evaluation expand.
Stephen Kempainen, National Semiconductor Low Voltage Differential Signaling (LVDS), Part 2 LVDS applications, testing, and performance evaluation expand. Buses and Backplanes D Multi-drop D LVDS is a
More informationDesigning with the Xilinx 7 Series PCIe Embedded Block. Tweet this event: #avtxfest
Designing with the Xilinx 7 Series PCIe Embedded Block Follow @avnetxfest Tweet this event: #avtxfest www.facebook.com/xfest2012 Why Would This Presentation Matter to You? 2 If you are designing a PCIe
More informationSerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices
IP Core Design Example User Guide for Intel Arria 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start
More information5 GT/s and 8 GT/s PCIe Compared
5 GT/s and 8 GT/s PCIe Compared Bent Hessen-Schmidt SyntheSys Research, Inc. Copyright 2008, PCI-SIG, All Rights Reserved 1 Disclaimer The material included in this presentation reflects current thinking
More informationLow Latency 100G Ethernet Design Example User Guide
Low Latency 100G Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 16.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start Guide...
More informationRiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications. Revision Date: March 18, 2005
RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications Revision Date: March 18, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed in conjunction with
More informationResource Efficiency of Scalable Processor Architectures for SDR-based Applications
Resource Efficiency of Scalable Processor Architectures for SDR-based Applications Thorsten Jungeblut 1, Johannes Ax 2, Gregor Sievers 2, Boris Hübener 2, Mario Porrmann 2, Ulrich Rückert 1 1 Cognitive
More informationApplication of Zero Delay Buffers in Switched Ethernet
3 Application Note15 Application of Zero Delay Buffers in Switched Ethernet By Cameron Katrai Abstract With the best and tightest characteristics of any PLL driver, Pericom s collection of Zero Delay Clock
More informationSV3C DPRX MIPI D-PHY Analyzer. Data Sheet
SV3C DPRX MIPI D-PHY Analyzer Data Sheet Table of Contents Table of Contents Table of Contents... 1 List of Figures... 2 List of Tables... 3 Introduction... 4 Overview... 4 Key Benefits... 4 Applications...
More informationQ Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height
Application Note Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height Copyrights and Trademarks Copyright 2004 Samtec, Inc. Developed in conjunction with Teraspeed Consulting
More informationPactron FPGA Accelerated Computing Solutions
Pactron FPGA Accelerated Computing Solutions Intel Xeon + Altera FPGA 2015 Pactron HJPC Corporation 1 Motivation for Accelerators Enhanced Performance: Accelerators compliment CPU cores to meet market
More information7. External Memory Interfaces in Stratix IV Devices
February 2011 SIV51007-3.2 7. External Memory Interfaces in Stratix IV evices SIV51007-3.2 This chapter describes external memory interfaces available with the Stratix IV device family and that family
More informationI/O Channels. RAM size. Chipsets. Cluster Computing Paul A. Farrell 9/8/2011. Memory (RAM) Dept of Computer Science Kent State University 1
Memory (RAM) Standard Industry Memory Module (SIMM) RDRAM and SDRAM Access to RAM is extremely slow compared to the speed of the processor Memory busses (front side busses FSB) run at 100MHz to 800MHz
More informationLow Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationAN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA Triple-Speed Ethernet and On-Board
More informationRHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing
RHiNET-3/SW: an 0-Gbit/s high-speed network switch for distributed parallel computing S. Nishimura 1, T. Kudoh 2, H. Nishi 2, J. Yamamoto 2, R. Ueno 3, K. Harasawa 4, S. Fukuda 4, Y. Shikichi 4, S. Akutsu
More informationIndustry Collaboration and Innovation
Industry Collaboration and Innovation Open Coherent Accelerator Processor Interface OpenCAPI TM - A New Standard for High Performance Memory, Acceleration and Networks Jeff Stuecheli April 10, 2017 What
More informationPBL Model Update. Trey Malpass Ye Min Ding Chiwu Zengli. IEEE Higher Speed Study Group Nov HUAWEI TECHNOLOGIES Co., Ltd.
Model Update Trey Malpass Ye Min Ding Chiwu Zengli IEEE 802.3 Higher Speed Study Group 12-15 Nov 2007 Contents Page 2 Model Architecture Model Detailed Information Interface Functions Applications 10 x
More informationIntel Thunderbolt. James Coddington Ed Mackowiak
Intel Thunderbolt James Coddington Ed Mackowiak Thunderbolt Basics PCI Express and DisplayPort through a single connection made available to external devices. Thunderbolt Basics Developed by Intel and
More information802.3bj FEC Overview and Status. 1x400G vs 4x100G FEC Implications DRAFT. IEEE P802.3bs 400 Gb/s Ethernet Task Force. Bill Wilkie Xilinx
802.3bj FEC Overview and Status 1x400G vs 4x100G FEC Implications DRAFT IEEE P802.3bs 400 Gb/s Ethernet Task Force July 2015 Hawaii Bill Wilkie Xilinx Introduction This presentation takes a look at the
More informationThe HTX-Board: A Rapid Prototyping Station
The HTX-Board: A Rapid Prototyping Station Holger Fröning Mondrian Nüssle David Slogsnat Heiner Litz Ulrich Brüning University of Mannheim Computer Architecture Group B6,26 68159 Mannheim, Germany {froening,nuessle,slogsnat,heiner.litz,bruening}@uni-mannheim.de
More information2. Link and Memory Architectures and Technologies
2. Link and Memory Architectures and Technologies 2.1 Links, Thruput/Buffering, Multi-Access Ovrhds 2.2 Memories: On-chip / Off-chip SRAM, DRAM 2.A Appendix: Elastic Buffers for Cross-Clock Commun. Manolis
More informationSMT9091 SMT148-FX-SMT351T/SMT391
Unit / Module Description: Unit / Module Number: Document Issue Number: Issue Date: Original Author: This Document provides an overview of the developed system key features. SMT148-FX-SMT351T/SMT391 E.Puillet
More informationAn Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation
An Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation C. Chastang, A. Amédéo V. Poisson, P. Grison, F. Demuynck C. Gautier, F. Costa Thales Communications &
More informationPCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers
PCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers - Transmitter Testing - Receiver Testing - Link Equalization Testing David Li Product Marketing Manager High Speed
More informationBoard Design Guidelines for PCI Express Architecture
Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs The facts, techniques and applications presented by the following
More informationXMC-FPGA05F. Programmable Xilinx Virtex -5 FPGA PMC/XMC with Quad Fiber-optics. Data Sheet
Data Sheet XMC-FPGA05F Programmable Xilinx Virtex -5 FPGA PMC/XMC with Quad s Applications Remote Sensor Interface Data Recorders Distributed Processing Interconnect Protocol Converter Data Encryption
More information7. External Memory Interfaces in Arria II Devices
ecember 2010 AIIGX51007-4.0 7. External Memory Interfaces in Arria II evices AIIGX51007-4.0 This chapter describes the hardware features in Arria II devices that facilitate high-speed memory interfacing
More informationINT G bit TCP Offload Engine SOC
INT 10011 10 G bit TCP Offload Engine SOC Product brief, features and benefits summary: Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured ASIC flow.
More informationIntegrating FPGAs in High Performance Computing A System, Architecture, and Implementation Perspective
Integrating FPGAs in High Performance Computing A System, Architecture, and Implementation Perspective Nathan Woods XtremeData FPGA 2007 Outline Background Problem Statement Possible Solutions Description
More informationIntroduction Electrical Considerations Data Transfer Synchronization Bus Arbitration VME Bus Local Buses PCI Bus PCI Bus Variants Serial Buses
Introduction Electrical Considerations Data Transfer Synchronization Bus Arbitration VME Bus Local Buses PCI Bus PCI Bus Variants Serial Buses 1 Most of the integrated I/O subsystems are connected to the
More information100 Gbps/40 Gbps PCS/PMA + MAC IP Core
100 Gbps/40 Gbps PCS/PMA + MAC IP Core Getting started guide: 1. Prerequisites: In order to simulate and implement Aitia's 100 Gbps / 40 Gbps Ethernet PCS/PMA + MAC IP core you must meet the following
More informationAN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Subscribe Latest document on the web: PDF HTML Contents Contents 1. Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference
More informationFarhad Shafai, Sarance Technologies March, 2008 SARANCE TECHNOLOGIES
Technical Feasibility of 100G/40G MLD Farhad Shafai, Sarance Technologies March, 08 1 Outline Presentation is focused on the implementation of the digital logic Agenda: MLD overview 100G implementation
More informationPXIe FPGA board SMT G Parker
Form : QCF51 Date : 6 July 2006 PXIe FPGA board SMT700 1.5 20 th November 2009 G Parker Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside, Chesham, Bucks. HP5 1PS. This document is the
More informationSerial RapidIO Gen2 Protocol Analyzer
Serial RapidIO Gen2 Protocol Analyzer Serial RapidIO Protocol Analyzer & Pattern Injector Supports Serial RapidIO Gen2 or Gen 1 Descrambling & scrambling supported Tight integration and easy setup with
More informationIGLOO2 Evaluation Kit Webinar
Power Matters. IGLOO2 Evaluation Kit Webinar Jamie Freed jamie.freed@microsemi.com August 29, 2013 Overview M2GL010T- FG484 $99* LPDDR 10/100/1G Ethernet SERDES SMAs USB UART Available Demos Small Form
More informationAN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction
AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction April 2009 AN-462-1.3 Introduction Many systems and applications use external memory interfaces as data storage or buffer
More information24DSI16WRC Wide-Range 24-Bit, 16-Channel, 105KSPS Analog Input Module With 16 Wide-Range (High-Level, Low-Level) Delta-Sigma Input Channels
24DSI16WRC Wide-Range 24-Bit, 16-Channel, 105KSPS Analog Input Module With 16 Wide-Range (High-Level, Low-Level) Delta-Sigma Input Channels Features Include: Available in PMC, PCI, cpci and PC104-Plus
More informationWhite Paper. ORSPI4 Field-Programmable System-on-a-Chip Solves Design Challenges for 10 Gbps Line Cards
White Paper ORSPI4 Field-Programmable System-on-a-Chip Solves Design Challenges for 10 Gbps Line Cards Sidhartha Mohanty and Fred Koons Lattice Semiconductor Corporation October 2003 Bringing the Best
More informationML505 ML506 ML501. Description. Description. Description. Features. Features. Features
ML501 Purpose: General purpose FPGA development board. Board Part Number: HW-V5-ML501-UNI-G Device Supported: XC5VLX50FFG676 Price: $995 The ML501 is a feature-rich and low-cost evaluation/development
More informationidp TM (Internal DisplayPort TM ) Technology Overview
idp TM (Internal DisplayPort TM ) Technology Overview New Generation Large-Screen Display Internal Interface DisplayPort Developer Conference December 6, 2010 Westin Taipei Alan Kobayashi R&D Director,
More informationSection I. Arria GX Device Data Sheet
Section I. Arria GX Device Data Sheet This section provides designers with the data sheet specifications for Arria GX devices. They contain feature definitions of the transceivers, internal architecture,
More informationSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide
SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: 8.1 Document Version: 4.0 Document Date: November 2008 UG-MF9504-4.0
More informationIntel Stratix 10 Clocking and PLL User Guide
Intel Stratix 10 Clocking and PLL User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel Stratix 10 Clocking
More informationQ2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation Gbps. Revision Date: February 13, 2009
Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation 2 5.0 Gbps Revision Date: February 13, 2009 Copyrights and Trademarks Copyright 2009 Samtec, Inc. Developed in conjunction
More informationPCI Express 1.0a and 1.1 Add-In Card Transmitter Testing
Abstract PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing Joan Gibson November 2006 SR-TN062 Add-in cards designed for PCI Express require numerous tests to assure inter-operability with different
More informationAN 829: PCI Express* Avalon -MM DMA Reference Design
AN 829: PCI Express* Avalon -MM DMA Reference Design Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Latest document on the web: PDF HTML Contents Contents 1....3 1.1. Introduction...3 1.1.1.
More informationDisplayPort 1.4 Webinar
DisplayPort 1.4 Webinar Test Challenges and Solution Yogesh Pai Product Manager - Tektronix 1 Agenda DisplayPort Basics Transmitter Testing Challenges DisplayPort Type-C Updates Receiver Testing Q and
More informationFELI. : the detector readout upgrade of the ATLAS experiment. Soo Ryu. Argonne National Laboratory, (on behalf of the FELIX group)
LI : the detector readout upgrade of the ATLAS experiment Soo Ryu Argonne National Laboratory, sryu@anl.gov (on behalf of the LIX group) LIX group John Anderson, Soo Ryu, Jinlong Zhang Hucheng Chen, Kai
More informationALTDQ_DQS2 Megafunction User Guide
ALTDQ_DQS2 Megafunction ALTDQ_DQS2 Megafunction 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01089-2.2 Feedback Subscribe 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE,
More information