Register Map for the PCI-DAS6402/16

Transcription

1 Register Map for the PCI-DAS6402/16 Document Revision 1, June, 2005 Copyright 2005, Measurement Computing Corporation

2 Register Description This document describes the register map for the PCI-DAS6402/16 board. Only experienced programmers should attempt register-level programming. Overview Any operations to the PLX PCI 9080 controller registers at BADR0 require a thorough understanding of the 9080 chip specification. Detailed descriptions of the PCI 9080 operation are beyond the scope of this document. The interested reader is encouraged to obtain the latest PCI 9080 product documentation for detailed programming information. The system dynamically assigns base addresses of PCI boards. You can determine these addresses by examining the Bus Interface chip used by the board. The PCI-DAS6402/16 board uses the PLX PCI 9080 PCI Bus Interface chip. For more information on the PLX PCI 9080, refer to the latest PCI 9080 Data Book. This document is available from PLX Technology at The PCI-DAS6402/16 board provides three base address regions BADR0, BADR1 and BADR2. BADR1 provides access to the board's PLX 9080 PCI interface chip, and also provides the interrupt control status and control registers for the board. BADR2 performs data and address read/write operations. The PCI-DAS6402/16 operation registers are mapped into PCI memory address space. Unlike ISA-based designs, this board has several base addresses each corresponding to a reserved block of address space. Of the six Base Address Regions (BADRs) available in the PCI 2.1 specification, three are implemented in this design and are summarized in Table 5-1 following: Table 1. PCI base address assignments Memory Region Function Operations BADR0 PLX 9080 PCI controller operation registers 32-bit DWORD BADR2 PCI-DAS6402/16 16-bit registers and FIFOs 16-bit WORD BADR3 PCI-DAS6402/16 8-bit registers 8-bit BYTE Any operations using the PLX 9080 PCI controller registers at BADR0 require a thorough understanding of the PCI 9080 chip specification. Detailed descriptions of PCI 9080 operation are beyond the scope of this document. The interested reader is encouraged to obtain the latest PCI 9080 product documentation for detailed programming information. The PLX PCI 9080 provides internal address decoding which allows remapping of BADR2 and BADR3 to convenient Local Address values. This eases the burden of Local Bus address decoding. The remap and space-specific parameters for the PCI-DAS6402/16 are summarized in Table 5-2 below: Table 2. address remap PCI BAR Space Width Burst Enabled Size Remap Address BADR2 Register & FIFO 16 Y 4K 0x BADR3 Digital I/O & counter 8 N 4K 0x Unless otherwise specified, the remapped version of BADR2 will be referred to as LocalSpace0 while the remap of BADR3 will be referred to as LocalSpace1. 1

3 Register summaries LocalSpace0 write-only registers Table 3 summarizes the LocalSpace0 write-only registers (16-bit) Table 3. LocalSpace0 write-only registers (16-bit) Register group Register Name LocalSpace0 Offset Address Interrupt enable register 0x00 Configuration Hardware configuration register 0x02 Memory size register 0x04 control register 0 0x10 control register 1 0x12 Calibration control register 0x14 Sample interval register (LOW) 0x16 Sample interval register (HIGH) 0x18 Delay interval register (LOW) 0x1A Delay interval register (HIGH) 0x1C ADC Sample/scan count register (LOW) 0x1E Sample/scan count register (HIGH) 0x20 DAQ soft start command 0x22 DAQ single conversion command 0x24 QUEUE FIFO pointer clear command 0x26 QUEUE load command 0x28 ADC FIFO pointer clear command 0x2A QUEUE high register 0x2C control register 0 0x50 control register 1 0x52 Sample interval register (LOW) 0x54 Sample interval register (HIGH) 0x56 Delay interval register (LOW) 0x58 Delay interval register (HIGH) 0x5A DAC Re-transmit register (LOW) 0x5C Re-transmit register (HIGH) 0x5E DAC select register 0x60 DAC soft start command 0x64 DAC FIFO pointer clear command 0x66 DAC0 single conversion command 0x70 DAC1 single conversion command 0x72 LocalSpace0 read-only registers Table 4 summarizes the LocalSpace0 read-only registers (16-bit) Table 4. LocalSpace0 read-only registers (16-bit) Register Group register Name LocalSpace0 Offset Address Status Hardware status register 0x00 PIPE1 read register 0x04 ADC read pointer register 0x08 ADC ADC write pointer register 0x0C User XFER counter register (LOW) 0x10 Pre-post register 0x14 2

4 LocalSpace0 read/write registers (16-bit) Table 5 summarizes the LocalSpace0 read/write registers (16-bit) Table 5. LocalSpace0 read/write registers (16-bit) Register group Register name LocalSpace0 offset address FIFO QUEUE FIFO 0x100 ADC FIFO 0x200 DAC FIFO 0x300 LocalSpace1 read/write registers (8-bit) Table 6 summarizes the LocalSpace1 read/write registers (8-bit) Table 6. LocalSpace1 read/write registers (8-bit) Register group Register name LocalSpace1 offset address Primary digital I/O Digital port A 0x00 Digital port B 0x01 Digital port C 0x02 Port control 0x03 User counter timer Counter data 0x08 Counter control 0x0B Auxiliary digital out DOUT[3:0] 0x20 Auxiliary digital in DIN[3:0] 0x28 Register descriptions - detailed This section provides detailed descriptions of all LocalSpace0 and LocalSpace1 registers. Note that DAQ refers to analog input data acquisition, while DAC refers to analog output operations. Bit locations that are hard coded with either a (0) or a (1) must be written with these values during register accesses. LocalSpace0 write-only registers Configuration goup Interrupt enable register (address offset 0x00) OVERRUN UNDERRUN 0 0 DAC_ACTIVE DAQ_STOP DAQ_ACTIVE XINT DACDONE DAC_IENB DAC_ISRC1 DAC_ISRC0 DAQDONE DAQ_IENB DAQ_ISRC1 DAQ_ISRC0 15 OVERRUN 14 UNDERRUN 11 DAC_ACTIVE 10 DAQ_STOP 9 DAQ_ACTIVE 8 XINT DAQ overrun enable If this bit is set, a DAQ overrun condition can be detected. DAQ overrun does not cause an interrupt but does set a bit in the Status register. DAC underrun enable If this bit is set, a DAC underrun condition can be detected. DAC underrun does not cause an interrupt but does set a bit in the Status register. DAC ACTIVE interrupt enable If this bit is set, an interrupt is generated when the DAC waveform circuitry is active. DAQ STOP interrupt enable If this bit is set, an interrupt is generated when the stop trigger (TRIG2) is detected. DAQ ACTIVE interrupt enable If this bit is set, an interrupt is generated when a DAQ sequence is active. XINT interrupt enable If this bit is set, the external XINT signal can generate an interrupt. 3

5 7 DACDONE 6 DAC_IENB 5-4 DAC_ISRC(1:0) 3 DAQDONE 2 DAQ_IENB DACDONE interrupt enable If this bit is set, an interrupt is generated when the DAC sequence completes. A DAC sequence ends by running its course or when an UNDERRUN condition occurs. DAC interrupt enable If this bit is set, one of the DAC_ISRC conditions will generate an interrupt. DAC interrupt source select These bits are used to select an additional DAC interrupt source in addition to the DACDONE source. DAC_ISRC1 DAC_ISRC0 Description 0 0 DAC FIFO ¼ Empty 0 1 DAC High Channel 1 X DAC Re-transmit DAQDONE interrupt enable If this bit is set, an interrupt is generated when the DAQ sequence completes. A DAQ sequence ends by running its course or when an OVERRUN condition occurs. DAQ interrupt enable If this bit is set, one of the DAQ_ISRC conditions will generate an interrupt. DAQ interrupt source select These bits are used to select an additional DAQ interrupt source in addition to the DAQDONE source. DAQ_ISRC1 DAQ_ISRC0 Description 1-0 DAQ_ISRC(1:0) 0 0 DAQ FIFO ¼ Full 0 1 DAQ Single Conversion: An interrupt is generated each conversion. 1 0 DAQ EOSCAN: During multi-channel scans, an interrupt is generated after the last channel in the external queue memory or last channel of the internal queue counter has been captured. 1 1 DAQ EOSEQ: During multi-channel scans, an interrupt is generated after each interval delay. Hardware configuration register (address offset 0x02) DMACH_SEL EXT_QUE XINT_POL 0 0 SSH/DACLK SSH_POL DMACH_SEL DMA channel select. The DMA Channel select signal selects which PLX PCI 9080 DMA Controllers (0 or 1) will be dedicated to the DAQ or DAC functions. If this bit is reset, DMA Channel 0 and 1 are allocated to the DAQ and DAC functions respectively. If this bit is set, DMA Channel 0 and 1 are allocated to the DAC and DAQ functions respectively. 9 EXT_QUE External queue select. If this bit is reset, an internal channel queue counter is used to sequence through the channels. If this bit is set, the external queue is enabled. 8 XINT_POL External interrupt polarity; 0=low-to-high transition, 1= high to low transition 5 1 SSH/DACLK Pin 52 output signal; 0 = SSH (default), 1 = DAC Pacer 4 1 SSH_POL SSH Polarity; 0 = Hold high (default), 1 = Hold low 1 Added in hardware revision 3. In previous revisions, these functions were fixed at the default value. 4

6 Memory size register (address offset 0x04) DSEG3 DSEG2 DSEG1 DSEG ASEG2 ASEG1 ASEG0 DAC buffer segment size (¼ FIFO size): The ¼ FIFO size can range from 256 samples deep upwards to 4K samples deep, in 256 sample increments. DSEG(3:0) ¼ FIFO Size FIFO size 11-8 DSEG(3:0) 0xF 256 1K 0xE 512 2K 0xC 1K 4K 0x8 2K 8K 0x0 4K 16K ADC buffer segment size (¼ FIFO size): The ¼ FIFO size can range from 256 samples deep upwards to 2K samples deep, in 256 sample increments. ASEG(2:0) ¼ FIFO Size FIFO size 2-0 ASEG(2:0) 0x K 0x K 0x4 1K 4K 0x0 2K 8K ADC Register Group DAQ control register 0 (address offset 0x10) DAQ_EN B 0 GATE_SEQ SAMPCNT ENB XCONV_PO L 0 TRIG2_ENB TRIG2_POL TRIG2_SR C TRIG1_P OL TRIG1_SR C1 TRIG1_SRC0 AGATE_PO L AGATE_L VL AGATE_SRC 1 AGATE_SRC0 15 DAQ_ENB Data acquisition enable This bit enables and disables a data acquisition operation. It is the master enable for DAQ operations. 13 GATE_SEQ GATE ON sequence: If this bit is set in multi-channel mode then an inactive gate will pause the data acquisition after the current scan sequence has completed. If this bit is cleared then an inactive gate will pause the data acquisition immediately. 12 SAMPCNT_ENB Sample counter enable. When this bit is set, the DAQ Sample counter is enabled. This bit must be set for pre-post triggered mode. 11 XCONV_POL External A/D convert polarity control. This bit controls the polarity of the External A/D convert input signal. If a low-to-high edge of XCONV is to be used to initiate a conversion then this bit should be cleared. If a high-to-low edge of XCONV is to be used to initiate a conversion then this bit should be set. 9 TRIG2_ENB TRIG2 pre-trigger enable. This bit enables pre-trigger mode. 8 TRIG2_POL TRIG2 trigger polarity select: 0 = rising edge trigger; 1 = falling edge trigger. 5

7 7 TRIG2_SRC TRIG2 pre-trigger source select; 0 = A/D Stop Trigger Input pin; 1 = Analog Trigger. 6 TRIG1_POL TRIG1 trigger polarity select: 0 = rising edge trigger; 1 = falling edge trigger. TRIG1 Source select These bits are used to select TRIG1 source. 5-4 TRIG1_SRC(1:0) TRIG1_SRC1 TRIG1_SRC0 Description 0 0 Disabled 0 1 Soft_Trigger 1 0 External A/D Start Trigger Input 1 1 Analog Trigger 3 AGATE_POL AGATE polarity select: 0 = active high gate; 1 = active low gate. 2 AGATE_LVL AGATE Level select; 0 = edge sensitive gate; 1 = level sensitive gate; AGATE Source select These bits are used to select AGATE source. 1-0 AGATE_SRC(1:0) DAQ control register 1 (address offset 0x12) AGATE_SRC1 AGATE_SRC0 Description 0 0 Disabled 0 1 Soft_Gate 1 0 External A/D Pacer Gate Input 1 1 Analog Gate MODE3 MODE2 MODE1 MODE SFT_AGATE 0 0 ATRIGMD2 ATRIGMD1 ATRIGMD Mode(3:0) DAQ mode select bits. Select data acquisition mode as detailed in Table 9. Software DAQ gate When SFT_GATE is cleared, no A/D conversions take place. SFT_AGAT 6 When SFT_GATE is set, A/D conversions take place normally. SFT_GATE can be used E as a software gating tool, or to inhibit random conversions during setup operations. ATRIGMD( 3-1 Analog trigger/gate mode select bits. 2:0) Analog trigger/gate modes There are many triggering/gating options for the analog trigger function. The output of the analog trigger circuit can be used as the source for TRIG1, TRIG2, or AGATE. In turn, TRIG1 can be used as the trigger source for the analog outputs. The ATRIGMD[2:0] bits select the type of trigger the ATRIG circuit produces for a given set of conditions (e.g., compare level(s), hysteresis mode etc). Depending on the mode selected, the ATRIG block uses one or both of the analog output channels as the HI/LO comparator reference(s). It is important to keep this sharing of resources in mind when both Analog Output and Analog Trigger functions are required at the same time. Generically, the ATRIG block will provide a high-going transition or level for a given configuration. The output is then selected as the appropriate TRIG1, TRIG2, or AGATE source. Table 5-7 (following) describes the basic settings of the ATRIGMD[2:0] bits and the DAC resources used for each mode. 6

8 Table 7. Analog trigger modes ATRIGMD2 ATRIGMD1 ATRIGMD0 Mode High threshold DAC Low threshold DAC INACTIVE Not used Not used Positive Hysteresis Negative Hysteresis DAC0 Threshold DAC1 Threshold DAC1 DAC1 DAC1 DAC1 DAC0 DAC0 Not Used Not Used Window DAC1 DAC0 Description Inactive state. Prior to programming the analog trigger to the desired state the analog trigger should be programmed to the inactive state to clear out the trigger circuitry. The trigger is generated when the signal value is greater than the highvalue, with hysteresis specified by low_value. The trigger is generated when the signal value is greater than the lowvalue, with hysteresis specified by high_value. The trigger/gate is generated with respect to DAC0 setting. The trigger/gate is generated with respect to DAC1 setting. The trigger is generated when the signal value is between the low-value and high-value. Table 8 provides further details of the trigger source/type and polarity settings for the most common analog trigger configurations. Note that the software must cycle through the INACTIVE state before setting up the desired mode. Table 8. Typical analog trigger configurations ATRIG Mode GATE_NEG_HYST GATE_POS_HYST GATE_ABOVE GATE_BELOW GATE_IN_WINDOW GATE_OUT_WINDOW TRIG_POS_SLOPE TRIG_NEG_SLOPE AGATE source ATRIG ATRIG ATRIG ATRIG ATRIG ATRIG SOFT GATE SOFT GATE TRIG1 source SOFT TRIG SOFT TRIG SOFT TRIG SOFT TRIG SOFT TRIG SOFT TRIG TRIGPOL AGATEPOL ATRIGMD2 ATRIGMD1 ATRIGMD ATRIG ATRIG

9 Mode 3 Mode2 Mode1 Mode Single Table 9. Data acquisition modes Single/multichannel Interval delay Single Yes 8 Prescale Single Yes Single Yes Yes Multi Multi. Yes Multi. Yes Multi. Yes Yes Multi. Yes Multi. Yes Multi. Yes Delay interval only Sample & delay interval Multi. Yes Yes Cont. Convert External convert Description Single channel mode. Single channel w/programmable prescale mode. Single Channel & continuous ADC convert mode. Single channel, programmable prescale & cont. ADC convert mode. Multi-channel mode. Multi-channel with programmable prescale mode. Multi-channel & continuous ADC convert mode. Multi-channel, programmable prescale & cont. ADC convert mode. Multi-channel with programmable interval delay mode. Resolution of sample & delay intervals = 25 ns. Multi-channel with programmable & pre-scaled interval delay mode. Resolution of the sample interval = 25 ns; of the delay interval = 10 µs. Multi-channel mode pre-scaled sample & delay intervals. Resolution of sample & delay intervals = 10 µs. Multi-channel, programmable interval mode & continuous ADC convert mode. 12- bit programmable prescale counter generates sample rate (resolution = 25 ns). Sample interval counter determines delay interval. The delay interval base clock frequency = sample rate.

10 Mode 3 Mode2 Mode1 Mode0 Single/multichannel Interval delay Prescale Cont. Convert Single Yes Multi. Yes Multi. Yes Yes Yes Calibration register (address offset 0x14) External convert Description Single Channel with external convert mode. Multi-channel mode with external convert mode. Multi-channel, programmable interval mode & external ADC convert mode. The external convert signal determines the sample rate. The sample interval counter is used to determine the delay interval. The delay interval base clock frequency = external convert rate GEN_SCLK SDI CALENB CSRC2 CSRC1 CSRC0 0 SEL8402N SEL8800N 8 GEN_SCLK Generate SCLK. If this bit is set the SCLK pin is pulsed to clock the current value of the SDI pin into the selected bit serial device. 7 SDI Serial Data In signal. This signal is used in conjunction with SCLK to serially shift data into the ADC and DAC calibration devices. 6 CALENB Calibration Enable: 0 = disabled; 1 = enabled. Disconnects CH0HI from and connects source selected via CSRC[2:0] 5-3 CSRC(2:0) Calibration source select: CSRC2 CSRC1 CSRC0 Cal Source AGND V V V V mv DAC DAC1 1 SEL8402N 0 SEL8800N Chip select for the 8402 digital potentiometer. When this bit is set the SEL8402N signal is low. This bit is reset to 1. Chip select for the 8800 Octal trim DAC. When this bit is set the SEL8800N signal is low. This bit is reset to 1. 9

11 ADC sample interval register, lower (address offset 0x16) ADCSIL15 ADCSIL14 ADCSIL13 ADCSIL12 ADCSIL11 ADCSIL10 ADCSIL9 ADCSIL8 ADCSIL7 ADCSIL6 ADCSIL5 ADCSIL4 ADCSIL3 ADCSIL2 ADCSIL1 ADCSIL ADCSIL(15:0) ADC sample interval lower - The lower 16 bits of the 24-bit sample interval divisor. ADC sample interval register, upper (address offset 0x18) ADCSIL23 ADCSIL22 ADCSIL21 ADCSIL20 ADCSIL19 ADCSIL18 ADCSIL17 ADCSIL ADCSIL(23:16) ADC sample interval upper The upper 8 bits of the 24-bit Sample Interval divisor. Notes: 1) ADC Pacer Frequency = Base_clock/(Divider + 3) 2) This register must be initialized after power-on to 0X00FFh before any DAQ operations can start. ADC delay interval register, lower (address offset 0x1A) ADCDIL15 ADCDIL14 ADCDIL13 ADCDIL12 ADCDIL11 ADCDIL10 ADCDIL9 ADCDIL8 ADCDIL7 ADCDIL6 ADCDIL5 ADCDIL4 ADCDIL3 ADCDIL2 ADCDIL1 ADCDIL ADCDIL(15:0) ADC delay interval lower The lower 16 bits of the 24-bit sample delay divisor. ADC delay interval register, upper (address offset 0x1C) ADCDIL23 ADCDIL22 ADCDIL21 ADCDIL20 ADCDIL19 ADCDIL18 ADCDIL17 ADCDIL ADCDIL(23:1 6) ADC delay interval upper - The upper 8 bits of the 24-bit sample delay divisor. 10

12 ADC sample/scan count register, lower (address offset 0x1E) ADCSMP15 ADCSMP14 ADCSMP13 ADCSMP12 ADCSMP11 ADCSMP10 ADCSMP9 ADCSMP8 ADCSMP7 ADCSMP6 ADCSMP5 ADCSMP4 ADCSMP3 ADCSMP2 ADCSMP1 ADCSMP ADCSMP(15:0) ADC sample count lower The lower 16 bits of the 24-bit sample counter. Note: The sample counter must always be loaded with a value other than zero prior to enabling a DAQ sequence. This holds true even when the sample counter is disabled via the SAMPCNT_ENB bit in the DAQ Control 0 register. ADC sample/scan count register, upper (address offset 0x20) ADCSMP23 ADCSMP22 ADCSMP21 ADCSMP20 ADCSMP19 ADCSMP18 ADCSMP17 ADCSMP ADCSMP(23:16) ADC sample count upper - The upper 8 bits of the 24-bit sample counter. DAQ start register (address offset 0x22) X X X X X X X X X X X X X X X X 15-0 Don t care Accessing DAQ start register location initiates a multiple A/D conversion data acquisition operation. To trigger the board with the start DAQ register, the TRIG1_SRC(1:0) bits need to select the soft-trigger source. Otherwise strobing the start DAQ register has no effect. DAQ single conversion register (address offset 0x24) X X X X X X X X X X X X X X X X 11

13 15-0 Don t care Prior to issuing a DAQ single conversion command, access the queue load register to select the desired channel, gain & mode (single ended, differential, unipolar or bipolar). Accessing the single conversion register location initiates a single A/D conversion. The actual ADC value can be retrieved via the PIPE1 read register. Queue pointer clear register (address offset 0x26) X X X X X X X X X X X X X X X X 15-0 Don t care Accessing the queue pointer clear register resets the queue pointer to home state. Queue load register (address offset 0x28) EOSCAN EOSEQ 0 SEDIFFN UNIBIPN 0 GSEL1 GSEL0 0 0 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 15 EOSCAN End-of-scan flag. When the EOSCAN flag is reached, the circuitry stops and waits the programmable delay interval before sequencing back to the top of the channel sequence list. 14 EOSEQ End-of-sequence. When the EOSEQ flag is reached, the circuitry stops and waits the programmable delay interval before sequencing to the start of the next channel sequence in the list. 12 SEDIFFN Channel single-ended/differential This bit configures the analog input section for single-ended or differential mode; 0 = differential, 1 = single-ended. 11 UNIBIPN Channel unipolar/bipolar - This bit configures the ADC for unipolar or bipolar mode; 0 = bipolar, 1 = unipolar. 9-8 GSEL(1:0) Channel gain select - These two bits control the gain settings of the input PGIA for the selected channel. UNIBIPN GSEL1 GSEL0 Range Bipolar 10 V Bipolar 5 V Bipolar 2.5 V Bipolar 1.25 V Unipolar 10 V Unipolar 5 V Unipolar 2.5 V Unipolar 1.25 V 5-0 CHSEL(5:0) Input channel select - These six bits control the input multiplexer address setting for selecting 1-of-64 analog input channels routed to the ADC When the internal queue counter is used to sequence through the channels, initialize the Channel High register with the desired high channel to be scanned prior to accessing the Queue Load register. Access 12

14 the Queue Load register prior to issuing an A/D convert for the first time to prime the Queue holding register. When the external RAM queue is used to sequence through the channels, program the external queue before accessing the Queue Load register. The external queue bit fields match the fields in the Queue load register. Access the Queue Load register before issuing an A/D convert for the first time to prime the Queue holding register. With an external queue, data is a don t-care and does not have to match the first scan entry in the sequence list. ADC buffer pointer clear register (address offset 0x02A) X X X X X X X X X X X X X X X X 15-0 Don t care Accessing the ADC buffer pointer clear register resets the pointer to home state, and clears the internal STC pipeline registers (PIPE1 and PIPE0). Queue high register (address offset 0x2C) 0 0 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 5-0 CHSEL(5:0) High channel select address. When the internal queue counter is used to sequence through the channels, initialize this register with the high-channel address. After the high channel has been converted, the queue counter is re-loaded with the low channel address. DAC register group DAC control register 0 (address offset 0x50) DAC_ENB CYCLESTOP PRESCAL E WFM_MD1 WFM_MD0 0 XUPD_ENB WTRIGSRC1 WTRIGS RC0 WTRIG_P OL WGATE_L VL WGATE_E NB WGATE_S RC 13

15 15 DAC_ENB DAC enable - Enable the DAC controller. 14 CYCLESTOP Cyclic stop enable This bit controls how a DAC cyclic sequence terminates. If this bit is cleared, DAC cyclic waveform generation terminates after the next update completes. If this bit is set, the DAC cyclic waveform generates terminates cleanly and halts when the next end-of-buffer is encountered. 11 PRESCALE 9-8 WFM_MD(1:0) DAC prescale enable. The base clock for the sample interval & delay interval counters is 40 MHz if this bit is set. The base clock is 100 khz if this bit is cleared. DAC waveform mode select: These bits are used to select the desired DAC Waveform Generation mode. WFM_MD1 WFM_MD0 Mode 0 0 Posted non-cyclic 0 1 continuous cyclic 1 0 programmed cyclic 1 1 pulsed waveform 6 XUPD_ENB External D/A Update Enable. This bit enables the external XUPDATE signal as the DAC pacer source. Waveform TRIG Source Select: These bits select the waveform trigger source. 5-4 WTRIGSRC(1:0) g WTRIG_SRC1 WTRIG_SRC0 Description Upper User Transfer Counter 0 0 Disabled 0 1 Soft_Trigger 1 0 External WTRIG 1 1 ADC Trig1 3 WTRIG_POL WTRIG trigger polarity select: 0 = rising edge trigger; 1 = falling edge trigger. 2 WGATE_LVL WGATE Level select; 0 = edge sensitive gate; 1 = level sensitive gate. 1 WGATE_ENB WGATE Enable; 0 = disabled, 1 = enabled. 0 WGATE_SRC WGATE source; 0 = External WTRIG; 1 = Soft_gate. DAC control register 1 (address offset 0x52) DAC_OE 0 SFT_WGATE DACHOG DAC1R1 DAC1R0 DAC0R1 DAC0R0 14

16 7 DAC_OE DAC output enable 5 SFT_WGATE 4 DACHOG When performing multi-channel DAC scans, all of the DAC input registers have to be loaded before the common update signal (DAC_UPDATE) arrives. When the DACHOG bit is set, the memory arbiter will retrieve all of the DAC channels data back-to-back before allowing another requesting device to access the shared SRAM resource. This can be useful in applications where the DACs should be given highest bandwidth priority. For slow DAC applications, the DACHOG bit should be cleared to allow all memory requesting devices equal priority 3-2 DAC1R(1:0) These bits configure the range of DAC1 in the analog output section. 1-0 DAC0R(1:0) These bits configure the range of DAC0 in the analog output section. DACnR1 DACnR0 DACn Range 0 0 Bipolar 5 V 0 1 Bipolar 10 V 1 0 Unipolar 5 V 1 1 Unipolar 10 V DAC sample interval register, lower (address offset 0x54) DACSIL15 DACSIL14 DACSIL13 DACSIL12 DACSIL11 DACSIL10 DACSIL9 DACSIL8 DACSIL7 DACSIL6 DACSIL5 DACSIL4 DACSIL3 DACSIL2 DACSIL1 DACSIL DACSIL(15:0) DAC sample interval lower - The lower 16 bits of the 24-bit sample interval divisor. Note: DAC pacer frequency = Base_clock/(divider + 2) DAC sample interval register, upper (address offset 0x56) DACSIL23 DACSIL22 DACSIL21 DACSIL20 DACSIL19 DACSIL18 DACSIL17 DACSIL DACSIL(23:16) DAC sample interval upper The upper 8 bits of the 24-bit sample interval divisor. DAC delay interval register, lower (address offset 0x58) DACDIL15 DACDIL14 DACDIL13 DACDIL12 DACDIL11 DACDIL10 DACDIL9 DACDIL8 DACDIL7 DACDIL6 DACDIL5 DACDIL4 DACDIL3 DACDIL2 DACDIL1 DACDIL0 15

17 15-0 DACDIL(15:0) DAC delay interval lower - The lower 16 bits of the 24-bit sample delay divisor. DAC delay interval register, upper (address offset 0x5A) DACDIL23 DACDIL22 DACDIL21 DACDIL20 DACDIL19 DACDIL18 DACDIL17 DACDIL DACDIL(23:16) DAC delay interval upper - The upper 8 bits of the 24-bit sample delay divisor. DAC re-transmit register, lower (address offset 0x5C) RTSMP15 RTSMP14 RTSMP13 RTSMP12 RTSMP11 RTSMP10 RTSMP9 RTSMP8 RTSMP7 RTSMP6 RTSMP5 RTSMP4 RTSMP3 RTSMP2 RTSMP1 RTSMP RTSMP(15:0) RT sample count lower - The lower 16 bits of the 24-bit sample counter. RT re-transmit register, upper (address offset 0x5E) RTSMP23 RTSMP22 RTSMP21 RTSMP20 RTSMP19 RTSMP18 RTSMP17 RTSMP DACSMP(23:16) DAC sample count upper - The upper eight bits of the 24-bit Sample Counter. DAC select register (address offset 0x60) DACHI 0 0 DACLO 3 DACHI 0 DACLO DAC high channel select register. This bit is used to select the high channel during a multichannel DAC scan operation. DAC low channel select register. This bit is used to select the low channel during a multi-channel DAC scan operation. Note: The DAC high channel must be greater than or equal to the DAC low channel. 16

18 DAC start register (address offset 0x64) X X X X X X X X X X X X X X X X 15-0 Don t care Accessing the DAC start register location initiates a multiple D/A conversion waveform generation operation. To trigger the board with the Start DAC register, the WTRIG_SRC (1:0) bits must select the soft-trigger source. Otherwise, strobing the DAC Start register has no effect. DAC buffer pointer clear register (address offset 0x66) X X X X X X X X X X X X X X X X 15-0 Don t care Accessing the DAC buffer pointer clear register resets the pointer to home state. DAC data registers The next two registers are used to initiate non-timed single DAC updates for DAC0 and DAC1 respectively. The input coding for the 16-bit DACs is described in Table 5-10 below: Table 10- DAC input coding DAC range Input code binary Input code hex Output voltage +/- 5 V x µv V +/- 5 V x V +/- 5 V xFFFF V +/- 10 V x µv V +/- 10 V x V +/- 10 V xFFFF V 0 to 5 V x µv V 0 to 5 V x V 0 to 5 V xFFFF V 0 to 10 V x µv V 0 to 10 V x V 0 to 10 V xFFFF V 17

19 DAC0 single conversion register (address offset 0x70) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D D[15:0] DAC0 data Accessing the DAC0 single conversion register location initiates a single D/A conversion on channel 0. DAC1 single conversion register (address offset 0x72) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D D[15:0] DAC1 data Accessing the DAC1 Single Conversion Register location initiates a single D/A conversion on Channel 1. LocalSpace0 read-only registers Status register Hardware status register (address offset 0x00) REV3 REV2 REV1 REV0 PIPEFULL1 PIPEFULL0 TRIG2_FLG XINT_FLG DAQDONE DACDONE ASRC_FLG DSRC_FLG DAQ_ACTIVE DAC_ACTIVE DAQ_OVERRUN DAC_UNDERRUN REV(3:0) Hardware (STC chip) revision PIPEFULL(1:0) STC PIPE FULL status: The STC contains two internal pipe line registers in the DAQ data path. At the completion of a DAQ operation these two pipeline registers may contain residual ADC data. The PIPEFULL(1:0) bits provides status on which pipe line register contains valid data. 9 TRIG2_FLG If this bit is set, a DAQ stop trigger interrupt is pending. 8 XINT_FLG If this bit is set, an external interrupt is pending. 7 DAQDONE If this bit is set, the current DAQ operation has been completed. If the DAQDONE interrupt was enabled, then it is pending. 6 DACDONE If this bit is set, the current DAC operation has been completed. If the DAQDONE interrupt was enabled, then it is pending. 5 ASRC_FLG If this bit is set, one of the DAQ interrupt sources (DAQ_ISRC(1:0) field in the Interrupt Enable Register) is pending. This bit can also be polled to determine the ADC_BUSY status after a Single Covert Command has been issued. 4 DSRC_FLG If this bit is set, one of the DAC interrupt sources (DAC_ISRC(1:0) field in the Interrupt Enable Register) is pending. 18

20 3 DAQ_ACTIVE If this bit is set, the current DAQ operation is active. 2 DAC_ACTIVE If this bit is set, the current DAC operation is active. 1 DAQ_OVERRUN If this bit is set, an overrun error was detected during the previous DAQ operation. 0 DAC_UNDERRUN If this bit is set, an underrun error was detected during the previous DAC operation. All pending card-generated interrupts are serviced by reading the hardware status register. ADC register group ADC data register Read the PIPE1 register to retrieve ADC data when conversions are performed in non-paced mode (i.e. single conversion mode). Reading the register clears it. Paced ADC conversion data is available at the ADC FIFO register described later in this document. The output coding for the ADC is shown in Table 11: Table 11 ADC output coding Mode Output code binary Output code hex Bipolar -FS x0000 Bipolar 0V x8000 Bipolar +FS xFFFF Unipolar 0 V x0000 Unipolar +FS / x8000 Unipolar +FS xFFFF PIPE1 read register (address offset 0x04) PIPE15 PIPE14 PIPE13 PIPE12 PIPE11 PIPE10 PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE PIPE(15:0) PIPE 1 register data. ADC read pointer register (address offset 0x08) 0 ARPNTR1 4 ARPNTR13 ARPNTR12 ARPNTR11 ARPNTR10 ARPNTR9 ARPNTR8 ARPNTR7 ARPNTR6 ARPNTR5 ARPNTR4 ARPNTR3 ARPNTR2 ARPNTR1 ARPNTR0 19

21 14-0 ARPNTR(14:0) The lower ADC read pointer data. The overall ADC read pointer is a 17-bit address. This register provides the lower 15-bits. Reference the upper user transfer counter for the remaining upper two bits. ADC write pointer register (address offset 0x0C) 0 AWPNTR1 4 AWPNTR13 AWPNTR12 AWPNTR11 AWPNTR10 AWPNTR9 AWPNTR8 AWPNTR 7 AWPNTR6 AWPNTR5 AWPNTR4 AWPNTR3 AWPNTR2 AWPNTR1 AWPNTR AWPNTR(14:0) The lower ADC write pointer data. The overall ADC write pointer is a 17-bit address. This register provides the lower 15-bits. Reference the upper user transfer counter for the remaining upper two bits. Lower user transfer counter register (address offset 0x10) XFERCNT15 XFERCNT14 XFERCNT13 XFERCNT12 XFERCNT11 XFERCNT10 XFERCNT9 XFERCNT8 XFERCNT7 XFERCNT6 XFERCNT5 XFERCNT4 XFERCNT3 XFERCNT2 XFERCNT1 XFERCNT XFERCNT(15:0) Lower user transfer counter data. The overall user transfer counter has a 24-bit address. This register provides the lower 16 bits. Reference the upper user transfer counter for the remaining upper 8 bits. Pre-post register (address offset 0x14) AWPNTR16 AWPNTR15 ARPNTR16 ARPNTR CHAIN_FLG1 CHAIN_FLG

22 15-14 AWPNTR(16:15) ARPNTR(16:15) Upper ADC write pointer bits. These bits are grey scale encoded and should be remapped prior to being used to determine the final ADC Write pointer address. Remap as shown below: Upper ADC read pointer bits. These bits are grey scale encoded and should be remapped prior to being used to determine the final ADC Write pointer address. Remap as shown below: Chain flag bits. These bits are used to help determine what scatter-gather chain entry data was last DMA transferred to. These bits can be compared to the LAD(4:3) bits programmed in the DMA Channel Local Address register to guarantee that the correct final chain entry has been located. 7-6 CHAIN_FLG(1:0) Register value AWPNTR(16:15) Re-mapped value AWPNTR(16:15) Register value ARPNTR(16:15) Re-mapped value ARPNTR(16:15) 00b 00b 00b 00b 01b 01b 01b 01b 10b 11b 10b 11b 11b 10b 11b 10b LocalSpace0 read/write registers FIFO Group QUEUE FIFO register (address offset 0x100) The bit fields in the Queue FIFO register mirror those of the Queue Load register described earlier. The QUEUE FIFO register is used when the EXT_QUE bit is set in the Hardware Configuration register at LocalSpace0 + 0x02. The external queue should only be used where non-sequential channels and multiple ranges are required. Sequential channel, fixed-gain applications should use the internal queue channel sequencer. EOSCAN EOSEQ 0 SEDIFFN UNIBIPN 0 GSEL1 GSEL0 0 0 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 21

23 15 EOSCAN 14 EOSEQ 12 SEDIFFN 11 UNIBIPN End-Of-Scan flag. When the EOSCAN flag is reached, the circuitry stops and waits the programmable delay interval before sequencing back to the top of the channel sequence list. End-Of-Sequence. When the EOSEQ flag is reached, the circuitry stops and waits the programmable delay interval before sequencing to the start of the next channel sequence in the list. Channel Single-Ended/Differential - This bit configures the analog input section for singleended or differential mode. 0 = differential, 1 = single-ended. Channel Unipolar/Bipolar - This bit configures the ADC for unipolar or bipolar mode.. 0 = bipolar, 1 = unipolar. Channel Gain Select These two bits control the gain settings of the input PGIA for the selected channel. UNIBIPN GSEL1 GSEL0 Range 9-8 GSEL(1:0) Bipolar 10V Bipolar 5V Bipolar 2.5V Bipolar 1.25V Unipolar 10V Unipolar 5V Unipolar 2.5V Unipolar 1.25V Perform the following steps to create an acquisition sequence using arbitrary ranges and non-sequential channels: 1. Enable the external queue via EXT_QUE bit at LocalSpace0 + 0x Clear the QUEUE pointers via a write to LocalSpace0 + 0x Build the desired QUEUE buffer by performing multiple writes to the QUEUE FIFO register. Each write corresponds to a given channel/gain setting in the Queue. 4. Initialize the Queue by performing a write to the Queue Load register at LocalSpace0 + 0x28. Data is don t care. 5. Set up normal acquisition parameters (pacer rate, triggering etc.) and collect data. Example: An application requires single-ended scanning of channels 0, 2, 3, and 5. Channels 0 and 2 need to be at BIP10V range while CH3 and CH5 require UNI5V and BIP1P25V, respectively. It is desired that this sequence be repeated until 100 samples are gathered (i.e. 25 scans). Queue entry 0x1000 0x1002 0x1903 0xDB05 Comments CH0, SE, BIP10V CH2, SE, BIP10V CH3, SE, UNI5V CH5, SE, UNI1P25V, End-of-Scan, End-of- Sequence Repeat until sample counter expires 22

24 ADC FIFO register (address offset 0x200) ADFIFO15 ADFIFO14 ADFIFO13 ADFIFO12 ADFIFO11 ADFIFO10 ADFIFO9 ADFIFO8 ADFIFO7 ADFIFO6 ADFIFO5 ADFIFO4 ADFIFO3 ADFIFO2 ADFIFO1 ADFIFO ADFIFO(15:0) 16-bit ADC data This register is read via the System Timing Controller chip during DMA or Direct Slave Read operations and is used with scanned acquisitions. Resultant data from single non-paced ADC conversions is read from the PIPE1 register located at LocalSpace0 + 0x04 as described earlier. Although this register is read/write-capable, it is treated as a read-only register during normal ADC operations. Writing would only occur during diagnostic testing of the ADC buffer memory. DAC FIFO register (address offset 0x300) DAFIFO15 DAFIFO14 DAFIFO13 DAFIFO12 DAFIFO11 DAFIFO10 DAFIFO9 DAFIFO8 DAFIFO7 DAFIFO6 DAFIFO5 DAFIFO4 DAFIFO3 DAFIFO2 DAFIFO1 DAFIFO DAFIFO(15:0) 16-bit DAC data This register is written via the System Timing Controller chip during DMA or Direct Slave Write operations. It is used during DAC waveform generation. For simultaneous DAC0/DAC1 operation, the data must be interleaved in the buffer starting with DAC0 then DAC1. Although this register is read/write-capable, it is treated as a write-only register during normal DAC operations. Reading would only occur during diagnostic testing of the DAC buffer memory or during write-verify operations. Note that writes to the QUEUE FIFO may not be performed during operations that involve writes to the DAC FIFO register (i.e. waveform generation using DMA or loading of the DAC buffer for cyclic operation). LocalSpace1 read/write registers LocalSpace1 is an 8-bit space reserved for digital I/O and counter/timer operations. Bursting to this space is not supported since it is not required for these functions. Two separate digital I/O blocks are incorporated in the PCI-DAS6402/16. The first uses an industry-standard 85C55 whose data lines are available on the 40-pin header provided at the rear of the card. The second group of DIO is available at the 100-pin user-connector. The group is comprised of four dedicated DIN lines and four dedicated DOUT lines. A single 16-bit counter timer (one channel of an industry-standard 82C54) is also available to the user with its control and signal line available at the 100-pin connector. 23

25 Primary digital I/O group DIO 24 registers Digital port A (read/write) offset: 0x00 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Digital port B (read/write) offset: 0x01 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Digital port C (read/write) offset: 0x02 PCH3 PCH2 PCH1 PCH0 PCL3 PCL2 PCL1 PCL0 DIO control register (write-only) offset: 0x03 D7 D6 D5 D4 D3 D2 D1 D0 Table 12 summarizes the possible I/O port configurations (Mode 0). NOTE: Modes 1 and 2 can be programmed in the 82C55. Refer to the manufacturer s application manual available on-line from Table 12 DIO configuration (Mode 0) D4 D3 D1 D0 HEX Decimal Port A Port C upper Port B Port C Lower OUT OUT OUT OUT OUT OUT OUT IN OUT OUT IN OUT OUT OUT IN IN OUT IN OUT OUT OUT IN OUT IN A 138 OUT IN IN OUT B 139 OUT IN IN IN IN OUT OUT OUT IN OUT OUT IN IN OUT IN OUT IN OUT IN IN IN IN OUT OUT IN IN OUT IN A 154 IN IN IN OUT B 155 IN IN IN IN NOTE: D7 is always 1; D6, D5, D2 are always 0 (for Mode 0). 24

26 User Counter Timer Group 8254 counter data (read/write) offset: 0x08 D7 D6 D5 D4 D3 D2 D1 D control register (write-only) offset: 0x0B D7 D6 D5 D4 D3 D2 D1 D0 The control register is used to set the operating Modes of 8254 Counter 0. Writing the correct Mode information to the Control Register configures a counter. Count data is then written to the Counter Data Register. The Counters on the 8254 are 16-bit devices. Since the interface to the 8254 is 8-bits wide, Count data is written to the Counter Register as two successive bytes. First, the low byte is written, then the high byte. Further information can be obtained on the 8254 data sheet, available from Intel or Harris. Auxiliary digital I/O registers These bits are LSTTL-compatible, general-purpose digital I/O lines. Digital output register (write-only) offset: 0x DO3 DO2 DO1 DO0 Digital input register (read-only) offset: 0x DI3 DI2 DI1 DI0 25

27 RegMapPC-CARD-DAC08.doc RegMapPCI-DAS doc Measurement Computing Corporation Measurement 16 Commerce Computing Boulevard, Corporation Middleboro, Massachusetts 10 Commerce Way (508) Suite 1008 Norton, Massachusetts Fax: (508) (508) Fax: (508)