STC Register Map for the PCI-DAS6000 Series

Transcription

1 STC Register Map for the PCI-DAS6000 Series Revision 1, January, 2002 Copyright 2002, Measurement Computing Corporation

2 Memory Map Space width Burst A(12:11) Size Remap PCI Base PLX space Enabled Address Address Register & 16-bits Y 1X 4K bytes 0x BADR2 Local Space 0 FIFO space 8-bit peripheral devices space (memory mapped) 8-bits N 01 4K bytes 0x BADR3 Local Space 1 (memory mapped) Register Map 16 Bit write only registers Register Group Register Name Offset Address Configuration Group Interrupt Enable Register* 0x00 Hardware Configuration Register* 0x02 Memory Size Register* 0x04 External Control Signal Register 0 0x06 External Control Signal Register 1* 0x08 Auxiliary Output Register 0* 0x0A DAQ Sync Register* 0x0C ADC Register Group Control Register 0 0x10 Control Register 1 0x12 (both ADC and DAC) Calibration Control Register* 0x14 Sample Interval Register (LOW) 0x16 Sample Interval Register (HIGH) 0x18 Delay Interval Register (LOW) 0x1A Delay Interval Register (HIGH) 0x1C Sample/Scan Count Register (LOW) 0x1E Sample/Scan Count Register (HIGH) 0x20 DAQ Soft Start Command 0x22 DAQ Single Conversion Command 0x24 QUEUE FIFO pointer clear command 0x26 QUEUE load command 0x28 ADC FIFO pointer clear command 0x2A QUEUE High register 0x2C DAC register Group Control Register 0* 0x50 Control Register 1* 0x52 Sample Interval Register (LOW)* 0x54 Sample Interval Register (HIGH)* 0x56 DAC Select register* 0x60 DAC Soft Start command* 0x64 DAC FIFO pointer clear command* 0x66 DAC Single Conversion Command* 0x70:7E * these registers contain some control bits specific only to boards with D/A s. For boards without D/A s, these control bits become don t cares. 1

3 16 Bit Read only registers Register Name Hardware Status Register* PIPE1 Read Register ADC Read Pointer Register ADC Write Pointer Register User XFER Counter Register (lower) User XFER Counter Register (upper) Offset Address 0x00 0x04 0x08 0x0C 0x10 0x14 16 Bit FIFOs (read/write) Register Name QUEUE FIFO ADC FIFO DAC FIFO* Offset Address 0x100 0x200 0x300 8 Bit Registers Register Name Register Name Offset Addresses Read/Write Access Peripheral Devices Device 0 chip select 0x00 0x07 Read/Write access Device 1 chip select 0x08 0x0F Read/Write access Device 2 chip select 0x10 0x17 Read/Write access Device 3 chip select 0x18 0x1F Read/Write access Digital I/O Direction Register 0x40 Read/Write access Data Register 0x48 Read/Write access User Counters Configuration Register 0x50 Write access only * these registers contain some control bits specific only to boards with D/A s. For boards without D/A s, these control bits become don t cares. 2

4 STC Register Descriptions Interrupt Enable Register - 0x00 OVERRUN UNDERRUN X X DAC_ACTIVE DAQ_STOP DAQ_ACTIVE X DACDONE DAC_IENB 0 DAC_ISRC DAQDONE DAQ_IENB DAQ_ISRC1 DAQ_ISRC0 15 OVERRUN DAQ Overrun Enable If this bit is set a DAQ overrun condition can be detected. DAQ overrun does not cause an interrupt but does set a bit in the Status register. 14 UNDERRUN DAC Underrun Enable If this bit is set a DAC underrun condition can be detected. DAC underrun does not cause an interrupt but does set a bit in the Status register. 11 DAC_ACTIVE DAC ACTIVE Interrupt Enable If this bit is set an interrupt will be generated when the DAC waveform circuitry is active. 10 DAQ_STOP DAQ STOP Interrupt Enable If this bit is set an interrupt will be generated when the stop trigger (TRIG2) is detected. 9 DAQ_ACTIVE DAQ ACTIVE Interrupt Enable If this bit is set an interrupt will be generated when a DAQ sequence is active. 7 DACDONE DACDONE Interrupt Enable If this bit is set an interrupt will be generated when the DAC sequence completes. A DAC sequence ends by running its course or when an UNDERRUN condition occurs. 6 DAC_IENB DAC Interrupt Enable If this bit is set then one of the DAC_ISRC conditions will generate an interrupt. 5-4 DAC_ISRC DAC Interrupt Source select These bits are used to select an additional DAC interrupt source, in addition to the DACDONE source. If bit is clear, interrupt comes from DAC FIFO ¼ Empty. If bit is set, interrupt comes from DAC High Channel. 3 DAQDONE DAQDONE Interrupt Enable If this bit is set an interrupt will be generated when the DAQ sequence completes. A DAQ sequence ends by running its course or when an OVERRUN condition occurs. 2 DAQ_IENB DAQ Interrupt Enable If this bit is set then one of the DAQ_ISRC conditions will generate an interrupt. 1-0 DAQ_ISRC(1:0) DAQ Interrupt Source select These bits are used to select an additional DAQ interrupt source, in addition to the DAQDONE source. DAQ_ISRC1 DAQ_ISRC0 Description 0 0 DAQ FIFO ¼ Full 0 1 DAQ Single Conversion: An interrupt is generated each conversion. Single Conversion Command: An interrupt can be generated by a Single Conversion Command when the corresponding ADC data is available in the PIPE1 Read Register. Paced Conversions: An interrupt can be generated each ADC conversion during paced conversions when the corresponding ADC data is available in the AFIFO. 1 0 DAQ EOSCAN: During multi-channel scans, an interrupt is generated after the last channel in the external queue memory or last channel of the internak queue counter has been captured. 1 1 DAQ EOSEQ: During multi-channel scans, an interrupt is generated after each interval delay. 3

5 Hardware Configuration Register 0x02 DMACH_SEL SLOW_DAC EXT_QUE X X X BRDTYPE1 BRDTYPE0 15 DMACH_SEL DMA Channel Select. The DMA Channel select signal is used to select which PLX9080 DMA Controllers (0 or 1) will be dedicated to the DAQ or DAC functions. If this bit is cleared then DMA Channel 0 and 1 are allocated to the DAQ and DAC functions respectively. If this bit is set then DMA Channel 0 and 1 are allocated to the DAC and DAQ functions respectively. 10 SLOW_DAC Slow DAC select. The SLOW_DAC bit controls the write access time to the DAC devices. When this bit is set the write access time is extended to access slow DAC devices (225ns DACREGLD(1:0) strobes). For high speed DAC applications where a fast write access (50ns DACREGLD(1:0) strobes) can be tolerated the SLOW_DAC bit should not be set. Board Specific Settings PCI-DAS PCI-DAS6034 na 9 EXT_QUE External QUEUE select. If this bit is cleared then an internal Channel queue counter is used to sequence through the channels. If this bit is set then the external queue is enabled in off-chip RAM memory. 1-0 BRDTYPE(1:0) These bit are used to specify boards that require special functions in the STC. Board Specific Settings PCI-DAS PCI-DAS Memory Size Register - 0x04 DSEG7 DSEG6 DSEG5 DSEG4 DSEG3 DSEG2 DSEG1 DSEG0 X ASEG6 ASEG5 ASEG4 ASEG3 ASEG2 ASEG1 ASEG DSEG(7:0) DAC buffer segment size(¼ FIFO size):the ¼ FIFO size can range from 256 samples deep upwards to 16K samples deep. 6-0 ASEG(6:0) ADC buffer segment size(¼ FIFO size):the ¼ FIFO size can range from 256 samples deep upwards to 8K samples deep. ASEG(6:0) ¼ FIFO Size FIFO size 7F 256 1K 7E 512 2K 7C 1K 4K 78 2K 8K DSEG(7:0) ¼ FIFO FIFO size Size FF 256 1K FE 512 2K FC 1K 4K F8 2K 8K F0 4K 16K 4

6 External Control Signal Register 0 (write only) 0x06 D15 D14 D13 D12 D11 D10 D9 D8 ADC_ExtGate_S2 ADC_ExtGate_S1 ADC_ExtGate_S0 ADC_ ExtStop _S2 ADC_ ExtStop _S1 ADC_ExtStop_S0 ADC_ ExtStart _S2 ADC_ ExtStart _S1 D7 D6 D5 D4 D3 D2 D1 D0 ADC_ExtStart_S0 ADC_ExtTimeBase_Pol ADC_ExtTimeBase_S2 ADC_ExtTimeBase_S1 ADC_ExtTimeBase _S0 ADC_ExtConv_S2 ADC_ExtConv_S1 ADC_ExtConv_S0 ADC_ExtConv_S<2:0>: Bits: 2:0 ADC_ExtTimeBase_S<2:0>: Bits: 5:3 ADC_ExtTimeBase_Pol: Bit 6 ADC_ExtStart_S<2:0>: Bits: 9:7 ADC_ExtStop_S<2:0>: Bits: 12:10 ADC External Convert source select bits: ADC_ExtConv_S2 ADC_ExtConv_S1 ADC_ExtConv_S0 Source AUXIN0* AUXIN AUXIN AUXIN AUXIN AUXIN DS A/D Convert * Denotes power-on/reset selection ADC External Time Base source select bits: ADC_ExtTimeBase_S2 ADC_ ExtTimeBase _S1 ADC_ ExtTimeBase _S0 Source AUXIN0 * AUXIN AUXIN AUXIN AUXIN AUXIN5 * Denotes power-on/reset selection ADC External Time Base Polarity selection: 0=rising edge, 1=failling edge ADC External Start Trigger source select bits: ADC_Start_S2 ADC_Start_S1 ADC_Start_S0 Source AUXIN AUXIN1* AUXIN AUXIN AUXIN AUXIN DS A/D START TRIGGER * Denotes power-on/reset selection ADC External Stop Trigger source select bits: ADC_ExtStop_S2 ADC_ExtStop_S1 ADC_ExtStop_S0 Source AUXIN AUXIN AUXIN2* AUXIN AUXIN AUXIN DS A/D STOP TRIGGER * Denotes power-on/reset selection 5

7 ADC_ExtGate_S<2:0>: Bits: 15:13 ADC External Gate source select bits: ADC_ExtGate_S2 ADC_ExtGate_S1 ADC_ExtGate_S0 Source AUXIN AUXIN AUXIN AUXIN AUXIN AUXIN5* * Denotes power-on/reset selection External Control Signal Register 1 (write only) 0x08 D15 D14 D13 D12 D11 D10 D9 D8 X X X X X X DAC_ExtTimeBase_Pol DAC_ExtTimeBase_S2 D7 D6 D5 D4 D3 D2 D1 D0 DAC_ExtTimeBase_S1 DAC_ExtTimeBase_S0 DAC_ExtUpd_S2 DAC_ ExtUpd_S1 DAC_ ExtUpd _S0 DAC_ExtStart_S2 DAC_ ExtStart _S1 DAC_ ExtStart _S0 DAC_ExtStart_S<2:0>: Bits: 2:0 DAC External Start source select bits: DAC_Start_S2 DAC_Start_S1 DAC_Start_S0 Source AUXIN AUXIN AUXIN AUXIN AUXIN4* AUXIN DS D/A START * Denotes power-on/reset selection DAC_ExtUpd_S<2:0>: Bits: 5:3 DAC External Update source select bits: DAC_ExtUpd_S2 DaC_ ExtUpd _S1 DAC_ ExtUpd _S0 Source AUXIN AUXIN AUXIN AUXIN3* AUXIN AUXIN DS D/A UPDATE * Denotes power-on/reset selection DAC_ ExtTimeBase _S<2:0>: Bits: 8:6 DAC_ExtTimeBase_Pol: Bit 9 DAC External Time Base source select bits: DAC_ExtTimeBase_S2 DAC_ ExtTimeBase _S1 DAC_ ExtTimeBase _S0 Source AUXIN AUXIN AUXIN AUXIN3* AUXIN AUXIN5 * Denotes power-on/reset selection DAC External Time Base Polarity selection: 0=rising edge, 1=failling edge 6

8 AUXOUT Register (write only) 0x0A D15 D14 D13 D12 D11 D10 D9 D8 0 AUXOUT2_POL AUXOUT2_S3 AUXOUT2_S2 AUXOUT2_S1 AUXOUT2_S0 AUXOUT1_POL AUXOUT1_S3 D7 D6 D5 D4 D3 D1 D1 D0 AUXOUT1_S2 AUXOUT1_S1 AUXOUT1_S0 AUXOUT0_POL AUXOUT0_S3 AUXOUT0_S2 AUXOUT0_S1 AUXOUT0_S0 AUXOUT0_S<3:0>: Bits: 3:0 AUXOUT0_POL: Bit: 4 AUXOUT1_S<3:0>: Bits: 8:5 AUXOUT1_POL: Bit: 9 AUXOUT0 source select bits: S3 S2 S1 S0 Source DAC_Update* ADC_Stop ADC_Convert Scanclk CTR1_Src SSH Startscan CTR2_Src ADC_Start_Trig ADC_Stop_Trig DAC_Start_Trig GND 1 1 x x GND * Denotes power-on/reset selection Sets polarity of selected AUXOUT0 source. 0 = non inverted 1= inverted. Default=0. AUXOUT1 source select bits: S3 S2 S1 S0 Source DAC_Update ADC_Stop ADC_Convert* Scanclk CTR1_Src SSH Startscan CTR2_Src ADC_Start_Trig ADC_Stop_Trig DAC_Start_Trig GND 1 1 x x GND * Denotes power-on/reset selection Sets polarity of selected AUXOUT1 source. 0 = non inverted 1= inverted. Default=0. 7

9 AUXOUT2_S<3:0>: Bits: 13:10 AUXOUT2_POL: Bit: 14 AUXOUT2 source select bits: S3 S2 S1 S0 Source DAC_Update ADC_Stop ADC_Convert Scanclk* CTR1_Src SSH Startscan CTR2_Src ADC_Start_Trig ADC_Stop_Trig DAC_Start_Trig GND 1 1 x x GND * Denotes power-on/reset selection Sets polarity of selected AUXOUT2 source. 0 = non inverted 1= inverted. Default=0. 8

10 DAQ_SYNC Register (write only) 0x0C D15 D14 D13 D12 D11 D10 D9 D8 X X X X X X DAC_TIMEBASE_SEL ADC_TIMEBASE_SEL D7 D6 D5 D4 D3 D2 D1 D0 x Clk_Src_1 Clk_Src_0 D/A_Upd_MS D/A_Start_MS A/D_Stop_MS A/D_Start_M/S A/D_Conv_M/S Notes: 1. DS = DAQ-Sync. 2. Power-on reset value of all bits is 0 3. To use a DAQ-Sync signal as a slave, you must also select it as the source in the appropriate External Control Signal register A/D_Conv_M/S: Bit: 0 Selects direction of DS A/D CONVERT. 0 = Slave (input) 1 = Master (output) A/D_Start_M/S: Bit: 1 Selects direction of DS A/D START TRIGGER. 0 = Slave (input) 1 = Master (output) A/D_Stop_M/S: Bit: 2 Selects direction of DS A/D STOP TRIGGER. 0 = Slave (input) 1 = Master (output) D/A_Start_M/S: Bit: 3 Selects direction of DS D/A START TRIGGER. 0 = Slave (input) 1 = Master (output) D/A_Upd_M/S: Bit: 4 Selects direction of DS D/A UPDATE. 0 = Slave (input) 1 = Master (output) Clk_Src(1:0): Bits: 5,6 Clk_Src_1 Clk_Src_0 Mode 0 0 Board uses STC 40MHz clock signal. 0 1 Board uses DS 40MHz clock signal. 1 0 Board uses STC 40MHz clock signal and sources this signal to DS bus. 1 1 Invalid option. ADC_TIMEBASE_SEL: Bit: 8 ADC Time Base Select - When ADC_TIMEBASE_SEL is cleared, the internal clock is used as the time base for the ADC interval counter. - When ADC_TIMEBASE_SEL is set, the ADC external clock is used as the time base for the ADC interval counter. DAC_TIMEBASE_SEL: Bit: 9 DAC Time Base Select - When DAC_TIMEBASE_SEL is cleared, the internal clock is used as the time base for the DAC interval counter. - When DAC_TIMEBASE_SEL is set, the DAC external clock is used as the time base for the DAC interval counter. 9

11 DAQ Control Register 0 0x10 DAQ_ENB DAQ_DMA_DISABLE GATE_SEQ SAMPCNT_ENB XCONV_POL TRIG2_STOPTRIG_ENB TRIG2_PRETRIG_ENB TRIG2_POL TRIG2_SRC TRIG1_POL TRIG1_SRC1 TRIG1_SRC0 AGATE_POL AGATE_LVL AGATE_SRC1 AGATE_SRC0 15 DAQ_ENB Data Acquisition Enable This bit enables and disables a data acquisition operation. It is the master enable for DAQ operations. 14 DAQ_DMA_DISABLE Data Acquisition DMA Disable This bit enables (0) and disables (1) the use of DMA for data transfer during a data acquisition operation. 13 GATE_SEQ GATE ON Sequence: If this bit is set in multi-channel mode then an inactive gate will pause the data acquisition after the current scan sequence has completed. If this bit is cleared then an inactive gate will pause the data acquisition immediately. 12 SAMPCNT ENB Sample Counter enable. When this bit is set the DAQ Sample counter in enabled. This bit must be set for prepost triggered mode. 11 XCONV_POL External A/D Convert polarity control. This bit controls the polarity of the External A/D convert input signal. If a low-to-high edge of XCONV is to be used to initiate a conversion then this bit should be cleared. If a high-tolow edge of XCONV is to be used to initiate a conversion then this bit should be set. 10 TRIG2_STOPTRIG_ENB TRIG2 stop-trigger enable. This bit enables stop-trigger mode. Cannot be used with TRIG2_ PRETRIG _ENB 9 TRIG2_PRETRIG_ENB TRIG2 pre-trigger enable. This bit enables pre-trigger mode. Cannot be used with TRIG2_STOPTRIG_ENB 8 TRIG2_POL TRIG2 trigger polarity select: 0 = rising edge trigger; 1 = falling edge trigger. 7 TRIG2_SRC TRIG2 pre-trigger source select: 0 = External X_TRIG2 pin; 1 = Analog Trigger. 6 TRIG1_POL TRIG1 trigger polarity select: 0 = rising edge trigger; 1 = falling edge trigger. 5-4 TRIG1_SRC(1:0) TRIG1 Source select These bits are used to select TRIG1 source. TRIG1_SRC1 TRIG1_SRC0 Description 0 0 Disabled 0 1 Soft_Trigger 1 0 External XTRIG1 1 1 Analog Trigger 3 AGATE_POL AGATE polarity select: 0 = active high gate; 1 = active low gate. 2 AGATE_LVL AGATE Level select; 0 = edge sensitive gate; 1 = level sensitive gate; 1-0 AGATE_SRC(1:0) AGATE Source select These bits are used to select AGATE source. AGATE_SRC1 AGATE_SRC0 Description 0 0 Disabled 0 1 Soft_Gate 1 0 External AGATE 1 1 Analog Gate 10

12 DAQ Control Register 1 0x12 MODE3 MODE2 MODE1 MODE0 RETRIGGER ATRIG_SRC DITHER_EN 0 MODE 0 SFT_AGATE EOC_POL CONV_POL ATRIGMD2 ATRIGMD1 ATRIGMD0 QUECFG MODE(3:0) DAQ MODE select bits. Mode 3 Mode 2 Mode 1 Mode 0 Single or Multi chan. Interval Delay External Convert Description Single Single Channel mode, internal convert clock Not Supported x Not Supported Multi. Multi Channel mode, internal convert clock Not Supported x Not Supported Multi. Yes Multi Channel, internal convert clock with programmable interval delay mode. The resolution of both the sample & delay intervals = 25ns Not Supported x Not Supported Single Yes Single Channel with external convert clock Multi. Yes Multi Channel mode with external convert clock x Not Supported 11 RETRIGGER MODE Retrigger Mode: 0= RETRIGGER MODE DISABLED, 1= RETRIGGER MODE ENABLED Retrigger mode is used in multi-channel modes to allow the scan to be repeated each time the retrigger (TRIG1) is asserted. 10 ATRIG_SRC Analog Trigger Source - When ATRIG_SRC is cleared, the external analog trigger (from the Aux0) is the analog trigger source. When ATRIG_SRC is set, the 1 st channel in the scan after gain is applied is the analog trigger source. This only pertains to boards that support analog triggering. 9 DITHER_EN Dither Enable - When DITHER_EN is cleared, no noise is added to the analog signal. When DITHER_EN is set, ~1/2 rms of random noise is added to the analog signal. This only pertains to boards that support dither. 6 SFT_GATE Software DAQ Gate - When SFT_GATE is cleared, no A/D conversions take place. When SFT_GATE is set, A/D conversions take place normally. SFT_GATE can be used as a software gating tool, or to inhibit random conversions during setup operations. 5 EOC_POL ADC EOC polarity control. This bit controls the polarity of the EOC ADC input signal. If a low-to-high edge of EOC signifies ADC data is ready then this bit should be cleared. If a high-to-low edge of EOC signifies ADC data is ready then this bit should be set. Board Specific Settings PCI-DAS PCI-DAS CONV_POL ADC Convert output polarity control. This bit controls the polarity of the ADC convert pulse to the ADC. If a low going pulse is desired this bit should be cleared. If a high going pulse is desired then this bit should be set. Board Specific Settings PCI-DAS PCI-DAS ATRIGMD(2:0) Analog Trigger/Gate Mode select bits. These bits only pertain to boards that support analog triggering 11

13 Analog Trigger/Gate Modes ATRIGMD2 ATRIGMD1 ATRIGMD0 Mode Description INACTIVE Inactive state. Prior to programming the analog trigger to the desired state the analog trigger should be programmed to the inactive state to clear out the trigger circuitry Positive Hysteresis The trigger is generated when the signal value is greater than the high-value, with hysteresis specified by low_value Negative Hysteresis The trigger is generated when the signal value is greater than the low-value, with hysteresis specified by high_value Low Threshold DAC The trigger/gate is generated with respect to the Low Threshold DAC setting High Threshold DAC The trigger/gate is generated with respect to the Low Threshold DAC setting Window The trigger is generated when the signal value is between the low-value and high-value. 0 QUECFG QUEUE Configuration select QUECFG = 0: Used for boards with 16-SE/8-DIFF. Channels. QUECFG = 1: Used for boards with greater than 16-SE/8-DIFF channels. Board Specific Settings PCI-DAS PCI-DAS Calibration/SPI Register 0x14 x x x x CAL_GAIN/OFFSETN SELCALFPGA CALENB GEN_SCLK SDI CSRC3 CSRC2 CSRC1 CSRC0 SEL_SPI2 SEL1590N SEL8800N for a board specific settings see that board s calibration document 10 CAL_GAIN/OFFSETN Used to select calibration value written for range. If set, writing gain. If clear writing offset. 10 SELCALFPGA Used to select the calibration FPGA. 9 CALENB Calibration Enable: 0 = disabled; 1 = enabled. 8 GEN_SCLK Generate SCLK. If this bit is set the SCLK pin is pulsed to clock the current value of the SDI pin into the selected bit serial device. 7 SDI Serial Data In signal. This signal is used in conjunction with SCLK to serially shift data into the ADC and DAC calibration devices. 6-3 CSRC(3:0) Calibration source select: 2 SEL_SPI2 General purpose user Bit port. This bit is cleared at reset. 1 SEL1590N Used to chip select for the ltc1590 device. When this bit is set the SEL1590N signal is low. This bit is cleared at reset. 0 SEL8800N Used to chip select for the 8800 device. When this bit is set the SEL8800N signal is low. This bit is cleared at reset. ADC Sample Interval Register (Lower) 0x16 ADCSIL15 ADCSIL14 ADCSIL13 ADCSIL12 ADCSIL11 ADCSIL10 ADCSIL9 ADCSIL8 ADCSIL7 ADCSIL6 ADCSIL5 ADCSIL4 ADCSIL3 ADCSIL2 ADCSIL1 ADCSIL ADCSIL(15:0) ADC Sample Interval lower - The lower 16 bits of the Sample Interval divisor. 12

14 ADC Sample Interval Register (Upper) 0x18 ADCSIL23 ADCSIL22 ADCSIL21 ADCSIL20 ADCSIL19 ADCSIL18 ADCSIL17 ADCSIL ADCSIL(23:16) ADC Sample Interval upper - The upper 8 bits of the Sample Interval divisor. ADC Pacer Frequency = Base_clock/(Divider + 3) ADC Delay Interval Register (Lower) 0x1A ADCDIL15 ADCDIL14 ADCDIL13 ADCDIL12 ADCDIL11 ADCDIL10 ADCDIL9 ADCDIL8 ADCDIL7 ADCDIL6 ADCDIL5 ADCDIL4 ADCDIL3 ADCDIL2 ADCDIL1 ADCDIL ADCDIL(15:0) ADC Delay Interval lower - The lower 16 bits of the Sample Delay divisor. ADC Delay Interval Register (Upper) 0x1C ADCDIL23 ADCDIL22 ADCDIL21 ADCDIL20 ADCDIL19 ADCDIL18 ADCDIL17 ADCDIL ADCDIL(23:16) ADC Delay Interval upper - The upper 8 bits of the Sample Delay divisor. ADC Sample/Scan Count Register (Lower) 0x1E ADCSMP15 ADCSMP14 ADCSMP13 ADCSMP12 ADCSMP11 ADCSMP10 ADCSMP9 ADCSMP8 ADCSMP7 ADCSMP6 ADCSMP5 ADCSMP4 ADCSMP3 ADCSMP2 ADCSMP1 ADCSMP ADCSMP(15:0) ADC Sample Count lower - The lower 16 bits of the Sample Counter. Note: The sample counter must always be loaded with a value other than zero prior to enabling a DAQ sequence. This holds true even when the sample counter is disabled via the SAMPCNT_ENB bit in the DAQ Control 0 register. 13

15 ADC Sample/Scan Count Register (Upper) 0x ADCSMP23 ADCSMP22 ADCSMP21 ADCSMP20 ADCSMP19 ADCSMP18 ADCSMP17 ADCSMP ADCSMP(23:16) ADC Sample Count upper - The upper 8 bits of the Sample Counter. DAQ Start Register 0x Don t care Accessing the DAQ Start Register location initiates a multiple A/D conversion data acquisition operation. To trigger the board with the Start DAQ register the TRIG1_SRC(1:0) bits need to select the soft-trigger source. Otherwise strobing the DAQ Start register has no effect. DAQ Single Conversion Register 0x Don t care Prior to issuing a DAQ Single Conversion command the Queue load register should be accessed to select the desired channel, gain & mode (S.E./DIFF., UNI/BIP). Accessing the Single Conversion Register location initiates a single A/D conversion. The actual ADC value can be retrieved via the PIPE1 Read register. Queue pointer clear Register 0x Don t care Accessing the Queue pointer clear register resets the Q pointer to home state. 14

16 Queue Load Register 0x28 EOSCAN EOSEQ NRSE DIFFSEN UNIBIPN GSEL2 GSEL1 GSEL0 CHSEL7 CHSEL6 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 refer to your board s specifications for valid ranges and channel count 15 EOSCAN End-Of-Scan flag. When the EOSCAN flag is reached, the circuitry stops and waits the programmable delay interval before sequencing back to the top of the channel sequence list. 14 EOSEQ End-Of-Sequence. When the EOSEQ flag is reached, the circuitry stops and waits the programmable delay interval before sequencing to the start of the next channel sequence in the list. 13 NRSE Non Referenced Single-ended. When the NRSE bit is clear, the minus input is connected to analog ground. When the NRSE bit is set, the minus input is connected to the AISENSE input on the connector. 12 DIFFSEN Channel Single-Ended/Differential - This bit configures the analog input section for single-ended or differential mode. 1 = differential, 0 = single-ended. 11 UNIBIPN Channel Unipolar/Bipolar - This bit configures the ADC for unipolar or bipolar mode.. 0 = bipolar, 1 = unipolar GSEL(2:0) Channel Gain Select - These three bits control the gain settings of the input PGIA for the selected channel. Range UNIBIPN GSEL2 GSEL1 GSEL0 +/- 10V /- 5V /- 2/2.5V /- 1/1.25V /- 0.5V /- 0.2/0.25V /- 0.1V /- 0.05V V V /2.5V /1.25V V /.25V V CHSEL(7:0) Input Channel Select - These eight bits control the input multiplexer address setting for selecting the analog input channel routed to the ADC When the internal queue counter is used to sequence through the channels the Channel High register must be initialized with the desired high channel to be scanned prior to accessing the Queue Load register. The Queue Load register needs to be accessed prior to issuing an A/D convert for the 1 st time to prime the Queue holding register. When the external RAM queue is used to sequence through the channels the external queue should be programmed prior to accessing the Queue Load register. The external queue bit fields match the fields in the Queue load register. The Queue Load register needs to be accessed prior to issuing an A/D convert for the 1 st time to prime the Queue holding register. With an external Queue the data is a don t care and does not have to match the 1 st scan entry in the sequence list. The following table details the channel select decoding: QUECFG DIFFSEN CHSEL[7: 4] CHSEL3 CHSEL(2:0) Description 0 1 x 0 V 8 DIFF Chan. 0 0 x 0 V 16 SE Low Chan. 0 0 x 1 V 16 SE High Chan. X= don t care; V= variable.; (DIFFSEN and CHSEL(4:0) bits reside in the QUEUE Load register). 15

17 ADC buffer pointer clear Register 0x2A 15-0 Don t care Accessing the ADC buffer pointer clear register resets the pointer to home state, and clears the internal STC pipeline registers (PIPE1 and PIPE0). Queue High Register 0x2C CHSEL7 CHSEL6 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 7-0 CHSEL(7:0) High channel select address. When the internal queue counter is used to sequence through the channels this register must be initialized with the high channel address. Once the high channel has been converted then the queue counter is re-loaded with the low channel address. DAC Control Register 0 0x50 DAC_ENB CYCLESTOP 0 0 WFM_MD XUPD_POL XUPD_ENB WTRIGSRC1 WTRIGSRC0 WTRIG_POL WGATE_LVL WGATE_ENB WGATE_SRC 15 DAC_ENB DAC Enable - Enable the DAC controller. 14 CYCLESTOP Cyclic Stop enable - This bit controls how a DAC cyclic sequence terminates. If this bit is cleared then DAC cyclic waveform generation terminates after the next update completes. If this bit is set the DAC cyclic waveform generator terminates cleanly and will halt when the next end of buffer is encountered. 8 WFM_MD DAC waveform mode select: Clearing this bit selects posted non cyclic mode. Setting this bit selects continuous cyclic mode. 7 XUPD_POL External D/A Update polarity control.this bit controls the polarityof the external D/A update input signal. If a low-to-high edge of XUPDATE is to be used to initiate an update then this bit should be cleared. If a high-to-low edge of XUPDATE is to be used to initiate an update then this bit should be set. 6 XUPD_ENB External D/A Update Enable. This bit enables the external XUPDATE signal as the DAC pacer source. 5-4 WTRIGSRC(1:0) Waveform TRIG Source Select: These bits are used to select the Waveform trigger source. 16

18 WTRIG_SRC1 WTRIG_SRC0 Description 0 0 Disabled 0 1 Soft_Trigger 1 0 External WTRIG 1 1 ADC Trig1 3 WTRIG_POL WTRIG trigger polarity select: 0 = rising edge trigger; 1 = falling edge trigger. 2 WGATE_LVL WGATE Level select; 0 = edge sensitive gate; 1 = level sensitive gate. 1 WGATE_ENB WGATE Enable; 0 = disabled, 1 = enabled. 0 WGATE_SRC WGATE source; 0 = External WTRIG; 1 = Soft_gate. DAC Control Register 1 0x52 X X X X DAC_WRITE_POL X DAC1REF_SEL DAC0REF_SEL DAC_OE DAC_UPDATE_POL SFT_WGATE 0 DAC1_UNIBIPN X DAC0_UNIBIPN X 11 DAC_WRITE_POL DAC Write Polarity When DAC_WRITE_POL is set to 0, the DAC_WRITE signal is active low. When DAC_WRITE_POL is set to 1, the DAC_WRITE signal is active high. The DAC_WRITE signal latches the data in the first buffer of a double buffered DAC Board Specific Settings PCI-DAS PCI-DAS6034 na 9 DAC1REF_SEL DAC 1 Reference Select When DAC1REF_SEL is set to 0, the onboard reference is used for DAC 1. When DAC1REF_SEL is set to 1, the external DAC reference is used for DAC 1. 8 DAC0REF_SEL DAC 0 Reference Select When DAC0REF_SEL is set to 0, the onboard reference is used for DAC 0. When DAC0REF_SEL is set to 1, the external DAC reference is used for DAC 0. 7 DAC_OE DAC Output Enable When this bit is set to 0 the DAC outputs go to ~0v. When this bit is set to 1, the DAC outputs go to there previously defined state. 6 DAC_UPDATE_POL DAC Update Polarity When DAC_UPDATE_POL is set to 0, the DAC_UPDATE signal is active low. When DAC_UPDATE_POL is set to 1, the DAC_UPDATE signal is active high. The DAC_UPDATE signal latches the data in the second buffer of a double buffered DAC. Board Specific Settings PCI-DAS PCI-DAS6034 na 5 SFT_WGATE Software gate for the DACs. Only valid if WGATE_ENB and WGATE_SRC is set. Clearing this bit gates off the DAC output. Setting this bit gates on the DAC outputs 3 DAC1_UNIBIPN DAC1 Unipolar/Bipolarn configuration bit. When is set to 0, DAC1 is configured in BIPOLAR mode. When set to 1, DAC1 is configured in UNIPOLAR mode. 1 DAC0_UNIBIPN DAC0 Unipolar/Bipolarn configuration bit. When is set to 0, DAC0 is configured in BIPOLAR mode. When set to 1, DAC0 is configured in UNIPOLAR mode. DAC Sample Interval Register (Lower) 0x54 DACSIL15 DACSIL14 DACSIL13 DACSIL12 DACSIL11 DACSIL10 DACSIL9 DACSIL8 DACSIL7 DACSIL6 DACSIL5 DACSIL4 DACSIL3 DACSIL2 DACSIL1 DACSIL DACSIL(15:0) DAC Sample Interval lower - The lower 16 bits of the Sample Interval divisor. DAC Pacer Frequency = Base_clock/(Divider + 2) 17

19 DAC Sample Interval Register (Upper) 0x DACSIL23 DACSIL22 DACSIL21 DACSIL20 DACSIL19 DACSIL18 DACSIL17 DACSIL DACSIL(23:16) DAC Sample Interval upper - The upper 8 bits of the Sample Interval divisor. DAC Select register 0x60 DACHI DACLO 5-3 DACHI DAC High Channel Select bit. This bit is used to select the high channel during a multi-channel DAC scan operation. 2-0 DACLO DAC Low Channel Select bit. This bit is used to select the low channel during a multi-channel DAC scan operation. Note: The DAC High channel must be greater than or equal to the DAC Low channel. DAC Start Register 0x Don t care Accessing the DAC Start Register location initiates a multiple D/A conversion waveform generation operation. To trigger the board with the Start DAC register the WTRIG_SRC(1:0) bits need to select the soft-trigger source. Otherwise strobing the DAC Start register has no effect. DAC buffer pointer clear Register 0x Don t care Accessing the DAC buffer pointer clear register resets the pointer to home state. 18

20 DAC Single Conversion Registers (a total of 8 registers at address offset range 0x70:0x7E) 15-0 Don t care Accessing the Single Conversion Register location initiates a single D/A conversion. The DAC channel is selected via the address offset. READ ONLY 16-BIT REGISTER Hardware Status Register 0x00 REV3 REV2 REV1 REV0 PIPEFULL1 PIPEFULL0 TRIG2_FLG 0 DAQDONE DACDONE ASRC_FLG DSRC_FLG DAQ_ACTIVE DAC_ACTIVE DAQ_OVERRUN DAC_UNDERRUN REV(3:0) REV Control Field: This document supports hardware revision PIPEFULL(1:0) STC PIPE FULL status: The STC contains two internal pipe line registers in the DAQ data path. At the completion of a DAQ operation these two pipeline registers may contain residual ADC data. The PIPEFULL(1:0) bits provides status on which pipe register contains vaild data. 9 TRIG2_FLG If this bit is set then a DAQ stop trigger interrupt is pending. 7 DAQDONE If this bit is set then the current DAQ operation has completed. If the DAQDONE interrupt was enabled then it is pending. 6 DACDONE If this bit is set then the current DAC operation has completed. If the DAQDONE interrupt was enabled then it is pending. 5 ASRC_FLG If this bit is set then one of the DAQ interrupt sources (DAQ_ISRC(1:0) field in the Interrupt Enable Register) is pending. This bit can also be polled to determine the ADC_BUSY status after a Single Covert Command has been issued. 4 DSRC_FLG If this bit is set then one of the DAC interrupt sources (DAC_ISRC(1:0) field in the Interrupt Enable Register) is pending. 3 DAQ_ACTIVE If this bit is set then the current DAQ operation is active. 2 DAC_ACTIVE If this bit is set then the current DAC operation is active. 1 DAQ_OVERRUN If this bit is set then an overrun error was detected during the previous DAQ operation. 0 DAC_UNDERRUN If this bit is set then an underrun error was detected during the previous DAC operation. All pendinding interrupts sourced by the STCs interrupt control logic are serviced by reading the Hardware Status Register. PIPE1 Read Register - 0x04 PIPE15 PIPE14 PIPE13 PIPE12 PIPE11 PIPE10 PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE PIPE(15:0) PIPE 1 Register data. This register is read to retrieve the contents of the internal PIPE1 and PIPE 1 registers. After the 1 st PIPE1 read has completed if data is available in the PIPE0 register it will automatically be shifted into the PIPE1 register. 19

21 ADC Read Pointer Register 0x08 0 ARPNTR14 ARPNTR13 ARPNTR12 ARPNTR11 ARPNTR10 ARPNTR9 ARPNTR8 ARPNTR7 ARPNTR6 ARPNTR5 ARPNTR4 ARPNTR3 ARPNTR2 ARPNTR1 ARPNTR ARPNTR(14:0) The Lower ADC Read pointer data. The overall ADC Read pointer is a 17-bit address. This register provides the lower 15-bits. Reference the Upper User Transfer Counter for the remaining upper two bits. ADC Write Pointer Register 0x0C 0 AWPNTR14 AWPNTR13 AWPNTR12 AWPNTR11 AWPNTR10 AWPNTR9 AWPNTR8 AWPNTR7 AWPNTR6 AWPNTR5 AWPNTR4 AWPNTR3 AWPNTR2 AWPNTR1 AWPNTR AWPNTR(14:0) The Lower ADC Write pointer data. The overall ADC Write pointer is a 17-bit address. This register provides the lower 15-bits. Reference the Upper User Transfer Counter for the remaining upper two bits. Lower User Transfer Counter Register 0x10 XFERCNT15 XFERCNT14 XFERCNT13 XFERCNT12 XFERCNT11 XFERCNT10 XFERCNT9 XFERCNT8 XFERCNT7 XFERCNT6 XFERCNT5 XFERCNT4 XFERCNT3 XFERCNT2 XFERCNT1 XFERCNT XFERCNT(15:0) Lower User Transfer counter data. The overall User Transfer Counter is a 21-bit address. This register provides the lower 16-bits. Reference the Upper User Transfer Counter for the remaining upper 6-bits. Upper User Transfer Counter Register 0x14 AWPNTR16 AWPNTR15 ARPNTR16 ARPNTR CHAIN_FLG1 CHAIN_FLG2 XFERCNT21 XFERCNT20 XFERCNT19 XFERCNT18 XFERCNT17 XFERCNT AWPNTR(16:15) Upper ADC Write Pointer bits. These bits are grey scale encoded and should be remapped prior to being used to determine the final ADC Write pointer address. Remap as follows: 20

22 Register Value AWPNTR(16:15) Re-mapped Value AWPNTR(16:15) ARPNTR(16:15) Upper ADC Read Pointer bits. These bits are grey scale encoded and should be remapped prior to being used to determine the final ADC Write pointer address. Re-map as follows: Register Value ARPNTR(16:15) Re-mapped Value ARPNTR(16:15) CHAIN_FLG(1:0) Chain Flag bits. These bits are used to help determine what scatter-gather chain entry data was last DMA transferred to. These bits can be compared to the LAD(4:3) bits programmed in the DMA Channel Local Address register to guarantee that the correct final chain entry has been located. 16-BIT FIFO REGISTERS Queue FIFO Register (Read/Write access) 0x100 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D D(15:0) Queue FIFO: The QFIFO is accessed via this register. Note that the QFIFO can only be accessed if the EXT_QUE bit in the Hardware Configuration register has been set. ADC FIFO Register (Read/Write access) 0x200 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D D(15:0) ADC FIFO: The AFIFO is accessed via this register. 21

23 DAC FIFO Register (Read/Write access) 0x300 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D D(15:0) DAC FIFO: The DFIFO is accessed via this register. 8-BIT REGISTERS PCI BADR3, PLX9080 LOCAL SPACE 1 Peripheral Device 0,1,2,3 Chip Selects (Read/Write access) 0x00:0x1F D7 D6 D5 D4 D3 D2 D1 D0 7-0 D(7:0) Each of these Chip select windows provide read/write access to 8 sequential 8-bit addresses. The User address (A(2:0)),addresses CS0 for 8255 CS1 for 8254 CS2 for Analog Trigger Reference DAC CS3 not used Digital I/O Direction (Read/Write access) - 0x40 D7 D6 D5 D4 D3 D2 D1 D0 7-0 D(7:0) Each of these data bits represents the data direction of the eight digital I/O lines. Clearing a bit makes it s corresponding I/O an input. Setting a bit makes it s corresponding I/O an output. Digital I/O Data (Read/Write access) - 0x48 D7 D6 D5 D4 D3 D2 D1 D0 7-0 D(7:0) Each of these data bits represents the data written to or read from the eight digital I/O lines. User Counter Configuration (Write access) - 0x50 CTR2SRC1 CTR2SRC0 CTR1SRC1 CTR1SRC0 3-2 CTR2SRC(1:0) User Counter 2 clock source select bits: 00=external clock, 01=10MHz internal clock, 10=100kHz internal clock, 11=undefined 1-0 CTR1SRC(1:0) User Counter 1 clock source select bits: 00=external clock, 01=10MHz internal clock, 10=100kHz internal clock, 11=undefined 22

24 Measurement Computing Corporation 16 Commerce Boulevard Middleboro, Massachusetts (508) Fax: (508) RegMap STC 6000 Series.doc