Register Map for the PCI-2500 Series

Transcription

1 Register Map for the PCI-2500 Series Document Revision 1, April, 2007 Copyright 2007, Measurement Computing Corporation

2 Register Description Register level programming should be attempted only by experienced programmers. As an alternative to register level programming, the PCI-2500 Series is fully supported by the Universal Library software as well as most high-level data acquisition and control application packages. The PCI-2500 Series PCI controller (PLX9056) local bus is used in a 16-bit mode for register reads and writes, and in 32-bit mode for DMA operations. Therefore, all of the I/O registers are on word boundaries even though some of them are only 8- bits wide. There are seven bits of addressing used from the PLX 9056 LOCALADDRESS[7:1] the address expressed as though it was [6:0]. On the PCI-2500 Series, the local address bits (7:1) are mapped to address bits (6:0) in the FPGA. The driver multiplies this address by 2 shifting the address from [6:0] to [7:1] as it is written to the address to the local bus of the PLX Bit 0 is assumed to be 0 and is a "don t care." Register Table 1. Major register groups, along with their respective addresses, word counts, and FPGA select signals DIGADR[7:1] Location hex Words W/R FPGA select line Acquisition Acquisition control/status (see Note 1) 00 1 W/R ACQCTLCS Acquisition scan list FIFO 01 1 W/R ACQSLFCS Acquisition pacer clock divisor low, middle, high 02,03,05 3 W ACQPCRCS Acquisition scan counter 04 1 R ACQCNTCS Acquisition trigger count 06 1 R ACQTCTCS PDQ utility register 07 1 W/R expansioninterfacecs Acquisition results FIFO 08 1 R ACQRSFCS Set point FIFO 09 1 W patternfifocs Acquisition results shadow 0A 1 R ACQRSSCS Set point result register 0B 1 R setpointresultselect ADC result 0C 1 R ADCDATCS Local Expansion register 0D 1 W loaclexpansionifcs Variable conversion rate register 0F 1 W vccrcs Analog output Analog Output control/status (see Note 1) 10 1 W/R DACCTLCS Analog Output FIFO 12 1 W DACOFCS Analog Output Pacer CLK Divisor Low 15 1 W dacpacerdivlowcs Analog Output Pacer clock Divisor Mid 17 1 W dacpacerdivmedcs Analog Output Pacer clock Divisor High 11 1 W dacpacerdivhighcs Analog Output Scan counter 0E 1 R DACCNTCS DAC 0 3 Settings 1C,1D,1E,1F 1 W DAC[0:3]CS Digital I/O Digital I/O control/status (see Note 1) 18 1 W/R DIGCTLCS 16 bit Digital I/O 19 1 W/R P3DATACS P Ports A, B, C, control W/R PPICS- Counter/timer Counter-Timer control/status (see Note 1) 40 1 W/R CNTCTLCS Count Registers (0,1,2,3) (see Note 2) 44,45,46,47 4 R CNTDATCS Timer Divisor (0,1) 50,51 2 W TIMERCS Counter/encoder ch1 setup register 28 1 W Wbk17WriteRegCS1 Counter/encoder ch2 setup register 29 1 W Wbk17WriteRegCS2 Counter/encoder ch3 setup register 2A 1 W Wbk17WriteRegCS3 Counter/encoder ch4 setup register 2B 1 W Wbk17WriteRegCS4 Counter/encoder ch1,2 debounce setup 2C 1 W Wbk17WriteRegCS5 2

3 Acquisition 00h overview Register DIGADR[7:1] Location hex Words W/R FPGA select line Counter/encoder ch3,4 debounce setup 2D 1 W Wbk17WriteRegCS6 Counter/encoder counter1 low-high 30,31 2 R Wbk17AcqReadEnable0,1 Counter/encoder counter2 low-high 32,33 2 R Wbk17AcqReadEnable2,3 Counter/encoder counter3 low-high 34,35 2 R Wbk17AcqReadEnable4,5 Counter/encoder counter4 low-high 36,37 2 R Wbk17AcqReadEnable6,7 Miscellaneous DMA control (see Note 1) 58 1 W DMACTLCS Trigger control/status (see Note 2) 59 1 W/R TRGCTLCS Analog trigger DACs 5E 1 W ATRIGCS Calibration EEPROM control 1B 1 W CALCTLCS Calibration Table EEPROM 5C 1 W/R CALTBLCS Digital Mark (see Note 2) 5D 1 W/R DIGMRKCS External clock Divisor 74 1 W ECLKDIV Command Register (performance test) 7B 1 W commandregistercs Configuration data register *test 7C cpldshiftdatacs DWORD count register 7E 1 R readdwordcount Note 1: These registers use sub-decoding so individual bits can be changed without doing read-modify-writes. Note 2: These registers are clear-on-read or at least programmable as such. Acquisition 00h overview Write 00h (Control) Bit # Prepare for acquisition X 0h X Scan List FIFO control X 1h X Acq Pacer clock control X,RI 3h Digital Enhancement control # over samples O E 4h X X 1=Reset Scan List FIFO 1=Read Scan List FIFO En/Dis DAC Pacer also 1=Reset Result FIFO X 1=External, 0=Internal 1=over sample 0=normal 1=Reset config Pipe 1=Start, 0=Stop 1=Enable, 0=Disable 1=start of sample 0=start of scan Set Point control X 5 X 1= Reset Pattern FIFO X X Setpoint FIFO Start X 7 X X X 1= Start Pattern FIFO after write Reset Config Pipe Reset configuration scan list sequencer. Reset before starting an acquisition or after writing the scan list FIFO. Write active high is active for 1 system clock cycle; you don t have to write 0 inactive (only 1 write is necessary). Reset Results FIFO Reset acquisition results FIFO registers and valid data flags. Reset before starting an acquisition. Write active high is active for 1 system clock cycle; you don t have to write 0 inactive (only 1 write is necessary). Reset Scan List FIFO Reset scan list hardware FIFO and state machine logic. Reset before writing the scan list FIFO. Write active high is active for 1 system clock cycle; you don t have to write 0 inactive (only 1 write is necessary). Start/Stop Scan List FIFO Start/Stop data transfers from the Scan List FIFO into the configuration pipe. Must stop SLF to re-load. Set active high after the scan list FIFO is written; set inactive low after the acquisition is stopped (acquisition pacer is disabled). Read Scan List FIFO Force Scan List FIFO into read mode. Subsequent reads of the SLF returns config words (diagnostic) 3

4 Acquisition 00h overview Acquisition pacer clock control Enable/disable the acquisition pacer clock to start acquisition (and, optionally, the DAC pacer clock if bit 2 is set) and program as external or internal pacer clocking bit 1. If using internal pacing, OE = 1 (bit 3) enables the external output driver when unit is driving the external pacer clock. Must be 0 if using external pacing. Bit 8 controls the external pacer-clock polarity. 0 (default) = falling edge. 1 = rising edge. Digital enhancement control: Bit 0: Enables multiple samples of digital channels in a scan. Set this bit to 1 in order to latch digital-in data when analog sample are converted. This allows a digital channel to be in the scan list and get sampled at the same time as the analog channel that precedes it in the scan list. Set this bit to 0 to enable digital inputs to be sampled only at the start of the scan. The power-up default is 0. This parameter does not affect counter channels. Bit 1: Enables analog channel oversampling of analog channels. Set this bit to 1 to enable oversampling a number of times based on bits 15:8 of this same register. Set this bit 0 to sample each channel only once in the scan. The power-up default is 0. The acquisition pacer time must account for 1 µs the number of oversamples for every analog channel in the scan to properly calculate scan time. This is a global setting and affects every analog channel in the scan. Digital channels that follow analog channels in the scan are sampled after the last repeated sample of the analog channel that precedes it. Bits 15:8: This 8-bit field controls the number of oversamples to take when oversampling is enabled (bit 1). The number of oversamples allowed are in powers of 2: 2, 4, 8, 16, 32, 64, 128, and 256. This is because averaging is done in the FPGA and these values allow less logic for the operation. When oversampling, only the averaged value is returned to the PC after the programmed number of samples are averaged for a channel. The entries for this field are as follows. Number of samples Bits 11:8 (hex) Set Point control: Bit 2: Writing a 1 to this bit resets the set point FIFO. You should reset this FIFO if you want to rewrite the set point FIFO after it has been written once. The action resets the write pointer to the set point FIFO. You need not write a 0 to this bit after you write a 1 to reset it because the action of the write is active for 1 clock cycle of the write to the FPGA. Setpoint FIFO Start: Bit 0: This bit should be written once with a 1 after the set point FIFO has been written. It pops the first entry from the set point FIFO, readying the logic to respond to a set point match in an acquisition. This bit doesn t need to be written with a 0 to stop set point operation in a scan once that scan is stopped. It is active for one clock cycle of the write to the FPGA. 4

5 Acquisition scan list FIFO 01h Sequence of events to set up an acquisition: It is important to follow a sequence of events to successfully configure an acquisition. Reset the scan list FIFO before writing the scan list FIFO (write 0x0007 to 00h acquisition control register to completely reset device). Read 00h (Status) Name Shifting exp setup DPCROVR APCROVR Name ARBFAIL ADCFAIL SLFEF ACQCPF SCAN ACQROVR ACQFNE ACQFGT1 ACQFGT1 1 = Acq results FIFO has > 1 sample 0 = FIFO has 0 or 1 samples ACQFNE 1 = Acq results FIFO has valid data 0 = FIFO is empty ACQROVR 1 = Acq results FIFO overrun 0 = No overrun SCAN 1 = Acq logic currently scanning 0 = Acq logic is between scans ACQCPF 1 = Acq config pipe full (always set to 1) SLFEF 1 = Scan List FIFO empty 0 = FIFO not empty ADCFAIL 1 = ADC didn t return data 0 = ADC operating as expected ARBFAIL No bus arbitration on this design APCROVR 1 = Acquisition pacer overrun 0 = No overrun DPCROVR 1 = DAC pacer overrun 0 = No overrun Shifting expansion setup data (local expansion register addr: 0D hex) 1= shifting don t write register 0=not busy ACQROVR and ADCFAIL are reset by Reset Result FIFO (00h(0) bit 1). ARBFAIL is not used. APCROVR is reset by Reset configuration Pipe (00h(0) bit 0). DPCROVR is reset by Reset DAC FIFO (20h(0) bit 2). Acquisition scan list FIFO 01h Use the two 16-bit writes to the Scan List FIFO to configure each channel to be scanned (up to 512 channels total, or 2 Kb). The scan list is stored in an onboard dual-port RAM of the FPGA. On the write side of the dual port RAM, write two 16-bit words for each channel in the scan. On the read side of the dual port RAM, read 32 bits so you can read one digital channel in one system clock cycle. When analog and digital channels are in the scan list, the digital channels are read at the same time as the analog channels. The analog channels need 1 µs of delay for the analog-to-digital converter to convert an analog sample. Therefore, digital channels have no affect on the scan time in this case. 5

6 Acquisition scan list FIFO 01h Word 1 (First write to 01h) Analog CHSEL3* CHSEL2 CHSEL1* CHSEL0* SSH LAST Internal* DIG=0 Digital DIG=1 Analog CJCEN Set Point CHSEL6 CHSEL5 CHSEL4 Word 2 (Second write to 01h) Bit # 7 (23) 6 (22) 5 (21) 4 (20) 3 (19) 2 (18) 1 (17) 0 (16) Analog POD* DI_SE SELFCAL* Digital DIGADR7 DIGADR6 DIGADR5 DIGADR4 DIGADR3 DIGADR2 DIGADR1 - Bit # 15 (31 14 (30) 13 (29) 12 (28) 11 (27) 10 (26) 9 (25) 8 (24) Analog ACR2 ACR1 ACR0 GAIN3 GAIN2 GAIN1 GAIN0 DIG (bit 0): This bit is set to 1 for reading a digital channel (digital I/O, counters, Counter/encoder channels) and is set to 0 for reading analog channels. Internal (bit 1) = 1 = local board channels are read. 0 = option card channels are read. In the current implementation there are no option boards yet available so set this bit to 1. This bit also applies to expansion devices (PDQ30). If an option board of an expansion bit is being read set the bit to 0. For regular expansion channels set the internal bit to 1. Last (bit 2): This bit is set to 1 if the channel is the last channel in the scan. Otherwise set it to 0. SSH (bit 3): 1=SSH; 0= not SSH. CHSEL(6:0) (bits (10:4)) are for both main and daughter card channel selection. CHSEL[1:0] take place of CH[1:0] in the previous scan list. Choose the channel to read with CHSEL bits. CHSEL(6:0) = 0 corresponds with the first channel, 1 with the second channel, and so on. Set Point: This bit activates the channel to respond to set point data written to the set point FIFO. See Set Point FIFO section. 1 = set point active; 0 = no set point. CJCEN: This bit is set to enable a read of a CJC temperature channel. This bit in conjunction with CHSEL bits select CJC channels in a scan. DIGADR(7:1) (bits (23:17)): Use I/O address from the memory map to select counter, digital I/O and counter/encoder channels. This field is active when DIG (bit 0) is set to 1. SELFCAL (bit 21) maps CHSEL lines to a combination of SelfCalA(2:0) and SelfCalPosEn and NegEn lines on board which select self cal voltage. When SELFCAL bit is set high, the CHSEL(3:0) lines map to the following self cal voltage readings in the scan list: Self cal voltage CHSEL(3:0) Hex + 5 V V V V V V 5 0 V V V V V A -1.9 V B -5 V C 6

7 Acquisition scan list FIFO 01h DI_SE (bit 22) is 1 for differential configuration and 0 for single-ended regardless of channel or gain. POD (bit 23) bit is used to designate if the channel is an expansion channel (PDQ 30) or not. This bit is set to one if it is an expansion channel. It is set to 0 if it is a local channel. In either case the address range for either set of channels selected by this bit is 0 to N determined by CHSEL(6:0). The CHSEL(5:0) and the DI_SE bit are passed to the expansion unit for channel selection and type. Also there is an OPT generated by the FPGA logic which is determined by the Internal bit (bit 1) in the scan list. GAIN[2:0] (bits (26:24)) take place of gain A, B, C. The gains for the PCI-2500 Series are as follows: Voltage range (+/-volts) 10 V 0 5 V 1 2 V 2 1 V V V V 6 Gain[2:0] Hex GAIN3 (bit 27) is not yet implemented on PCI-2500 Series. ACR(2:0) (bits (31:29)) analog convert Rate(2:0) determines time between analog-to-digital conversions (ADC) or settling time. ACR(2:0) Convert time µs µs µs ms 100 Variable rate set by variable conversion rate register (0Fh) This entry does not affect acquisition time for digital samples that are read in one system clock cycle. There will be no option for digital sampling time. In the case where we read digital channels on a daughter card (might happen) we will allow 1 µs for a sample due to the fact that digital data is transmitted serially and takes a certain amount of time. The rate of 1uS is the operational convert rate of the PCI-2500 Series. Averaging for 50 and 60 cycle rejection: The conversion rates 100 and 101 allow us to average 256 samples over exactly a 1/50 or 1/60 second period. The conversion rate is set in the scan list and oversample averaging for 256 samples is set up in the acquisition control Register. Analog channel configuration is determined by parameters CHSEL(3:0) channel select, GAIN(2:0) for gain, and DI_SE to indicate if the channel is differential or single ended. SELFCAL bit must be 0 when reading an analog channel. There are the same number of bits in the scan list for digital or analog channels 32 bits. The scan list can be read back by the driver like we do now in the daqbxxxx after doing a Reset config pipe (bit 0 of acquisition control register). Scan list FIFO is read/write but the read address must be reset with a "Reset Config Pipe" between writing and reading the scan list FIFO. 7

8 Acquisition pacer clock 02h, 03h, 05h Acquisition pacer clock 02h, 03h, 05h The acquisition pacer clock is derived by counting clock ticks of the 48 MHz system clock to derive scan timing. The divisor has a resolution of 1/48 µs. The formula for the scan period for the divisor N is: N = (scan period (in µs) X 48) 1 or N = (scan period (in seconds) X 48,000,000) -1 or Scan period = (N +1)/48 in µs or Scan period = (N +1)/48,000,000 in seconds The maximum estimated rate for scanning a single digital channel is 12 MHz, with the divisor N = 3. The maximum scan time is 24 hours ((24 h 3600 s 48,000,000 µs) 1 ) gives us a divisor of 3C FFFF hex. The scan period can be longer, but because this is a 42-bit divisor, the maximum scan period was set at 24 hours. The 42 bits fit in the three acquisition pacer clock divisor registers. Word 0 (02h) Name APCR15 APCR14 APCR13 APCR12 APCR11 APCR10 APCR9 APCR8 Name APCR7 APCR6 APCR5 APCR4 APCR3 APCR2 APCR1 APCR0 Word 1 (03h) Name APCR31 APCR30 APCR29 APCR28 APCR27 APCR26 APCR25 APCR24 Name APCR23 APCR22 APCR21 APCR20 APCR19 APCR18 APCR17 APCR16 Word 2 (05h) Name APCR42 APCR41 APCR40 Name APCR39 APCR38 APCR37 APCR36 APCR35 APCR34 APCR33 APCR32 8

9 Acquisition scan 04h Acquisition scan 04h Word 0 (04h) Name ACQCNT15 ACQCNT14 ACQCNT 13 ACQCNT12 ACQCNT11 ACQCNT10 ACQCNT9 ACQCNT8 Name ACQCNT7 ACQCNT6 ACQCNT 5 ACQCNT15-0: 16-bit count that increments each time a scan completes. Reset to 0 when either: the Acq pacer clock enable is written with a '1' a hardware trigger (TTL or analog) is enabled. Acquisition trigger 06h Word 0 (06h) ACQCNT4 ACQCNT3 ACQCNT2 ACQCNT1 ACQCNT0 Name ACQTCT15 ACQTCT14 ACQTCT13 ACQTCT12 ACQTCT11 ACQTCT10 ACQTCT9 ACQTCT8 Name ACQTCT7 ACQTCT6 ACQTCT5 ACQTCT4 ACQTCT3 ACQTCT2 ACQTCT1 ACQTCT0 ACQTCT15-0: 16-bit value of the acquisition scan counter when the last trigger event occurred. PDQ utility 07h PDQ utility register (write) Word 0 (06h) Name Name D7 D6 D5 D4 D3 D2 D1 D0 1=on 2=off The PDQ utility register is a read/write register. To write a byte of data to the PDQ utility register: Write to register 07h with bit 8 set to 1, and a byte of data in bits 7 to 0. Bit 8 determines whether or not the RCLK signal going from the main unit to the expansion unit is active. After writing to register 07h, perform reads of this same register, and monitor bit 15 to determine when the transaction is complete. Bit 14 is a timeout bit that detects when there is no response within 31 RCLK pulses of the start of the transaction, indicating that no expansion unit is present. If bits 15 and 14 are both low after writing to the PDQ utility register, then bits 7 to 0 are the valid data returned by the expansion unit. If no expansion unit is present (bit 14 = 1), then write 0000h (bit 8 = 0) to the PDQ utility register to turn off the physical RCLK signal on the main unit. 9

10 Acquisition results 08h and shadow (0Ah) PDQ Utility Register (read) Name 1=on 2=off Name D7 D6 D5 D4 D3 D2 D1 D0 Acquisition results 08h and shadow (0Ah) These registers (08,0A) are not accessible in the PCI-2500 Series. Data is piped to the FIFO and is DMA'd to the PC "on demand." When a certain amount of data depends on the acquisition rate, the DREQ1 signal is asserted to the PLX 9056 PCI interface IC, and a DMA burst transfers data from the FPGA to the PC. The PLX 9056 gets its transfer addresses from the chaining descriptors read from PC memory. The status bits associated with this FIFO do not need to be read or acted upon. Set point 09h For every channel in the scan list that has the Set Point bit set, there is a corresponding entry in the Set Point FIFO for that channel. The order follows the sequence that they are set in the Scan List FIFO. A maximum of 16 Set Point channels are allowed. The set point conditions apply to analog and digital channels. There are five 16-bit entries in a Set Point FIFO entry. They are as follows: Word 1 (First write to 09h): Set point A - 16 bits corresponding to analog or digital data. Word 2 (Second write to 09h): Set point B - 16 bits corresponding to analog or digital data. Word 3 (Third write to 09h): - DA - This is the update data if the conditions in Q(2:0) 000, 001, 010, 011, and 100 are met, or if Ch < A in hysteresis mode. This is the 16-bit DAC data if a DAC is to be updated or if P2C is to be updated the lower 8 bits represent the bits in P2C and the data in which to update them and the upper 8 bits represent which bits in P2C are to be updated with the values in the data field. When the action is updating the timer Q[7:4]= 0110 or 0111, writing an FFFF hex turns off the timer. DAC Data Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0) Update P2C Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8) or Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0) Mask (7) Mask (6) Mask (5) Mask (4) Mask (3) Mask (2) Mask (1) Mask (0) Word 4 (Fourth write to 09h): DB - This update data is used in Hysteresis mode when: Ch > B, or if the inverse mode is set, when all the other mode conditions are NOT met. This is the 16-bit DAC data if a DAC or P2C is updated. The lower 8 bits represent the bits in P2C and the data used to update them, and the upper 8 bits represent the bits in P2C update with the values in the data field. When the action updates the timer Q[7:4]= 0110 or 0111, writing an FFFF hex turns off the timer. 10

11 Set point result 0Bh Word 5 (Fifth write to 09h): This 8-bit field represents the setpoint conditions and the action to take when these conditions are met or not met. Word 5 Q (7) Q (6) Q (5) Q (4) Q (3) Q (2) Q (1) Q (0) Defined as: X X X X X X X X Q[2:0] Setpoint criteria Q[7:4] Type of action 000 Ch=A 0000 None 001 Ch<A 0001 Update P2C 010 A<Ch<B (inside window) 0010 Update DAC0 011 Ch>B 0011 Update DAC1 100 Ch<A or Ch>B (outside window) 0100 Update DAC2 101 Hysteresis mode 0101 Update DAC Update Timer Update Timer 1 Q3=1 Inverse action taken for all actions above except hysteresis When Q3 is set, if the setpoint criteria are not met, the action (write DAC or update P2C) executes based on data DB in all modes except hysteresis mode. When Q3 is 0, action executes only when conditions are met and the is data from DA. In Hysteresis mode, an update from DA is executed when Ch < A, or an update from DB is executed when Ch > B. When the action updates the timer Q[7:4]= 0110 or writing an FFFF hex turns off the timer. Set point result 0Bh This register reflects the condition of a set point entry. The bit is 1 if the set point conditions are met, or 0 if it is not. This register can be read either with an asynchronous register or in the scan list. Each set point has a corresponding result bit based on its entry position in the Set Point FIFO bit 0 is the first entry in the set point FIFO, bit 1 the second, and so on. The state of the bit reflects the result of the set point the last time it was evaluated. The set point is evaluated every scan as the data is being stored in the acquisition FIFO. For this reason, the Set Point Result Register should be read at the end of the scan to reflect the most current condition of the set points. The bits are not cleared on read, but only reflect whether or not the set point conditions were met. The bit is set when the set point conditions are met, and cleared when the conditions are not met on a scan-by-scan basis. Word 0 (06h) Set point result SP (7) SP (6) SP (5) SP (4) SP (3) SP (2) SP (1) SP (0) SP (15) SP (14) SP (13) SP (12) SP (11) SP (10) SP (9) SP (8) 11

12 ADC 0Ch ADC 0Ch The current value of the ADC can be read from this register. It is only used for development purposes when the data from the A-to-D cannot be returned via DMA. Every ADC reading is stored in this register and overwrites the previous ADC conversion data as it comes from the ADC. Local expansion 0Dh This 16-bit register is written with 16 bits to shift out serially to the PCI-2500 Series onboard option board connecter J1. Monitor the acquisition status register (00h) bit 10 indicating when the data is being shifted out to the option board. If data is written to this register while it is shifting, the previous data written is corrupted. This register is intended for use in configuring option card parameters. Variable conversion rate 0Fh This 16-bit register is written with 16 bits that work with the ACR (analog conversion rate of the scan list FIFO) bits in the scan list. When ACR [2:0] = 100 b, the time between analog conversions is determined by the variable conversion rate register value according to the formula: N = (conversion period (in µs) X 48) 1 or N = (conversion period (in seconds) X 48,000,000) -1 This formula is the same as the one used to derive a divisor for the acquisition pacer clock. For line cycle rejection, a number of samples are oversampled and averaged. This is a power of two over the period of one cycle either 1/60 or 1/50 of a second. Following is a matrix of number of samples to average and the actual value of the variable conversion rate register to accomplish line cycle rejection. We plan to implement only 256 and number of samples for line cycle averaging. The 256 number gives us exactly the time of one line cycle; the number of gives us the maximum amount of noise rejection. # of samples to average Rejection Frequency (Hz) Register 0Fh value (decimal)

13 Analog output 10h Analog output 10h Write 10h (Control) Bit # DAC Update control X 0h X 1=Reset DAC FIFO X X DAC Pacer clock control X,RI 1h O E 1=Use acq Pacer 1=External, 0=Internal 1=Enable, 0=Disable DAC 0 Enable X 2h X X 1=Signed, 0=Unsigned 1=Enable, 0=Disable DAC 1 Enable X 3h X X 1=Signed, 0=Unsigned 1=Enable, 0=Disable DAC 2 Enable X 4h X X 1=Signed, 0=Unsigned 1=Enable, 0=Disable DAC 3 Enable X 5h X X 1=Signed, 0=Unsigned 1=Enable, 0=Disable Pattern Enable X 6h X X X 1=Enable, 0=Disable DAC Pacer clock control: Enable/disable the DAC pacer, program as external (input) or internal (output), and program to be driven by the acquisition pacer (analog output or P3 pattern is then updated at the end of each scan). If internal, OE = 1 enables the external output driver. Bit 8 controls the external pacer-clock polarity. 0 (default) = falling edge 1 = rising edge. DAC X Enable: Enable/disable DAC X for waveform output DAC X Signed: Don't invert (signed) or invert (unsigned) MSB of DAC data. Pattern Enable: Enable/disable digital I/O (ports B and A) for pattern (waveform) output. Read 10h (Status) Name DAC3BUS Y DAC2BUS Y DAC1BUS Y DAC0BUS Y CALBUSY TRGBUSY Dac Fifo Underrun DACFULL DACFULL 1 = DAC FIFO is full 0 = DAC FIFO is not full (ready for new data) No driver intervention is required. DMA is on-demand and is controlled by the FPGA. Dac FIFO Underrun 1 = When waveform output FIFO on the FPGA is empty and is not able to get new data before new data was needed to update DACs. This indicates a catastrophic error and waveform output is stopped by FPGA. Need to do a DAC reset FIFO to reset this error bit. 0 = DMA is keeping up with data requirements of waveform output. TRGBUSY 1 = Trigger DAC logic busy shifting data 0 = Trigger DAC logic is idle (ready for new data) CALBUSY 1 = Calibration EEPROM logic busy moving data 0 = calibration EEPROM logic is idle (ready for read/write) DACxBUSY 1 = DAC x is busy shifting data 0 = DAC x logic is ready for new data 13

14 Analog output 12h Analog output 12h The analog output FIFO buffers the waveform and pattern output data. Data is written to this register directly by the chaining DMA operation of the PLX 9056 and is not accessible by register I/O. This one-sample FIFO buffers the analog outputs (and P3 pattern register) and feeds the DACs and P3. The FPGA generates DMA requests and keeps a certain number of words in an analog output FIFO in the FPGA. The data comes from addresses in memory contained in the chaining descriptors read from PC memory by the PLX 9056 (see section and figure 5-17 in the PLX 9056 data book).the DACs are updated in the order of Dac 0 to Dac 3, and then digital pattern output if they are enabled. So, if only one DAC is enabled, then every sample written to the FIFO is directed to that DAC. The FPGA directs the FIFO data to the appropriate destination based on which destinations are enabled. If only one DAC is enabled, then every sample written to the FIFO is directed to DAC. If two DACs are enabled, each gets every other sample. The destinations are always written in the same order: DAC 0 (if enabled) first, then DAC 1 (if enabled), then DAC 2 (if enabled), then DAC 3 (if enabled), and finally P3 (if enabled). Then the cycle repeats at a rate determined by the DAC pacer clock. HOST DMA0c FIFO WORD 0 Waveform Output DAC SHIFT REG 0..3 OR P3 PAT REG Analog output (DAC) pacer clock 15h, 17h, 11h DAC 0..3 OR P3 OUTPUT The analog output pacer clock divisor is calculated with the same formula used for the acquisition pacer clock. The acquisition pacer clock is derived by counting clock ticks of the 48 MHz system clock to derive scan timing. The divisor has a resolution of 1/48 µs. The formula for the divisor N is: 15h = divisor low; 17h = divisor mid; 11h= divisor high N = (scan period (in µs) X 48) 1 or N= (scan period (in seconds) X 48,000,000) -1 or Scan period = (N +1)/48 in µs or Scan period = (N +1)/48,000,000 in seconds The maximum rate for outputting only digital pattern data is 12 MHz. If an analog channel is being output, then the maximum rate is 1 MHz. The maximum rate for analog channels is 1 MHz regardless. Word 0 (15h) Name DPCR15 DPCR14 DPCR13 DPCR12 DPCR11 DPCR10 DPCR9 DPCR8 Name DPCR7 DPCR6 DPCR5 DPCR4 DPCR3 DPCR2 DPCR1 DPCR0 Word 1 (17h) Name DPCR31 DPCR30 DPCR29 DPCR28 DPCR27 DPCR26 DPCR25 DPCR24 Name DPCR23 DPCR22 DPCR21 DPCR20 DPCR19 DPCR18 DPCR17 DPCR16 14

15 Analog output scan 0Eh Word 2 (11h) Name DPCR42 DPCR41 DPCR40 Name DPCR39 DPCR38 DPCR37 DPCR36 DPCR35 DPCR34 DPCR33 DPCR32 Analog output scan 0Eh Read 0Eh Name DACCNT15 DACCNT14 DACCNT13 DACCNT12 DACCNT11 DACCNT10 DACCNT9 DACCNT8 Name DACCNT7 DACCNT6 DACCNT5 DACCNT4 DACCNT3 DACCNT2 DACCNT1 DACCNT0 DACCNT15-0: 16-bit count that increments every DAC pacer clock pulse. Reset to 0 when the DAC pacer clock is enabled. DAC 0 3 1Ch, 1Dh, 1Eh, 1Fh Writing any of the DAC Setting registers with a 16-bit value sets the DAC output voltage. The DAC's sign must be set in the analog output control register before writing the static DAC value (refer to "Analog output 10h" on page 13). DAC0 = 1Ch; DAC1 = 1Dh; DAC2 = 1Eh; DAC3 = 1Fh; In unsigned mode a value of 0000h results in an output of -10 V where a value of FFFFh results in +10 V. In signed mode a value of 0000h to 7FFFh gives use a range of 0 to +10 V. 8000h to FFFFh gives us a range of -10 V to 0. Digital I/O 18h Write 18h (Control) Bit # P1 control X 0h X X X 1=Test, 0=Normal P1 Test Output Value X 1h X SSH state DAC Pacer state Acquisition Pacer state P2 control X 3h X X 1=Expansion, 0=82C55 X Timer control X 5h X X 1=Output, 0=Input 1 =Test, 0=Normal Timer Test Output Value P1 test/normal P2 Exp/82C55 Timer test/normal Timer output X 6h X X Timer 1 state Timer 0 state 1 = P1 test mode 0 = P1 normal mode 1 = P2 expansion port (addr, data, control) 0 = P2 82C55 emulation 1 = Timer test mode 0 = Timer normal mode 1 = High 0 = Low 15

16 16-bit digital 19h Read 18h (Status) Name DPCRIN APCRIN APCRIN: This bit follows the acquisition pacer input, before it goes into the divider. DPCRIN: This bit follows the analog output (DAC) pacer input. These follow the P1 test output values if the pacer clocks are programmed as outputs (and no external signal is driving them). 16-bit digital 19h This 16-bit digital I/O port is P2 portb (msb) and porta (lsb) concatenated. Since these ports are shared and accessed both from this address and by accessing P2 portb and porta, to read this port asynchronously or in a scan, you must set configure portb and porta to be inputs in the 8255 control word. To output data either asynchronously or in pattern output mode, you do not need to write the 8255 control word to set the two ports as outputs. P2 82C55 20h - 23h This is an 82C55-compatible digital interface. The digital I/O control/status register enables/disables this interface. For more details regarding these registers, refer to an 82C55 data sheet. P2 port C cannot be split both halves MUST be in or out; user can t have access to 8255 control word. The least significant bit in control word (lower) nibble is used to control port C transceiver direction. You can only use 8255 in mode 0 ONLY. Port A (20h) Name PPIA7 PPIA6 PPIA5 PPIA4 PPIA3 PPIA2 PPIA1 PPIA0 Port B (21h) Name PPIB7 PPIB6 PPIB5 PPIB4 PPIB3 PPIB2 PPIB1 PPIB0 Port C (22h) Name PPIC7 PPIC6 PPIC5 PPIC4 PPIC3 PPIC2 PPIC1 PPIC0 Control (23h) Name PPICTL7 PPICTL6 PPICTL5 PPICTL4 PPICTL3 PPICTL2 PPICTL1 PPICTL0 (from 8255 data book) PPICTL0: Port C (lower 4 bits): 1 = input; 0 = output PPICTL1: Port B: 1 = input; 0 = output PPICTL2: Mode Selection: 0 = mode 0; 1 = mode 1 PPICTL3: Port C (upper 4 bits): 1 = input; 0 = output PPICTL4: Port A: 1 = input; 0 = output PPICTL[6:5]: Mode Selection: 00 = mode 0; 01 = mode1; 1X = mode 2 16

17 Counter-timer 40h Counter-timer 40h Write 40h (control) Bit # Timer 0 enable X X 0h X X X 1=Enable, 0=Disable Timer 1 enable X X 1h X X X 1=Enable, 0=Disable All timers enable X X 4h X X X 1=Enable, 0=Disable Counter 0 cascade X X 5h X X X Counter 1 cascade X X 6h X X X Counter 0 enable/clear Counter 1 enable/clear Counter 2 enable/clear Counter 3 enable/clear All counters enable/clear X X X X C S C S C S C S 1=Cascade counter 0 and counter 2 1=Cascade counter 1 and counter 3 7h Rising Clear on read Clear counter 0 1=Enable, 0=Disable 8h Rising Clear on read Clear counter 1 1=Enable, 0=Disable 9h Rising Clear on read Clear counter 2 1=Enable, 0=Disable Ah Rising Clear on read Clear counter 3 1=Enable, 0=Disable X X Fh X X Clear all counters 1=Enable, 0=Disable Timer X enable: Enable/disable timer X output (when disabled, the output is 0). All timers enable: Enable/disable all timer outputs. Counter 0 cascade: Cascade counter 0 and counter 2. Use counter 0 control; counter 2 latched when counter 0 read. Counter 1 cascade: Cascade counter 1 and counter 3. Use counter 1 control; counter 3 latched when counter 1 read. Counter X enable: Enable/disable counter X. Counter X clear: Clear counter X. Clears 32 bits if cascaded. Counter X clear-on-read 1 = Clear counter when read 0 = Don t Clear counter when read. Counter X rising 1 = Count rising edges 0 = count falling edges. Counter X clear-on-start (CS) 1 = clear counter on acquisition start, 0 = don't. All counters enable/clear: Enable/disable/clear all counters. If a counter or cascaded pair is set for clear-on-read, then it does not overflow. Instead, it stops counting at its maximum count (0xFFFF or 0xFFFFFFFF). Read 28h (Status) Name CNT3IN CNT2IN CNT1IN CNT0IN CNTXIN: These bits follow the counter inputs. 17

18 Count 44 47h Count 44 47h One 16-bit register for each counter. When counter 0 and counter 2 or counter 1 and counter 3 are cascaded, both registers must be read and combined to obtain the 32-bit value (the upper register is latched when the lower one is read). Counter/encoder channel 0-3 Setup 28 2Bh Each of these four registers has the bits defined as follows: Name TICK1 TICK0 MAP3 MAP2 MAP1 MAP0 OPT6 OPT5 Name OPT4 OPT3 OPT2 OPT1 OPT0 MODE2 MODE1 MODE0 TICK [1:0]: These signals determine the tick length. 00: 1 clock cycle per tick ( ns/tick) 01: 10 clock cycles per tick ns/tick) 10: 100 clock cycles per tick ( ns/tick) 11: 1000 clock cycles per tick ( ns/tick) MAP [3:0]: These signals select the input channel or pattern detection channel used for the map channel. 0000: channel : channel : channel : channel : asynchronously read channel : asynchronously read channel : asynchronously read channel : asynchronously read channel 4 OPT [6:0]: These option signals for each channel determine what variables are chosen for the mode that the signal is currently in. MODE [2:0]: These last bits of the channel setup register are used to choose the mode in which the channel runs. Note that only odd-numbered channels can be the A channel in encoder mode, and only even-numbered channels can be the B channel in encoder mode. 18

19 Debounce setup for counter/encoder channels 0 and 2Ch The OPT and MODE correlations are given below: MODE[2:0] MEAS MODE CLEAR COUNTER PERIOD PULSEWIDTH TIMING ENCODER OPT0 0=TOTALIZE 1=COR Periods/Meas. 00=1 Period 00=>1X, 01=>2X OPT1 0=Rollover 1=Stop at the Top 01=10 Periods 10=100 Periods 11=1000 Periods 10=>4X OPT2 0=16 bit CTR 1=32 bit CTR 0=16 bit CTR 1=32 bit CTR 0=16 bit CTR 1=32 bit CTR 0=16 bit CTR 1=32 bit CTR 0=16 bit CTR 1=32 bit CTR OPT3 Map channel 0=Latches on SOS 1=Latches on Map Map channel 0=Latches on SOS 1=Latches on Map OPT4 Map channel 0=Doesn t Gate 1=Gates CTR Map channel 0=Doesn t Gate 1=Gates CTR Map channel 0=Doesn t Gate 1=Gates CTR Program a zero here. Map channel 0=Doesn t Gate 1=Gates CTR OPT5 Map channel 0=Doesn t DEC 1=DECs CTR Map channel 0=Doesn t Clear 1=Clears CTR OPT6 Map channel 0=Count Ch 1=Count Map Ch Map channel 0=Meas. Input 1=Meas. Map Ch. Map channel 0=Meas. Input 1=Meas. Map Ch. Since there are four channels in this design, there are four channel-setup registers as well. The channel-setup registers are given addresses in the [7:1] address space on the acquisition engine. Debounce setup for counter/encoder channels 0 and 2Ch These two registers are also given addresses in the [7:1] address space on the acquisition engine used to setup the debounce module of the FPGA. Since only eight bits per channel are necessary for this setup, they have been combined to make two registers with setup data for two channels each. Name DEB3 ON DEB3 MODE DEB3 INV DEB3 APPLY DEB3 RANGE DEB3 2 DEB3 1 Name DEB4 ON DEB4 MODE DEB4 INV DEB4 APPLY DEB4 RANGE DEB4 2 DEB4 1 DEB3 0 DEB4 0 Debounce setup for counter/encoder channels 2 and 2Dh Name DEB1 ON DEB1 MODE DEB1 INV DEB1 APPLY DEB1 RANGE DEB12 DEB1 1 Name DEB2 ON DEB2 MODE DEB2 INV DEB2 APPLY DEB1 RANGE DEB10 Since there are four channels in this design, there are four channel setup registers as well. They will are given addresses in the [7:1] address space on the acquisition engine, as are the next registers covered. The next two registers are used to setup the debounce module of the FPGA. Since only eight bits per channel are necessary for this setup, they have been combined to make two registers with setup data for two channels each. DEB2 2 DEB2 1 DEB2 0 19

20 Asynchronously reading these counters DEBX [2:0]: Debounce time for channel X. 000: 500 ns/0.1 ms 001: 1.5 µs/0.3 ms 010: 3.5 µs/0.7 ms 011: 7.5 µs/1.5 ms 100: 15.5 µs/3.1 ms 101: 31.5 µs/6.3 ms 110: 63.5 µs/12.7 ms 111: µs/25.5 ms DEBXRANGE: This signal determines the time used by the debounce. 0: Low Range 1: High Range DEBXAPPLY: This signal determines whether the signal is debounced or not. 0: Bypass Debounce 1: Apply Debounce DEBXINV: This signal chooses the edge to detect. 0: Rising edge 1: Falling edge DEBXMODE: This signal chooses whether the channel is in "true debounce" mode or in trigger before stable mode. 0: Trigger after stable 1: Trigger before stable DEBXON: This signal determines whether or not the channel is driven. 0: Channel is off 1: Channel is on Asynchronously reading these counters There are a few options to set before reading these counters asynchronously, and a few requirements to consider. To asynchronously read a counter channel, the OPT3 bit must be set to 1. The MAP bits must be set according to the "MAP [3:0]" in the Counter/encoder channel 0-3 Setup Registers section on page 18 to reflect the desired channel. OPT0 can be set to Totalize or Clear on Read it is not affected by the other channels. A counter can only be asynchronously read when it is NOT in the scan-list. Counter/encoder counters 30h - 37h There are two 16-bit count registers for each counter/encoder counter channel. You can program these encoder counters as either 16-bit or 32bit counters (refer to "Counter-timer 40h" on page 17). If the channel is setup as a 16-bit counter, only the low register of the pair is read. Channel 0 low: 30h Channel 1 low: 32h Channel 2 low: 34h Channel 3 low: 36h 20

21 Timer 50h, 51h If a channel is setup as a 32-bit counter, then the low register is read first and then the high (16 bits are read at a time). This order applies for synchronous and asynchronous reads. Channel 0 low, high: 30, 31h Channel 1 low, high: 32, 33h Channel 2 low, high: 34, 35h Channel 3 low, high: 36, 37h Timer 50h, 51h One 16-bit divisor for each timer defines the timer s output frequency. Each output is a 50% duty cycle square wave. Timer frequency out = 1 MHz /(Divisor+1). DMA 58h Write 58h (Control) Bit # DMA channel 0 enable X 0h X X X 1=Enable, 0=Disable DMA channel 1 enable X 1h X X X 1=Enable, 0=Disable Enable DMA 0 after DMA descriptors and data are defined for streaming output of DACs and digital output. This is followed by enabling individual output channels and then enable the DAC pacer clock (refer to "Analog output 10h" on page 13). Enable DMA 1 with acquisition parameters and DMA descriptors before starting the acquisition pacer clock to start acquisition data to be returned via DMA. Trigger 59h Write 59h (Control) Bit # Trigger control X X 1=TTL, 0=ANA X 1=L or H-to-L, 0=H or L-to-H 1=Level, 0=Edge 1=Enable, 0=Disable Trigger control: Selects TTL or analog trigger. Configures selected trigger: enable/disable, program level or edge trigger, polarity (high-to-low or low-to-high). When programming the analog trigger for a level, the threshold comparator is used for the trigger. Triggers are disabled immediately after they are detected to prevent double triggering. Read 59h (Status) Bit # Trigger control X X 1=TTL, 0=ANA X 1=L or H-to-L, 0=H or L-to-H ATRIGB: Current state of the analog hardware trigger TRIGB (threshold) comparator ATRIGA: Current state of the analog hardware trigger TRIGA (hysteresis) comparator TTLTRIG: Current state of the TTL trigger input TRGEVT: Set when an enabled hardware trigger occurs. Cleared on read. 1=Level, 0=Edge 1=Enable, 0=Disable ATRIGB, ATRIGA, and TTLTRIG are set to '1' when their respective input signals are high, and set to '0' when their signals are low. 21

22 Analog TRIGA (hysteresis) and TRIGB (threshold) 5Eh Analog TRIGA (hysteresis) and TRIGB (threshold) 5Eh These 12-bit DACs program the hysteresis and thresholds for the hardware analog trigger. Write BCh5Eh Name B/A- BUF PD1 PD00 ATRIG11 ATRIG10 ATRIG9 ATRIG8 Name ATRIG7 ATRIG6 ATRIG5 ATRIG4 ATRIG3 ATRIG2 ATRIG1 ATRIG0 B/A-: Selects DAC: 0 = hysteresis DAC (TRIGA), 1 = threshold DAC (TRIGB) BUF: Enables DAC's internal reference buffer. Normally 0 (unbuffered). PD[1:0]: Power-down mode, 00 = normal operation, 01 = 1 kω to GND, 10 = 100 kω to GND, 11 = hi-z. ATRIG[11:0]:Selected DAC setting. 000h = full-scale negative. FFFh = full-scale positive. Calibration table 5Ch(B8h) The calibration table is stored in a 64K 8 serial EEPROM (AT25640). The EEPROM responds to commands (called opcodes) that allow it to be put into different modes for reading, writing, and write-protecting. All commands require an opcode; some commands also require an address and/or data. The table below shows the different commands, their op-codes, and how many words are sent out. Before sending commands to the EEPROM, the byte count and hold bits must be programmed in the acquisition control register. The analog output status register can be polled to check busy status during serial transfers, and the RDSR command can be used to check for EEPROM write completion. For more specifics about the EEPROM chip, refer to the AT25640 data sheet. Write 36h 1Bh (Calibration EEPROM control) (CALCTLCS) Bit # Cal EEPROM control X Cal command Hold Cal command byte count Write Enable Write Enable: Enable (1) or disable (0) calibration EEPROM writing. Calibration command byte count 1 = Send two bytes to EEPROM 0 = Send one byte to EEPROM Calibration command hold 1 = Hold cal EEPROM CS - asserted for more data transfers 0 = Release cal EEPROM CS- in anticipation of a new command Command Operation Op-code # bytes WREN Write enable the device 06h 1 WRDI Write disable the device 04h 1 RDSR Read status register 05h 2 WRSR Write status register 01h 2 READ Read byte from memory array 03h 3+N WRITE Write byte to memory array 02h 3+N 22

23 Calibration table 5Ch(B8h) WREN and WRDI commands WORD 0: Cal command byte count = 0, Cal command hold = 0 Name Name OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RDSR and WRSR commands After sending RDSR, the status byte can be returned by reading the same location. WORD 0: Cal command byte count = 0, Cal command hold = 0 Name OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Name STAT7 STAT6 STAT5 STAT4 STAT3 STAT2 STAT1 STAT0 READ and WRITE commands Up to 32 bytes can be written at once. Any number of bytes can be read. WORD 0: Cal command byte count = 0, Cal command hold = 0 Name Name OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 WORD 0: Cal command byte count = 0, Cal command hold = 0 Name ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 Name ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 WORD 2 to N-1: Cal command byte count = 0, Cal command hold = 0 Name DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Name DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 WORD N: Cal command byte count = 0, Cal command hold = 0 Name DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Name DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 23

24 Digital 5Dh (BAh) OP0-7: Op-code (command) STAT0-7: Status byte ADDR0-15: Memory byte address DA0-7: Data byte for address N DB0-7: Data byte for address N+1 Digital 5Dh (BAh) Use this read/write register stores temporary digital patterns for "marking" acquisitions. The register is cleared after being read. Name DIGMRK7 DIGMRK6 DIGMRK5 DIGMRK4 DIGMRK3 DIGMRK2 DIGMRK1 DIGMRK0 External clock 74h Use this write-only register to hold the ECLKDIV divisor for the external clock. ECLKDIV is the 16-bit number that the external pacer clock gets divided by when it comes into the circuit. This number is from 0 to 65535, with the divisor being one plus this number, just like the internal pacer clock. On power-up, it defaults to a zero. Name EDIV15 EDIV14 EDIV13 EDIV12 EDIV11 EDIV10 EDIV9 EDIV8 Name EDIV7 EDIV6 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 External clock Divisor = EDIV[15:0] +1. EDIV defaults to zero upon reset. Performance test register (write 7Bh Use this 16-bit write-only register to implement a performance by following these steps: 1. Write an acquisition pacer clock divisor (refer to "Acquisition pacer clock divisor" on page Enable DMA channel Write a 1 to bit 0 of this register. These steps starts a sequence in which 16-bit samples are put into the FIFO at a rate determined by the acquisition pacer divisor. It uses the same DMA process as acquisition data. The data is sequential it starts at 0, increments to FFFF hex, and then rolls over to After the performance test is complete, write a "0" to bit 0 to stop the incremental data from being put into the FIFO. 5. Perform a FIFO reset operation to flush all data and reset the FIFO write and read pointers. The FPGA is now in a state to process acquisition data. Bit 1 starts the DMA loop test explained below. Bit 0 and 1 must be set to 0 (their default value) when acquiring data. Name X X X X X X DMA Loop Test Ramp Test Performance tests: There are two types of performance tests done on the PCI-2500 Series. Ramp data test: This test sends back data on DMA channel 1 (the acquisition DMA channel) that sequentially increments each sample. The data is generated by a digital counter in the FPGA. The data rate is determined by the acquisition Pacer clock. The steps to accomplish this test are: 24

25 Configuration data test register (write 7Ch 1. Set the acquisition pacer divisor for the desired data rate register addresses 02, 03, and 05 hex. 2. Set up the DMA descriptors and the DMA control register to enable DMA Set the command register (7B hex) bit 0 to 1 to start the data streaming back at the set rate on the acquisition DMA channel. DMA loop test: This test takes data that is DMA'd to the FPGA on DMA channel 0, and sends it back to the PC on DMA channel 1. The steps to accomplish this test are: 1. Set the acquisition pacer divisor for the desired data rate at register addresses 02, 03, and 05 hex. 2. Set up the DMA descriptors for both DMA channel 0 (data to FPGA) and DMA channel 1 (data from FPGA). Set the DMA control register to enable both DMA channel 0 and 1. Program a slight delay (1 ms) to allow the FPGA to start to get data from DMA channel 0 before the next step. 3. Set the command register (7B hex) bit 1 to 1 to start getting data from DMA channel 0 and putting it into the acquisition FIFO at the rate set by the acquisition pacer divisor. The data is then DMA'd back to the PC on DMA channel 1 as it does during an acquisition. To stop either test, write 0000 hex to the command register (7B), and reset the results FIFO by writing a 1 to bit 1 (0002 to register 00hex) to reset the results FIFO and test control bits. Configuration data test register (write 7Ch Name X CJCEN pod option local Gain_5a Gain_1a gain_1.25c Name Gain_2.5c Gain_5c Ch1 Ch0 lob hib Di_se Hi_lo Writing to the configuration data test register sets the analog configuration bits statically. These bits are meant to be set when there is no acquisition in progress. DWORD count register 7Eh The DWORD count register is a 32-bit register that counts 32-bit words as they are read on the local bus by the PLX 9056 during DMA. The register requires two reads of the same address 7E hex which is a change from reading 32-bits from two addresses. Reading from this register is similar to reading from a FIFO. However, you must read two 16-bit words from the location. The first is the low word and the second is the high word of the 32 bit count. The register keeps its value and keeps incrementing after it is read since it is not a clear-on-read register. The driver reads this register to know how much data has returned to the PC DMA RAM. To reset the low/high order,exert the reset results in the acquisition control register to make that the next time this register is read, the low word is read. 25