SSD1316. Advance Information. 128 x 39 Dot Matrix OLED/PLED Segment/Common Driver with Controller

Transcription

1 SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD36 Advance Information 28 x 39 Dot Matrix OLED/PLED Segment/Common Driver with Controller This document contains information on a new product Specifications and information herein are subject to change without notice SSD36 Rev 4 P /63 Mar 25 Copyright 25 Solomon Systech Limited

2 Appendix: IC Revision history of SSD36 Specification Version Change Items Effective Date st Release 5-Jul- Advance Information Release Modify from SSD36 Product Preview R Update the Charge Pump 8D Command Update the DC characteristics Update the AC characteristics Advance Information Release Modify from SSD36 Advance Information R Revise typo for ADh command for internal IREF selection Update V BAT and the Charge Pump 8Dh command Update the DC characteristics Revise Figure 9 and Figure 9 for continuous scrolling Add Content Scrolling Setup details 2 Advance Information Release Modify from SSD36 Advance Information R Update Contrast Control 8h command Update Typical Frequency in AC characteristics 3 Update V DD voltage range in Feature (revise < to ) Update Power on and off sequence Update DC Characteristics on charge pump description in ITO resistance requirements Update remark in Application example 4 Update V COMH value setting description Update External or Internal V COMH selection description -Oct- 6-Apr-2 8-Nov-3 24-Jun-4 Solomon Systech Mar 25 P 2/63 Rev 4 SSD36

3 CONTENTS GENERAL DESCRIPTION 7 2 FEATURES 7 3 ORDERING INFORMATION 7 4 BLOCK DIAGRAM 8 5 DIE PAD FLOOR PLAN 9 6 PIN DESCRIPTION 7 FUNCTIONAL BLOCK DESCRIPTIONS 3 7 MCU INTERFACE SELECTION 3 7 MCU Parallel 68-series Interface 3 72 MCU Parallel 88-series Interface 4 73 MCU Serial Interface (4-wire SPI) 5 74 MCU Serial Interface (3-wire SPI) 6 75 MCU I 2 C Interface 7 72 COMMAND DECODER 2 73 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR 2 74 FR SYNCHRONIZATION 2 75 RESET CIRCUIT 2 76 SEGMENT DRIVERS / COMMON DRIVERS GRAPHIC DISPLAY DATA RAM (GDDRAM) SEG/COM DRIVING BLOCK POWER ON AND OFF SEQUENCE Power ON and OFF sequence with External V CC Power ON and OFF sequence with Charge Pump Application 26 7 CHARGE PUMP REGULATOR 27 8 COMMAND TABLE 27 8 DATA READ / WRITE 37 9 COMMAND DESCRIPTIONS 38 9 FUNDAMENTAL COMMAND 38 9 Set Lower Column Start Address for Page Addressing Mode (h~fh) Set Higher Column Start Address for Page Addressing Mode (h~7h) Set Memory Addressing Mode (2h) Set Column Address (2h) Set Page Address (22h) 4 96 Set Display Start Line (4h~66h) 4 97 Set Contrast Control (8h) 4 98 Set Segment Re-map (Ah/Ah) 4 99 Entire Display ON (A4h/A5h) 4 9 Set Normal/Inverse Display (A6h/A7h) 4 9 Set Multiplex Ratio (A8h) 4 92 External or Internal VCOMH Selection / External or internal IREF Selection (ADh) 4 93 Set Display ON/OFF (AEh/AFh) 4 94 Set Page Start Address for Page Addressing Mode (Bh~B4h) 4 95 Set COM Output Scan Direction (Ch/C8h) Set Display Offset (D3h) Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) Set Pre-charge Period (D9h) Set COM Pins Hardware Configuration (DAh) 45 SSD36 Rev 4 P 3/63 Mar 25 Solomon Systech

4 92 Set V COMH Deselect Level (DBh) NOP (E3h) Status register Read Charge Pump Setting (8Dh) GRAPHIC ACCELERATION COMMAND Horizontal Scroll Setup (26h/27h) Continuous Vertical and Horizontal Scroll Setup (29h/2Ah) Deactivate Scroll (2Eh) Activate Scroll (2Fh) Set Vertical Scroll Area (A3h) Content Scroll Setup (2Ch/2Dh) ADVANCE GRAPHIC COMMAND 5 93 Set Fade Out / Fade In and Blinking (23h) Set Zoom In (D6h) 5 MAXIMUM RATINGS 52 DC CHARACTERISTICS 53 2 AC CHARACTERISTICS 54 3 APPLICATION EXAMPLES 6 4 PACKAGE INFORMATION 62 4 DIE TRAY DIMENSIONS 62 Solomon Systech Mar 25 P 4/63 Rev 4 SSD36

5 TABLES TABLE 3- : ORDERING INFORMATION 7 TABLE 5- : SSD36Z BUMP DIE PAD COORDINATES TABLE 6- : PIN DESCRIPTION TABLE 6-2 : MCU BUS INTERFACE PIN SELECTION 2 TABLE 7- : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE 3 TABLE 7-2 : CONTROL PINS OF 68 INTERFACE 3 TABLE 7-3 : CONTROL PINS OF 88 INTERFACE 5 TABLE 7-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE 5 TABLE 7-5 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE 6 TABLE 8-: SSD36 COMMAND TABLE 27 TABLE 8-2 : SEG PINS HARDWARE CONFIGURATION 33 TABLE 8-3 : READ COMMAND TABLE 37 TABLE 8-4 : ADDRESS INCREMENT TABLE (AUTOMATIC) 37 TABLE 9- : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITHOUT REMAP 43 TABLE 9-2 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH REMAP 44 TABLE 9-3 : CONTENT SCROLLING SOFTWARE FLOW EXAMPLE (PAGE ADDRESSING MODE COMMAND 2H, 2H) 49 TABLE 9-4 : CONTENT SCROLLING SETTING EXAMPLE (VERTICAL ADDRESSING MODE COMMAND 2H, H) 5 TABLE - : MAXIMUM RATINGS (VOLTAGE REFERENCED TO V SS) 52 TABLE - : DC CHARACTERISTICS 53 TABLE 2- : AC CHARACTERISTICS 54 TABLE 2-2 : 68-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS 54 TABLE 2-3 : 88-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS 56 TABLE 2-4 : SERIAL INTERFACE TIMING CHARACTERISTICS (4-WIRE SPI) 57 TABLE 2-5 : SERIAL INTERFACE TIMING CHARACTERISTICS (3-WIRE SPI) 58 TABLE 2-6 : I 2 C INTERFACE TIMING CHARACTERISTICS 59 SSD36 Rev 4 P 5/63 Mar 25 Solomon Systech

6 FIGURES FIGURE 4- : SSD36 BLOCK DIAGRAM 8 FIGURE 5- : SSD36Z DIE DRAWING 9 FIGURE 7- : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ 4 FIGURE 7-2 : EXAMPLE OF WRITE PROCEDURE IN 88 PARALLEL INTERFACE MODE 4 FIGURE 7-3 : EXAMPLE OF READ PROCEDURE IN 88 PARALLEL INTERFACE MODE 4 FIGURE 7-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ 5 FIGURE 7-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE 6 FIGURE 7-6 : WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE 6 FIGURE 7-7 : I 2 C-BUS DATA FORMAT 8 FIGURE 7-8 : DEFINITION OF THE START AND STOP CONDITION 9 FIGURE 7-9 : DEFINITION OF THE ACKNOWLEDGEMENT CONDITION 9 FIGURE 7- : DEFINITION OF THE DATA TRANSFER CONDITION 9 FIGURE 7- : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR 2 FIGURE 7-2 : SEGMENT OUTPUT WAVEFORM IN THREE PHASES 22 FIGURE 7-3 : GDDRAM PAGES STRUCTURE OF SSD36 23 FIGURE 7-4 : I REF CURRENT SETTING BY RESISTOR VALUE 24 FIGURE 7-5 : THE POWER ON SEQUENCE 25 FIGURE 7-6 : THE POWER OFF SEQUENCE 25 FIGURE 7-7 : THE POWER ON SEQUENCE WITH CHARGE PUMP APPLICATION 26 FIGURE 7-8 : THE POWER OFF SEQUENCE WITH CHARGE PUMP APPLICATION 26 FIGURE 9- : ADDRESS POINTER MOVEMENT OF PAGE ADDRESSING MODE 38 FIGURE 9-2 : EXAMPLE OF GDDRAM ACCESS POINTER SETTING IN PAGE ADDRESSING MODE (NO ROW AND COLUMN- REMAPPING) 38 FIGURE 9-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESSING MODE 39 FIGURE 9-4 : ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESSING MODE 39 FIGURE 9-5 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT 4 FIGURE 9-6 : TRANSITION BETWEEN DIFFERENT MODES 4 FIGURE 9-7 : EXAMPLE OF ROW ADDRESS MAPPING 42 FIGURE 9-8 : HORIZONTAL SCROLL EXAMPLE: SCROLL RIGHT BY COLUMN 46 FIGURE 9-9 : HORIZONTAL SCROLL EXAMPLE: SCROLL LEFT BY COLUMN 46 FIGURE 9- : HORIZONTAL SCROLLING SETUP EXAMPLE 46 FIGURE 9- : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING SETUP EXAMPLE 47 FIGURE 9-2 : VERTICAL SCROLL AREA SETUP EXAMPLES 48 FIGURE 9-3: CONTENT SCROLLING EXAMPLE (2DH, LEFT HORIZONTAL SCROLL BY ONE COLUMN) 49 FIGURE 9-4 : EXAMPLE OF FADE OUT MODE 5 FIGURE 9-5 : EXAMPLE OF FADE IN MODE 5 FIGURE 9-6 : EXAMPLE OF BLINKING MODE 5 FIGURE 9-7 : EXAMPLE OF ZOOM IN 5 FIGURE 2- : 68-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS 55 FIGURE 2-2 : 88-SERIES PARALLEL INTERFACE CHARACTERISTICS 56 FIGURE 2-3 : SERIAL INTERFACE CHARACTERISTICS (4-WIRE SPI) 57 FIGURE 2-4 : SERIAL INTERFACE CHARACTERISTICS (3-WIRE SPI) 58 FIGURE 2-5 : I 2 C INTERFACE TIMING CHARACTERISTICS 59 FIGURE 3- : APPLICATION EXAMPLE OF SSD36Z WITH EXTERNAL VCC AND I 2 C INTERFACE 6 FIGURE 3-2 : APPLICATION EXAMPLE OF SSD36Z WITH INTERNAL CHARGE PUMP, INTERNAL I REF AND I 2 C INTERFACE 6 FIGURE 4- : SSD36Z DIE TRAY INFORMATION 62 Solomon Systech Mar 25 P 6/63 Rev 4 SSD36

7 GENERAL DESCRIPTION SSD36 is a single-chip CMOS OLED/PLED driver with controller for organic / polymer light emitting diode dot-matrix graphic display system It consists of 28 segments and 39 commons This IC is designed for Common Cathode type OLED panel The SSD36 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption It has 256-step brightness control Data/Commands are sent from general MCU through the hardware selectable 68/88 series compatible Parallel Interface, I 2 C interface or Serial Peripheral Interface It is suitable for many compact portable applications, such as mobile phone sub-display, MP3 player and Bluetooth headset and Medical devices, etc 2 FEATURES Resolution: 28 x39 dot matrix panel Power supply o V DD = 65V ~ 33V, V BAT for IC logic o V BAT = 3V ~ 42V for charge pump regulator circuit o V CC = 7V~5V for Panel driving For matrix display OLED driving output voltage, 5V maximum Segment maximum source current: 6uA Common maximum sink current: 2mA 256 step contrast brightness current control Embedded 28 x 39 bit SRAM display buffer Pin selectable MCU Interfaces: o 8-bit 68/88-series parallel interface o 3 /4 wire Serial Peripheral Interface o I 2 C Interface Screen saving continuous scrolling function in both horizontal and vertical direction Internal charge pump regulator Internal regulated V COMH or external V COMH Internal I REF or external I REF Programmable Frame Rate Programmable Multiplexing Ratio Row Re-mapping and Column Re-mapping On-Chip Oscillator Chip layout for COG, COF Wide range of operating temperature: -4 C to 85 C 3 ORDERING INFORMATION Table 3- : Ordering Information Ordering Part Number SEG COM Package Form Remark SSD36Z COG - SSD36 Rev 4 P 7/63 Mar 25 Solomon Systech

8 4 BLOCK DIAGRAM Figure 4- : SSD36 Block Diagram RES# CS# D/C# E (RD#) R/W#(WR#) BS2 BS BS D7 D6 D5 D4 D3 D2 D D MCU Interface Graphic Display Data RAM (GDDRAM) Display Controller Segment Driver Common Driver SEG 63 SEG 62 : SEG SEG COM COM : COM37 COM38 V DD V CC V SS V LSS Command Decoder Oscillator Charge pump Regulator Current Control Voltage Control Segment Driver SEG 64 SEG 65 : SEG26 SEG27 CL CLS FR BGGND V COMH I REF V CC V BAT CN CP C2N C2P Solomon Systech Mar 25 P 8/63 Rev 4 SSD36

9 5 DIE PAD FLOOR PLAN Figure 5- : SSD36Z Die Drawing Pin Die Size (after sawing) Die Thickness Min I/O pad pitch Min SEG pad pitch Min COM pad pitch Bump Height 68mm +/- 5mm x 79mm +/- 5mm 3 um ± 5 um 6 um 32 um 4 um Nominal 2 um Bump Size Pad # X [um] Y [um] ~25, 34~63, 72~89, ~33, 64~ ~ ~7, 293~ ~78, 222~ ~ SSD36Z Alignment mark Position Size T shape (289, 95) 75um x 75um + shape (-289, 95) 75um x 75um Note () Diagram showing the Gold bumps face up (2) Coordinates are referenced to center of the chip (3) Coordinate units and size of all alignment marks are in um (4) All alignment keys do not contain gold y SSD36Z x Pad, 2, 3 -> Gold Bumps face up SSD36 Rev 4 P 9/63 Mar 25 Solomon Systech

10 Table 5- : SSD36Z Bump Die Pad Coordinates Pin number Pin name X Y Pin number Pin name X Y Pin number Pin name X Y Pin number Pin name X Y NC VCOMH SEG SEG C2N VCOMH SEG SEG C2N VCOMH SEG SEG C2N VCOMH SEG SEG C2N VCC SEG SEG C2P VCC SEG SEG C2P VCC SEG SEG C2P VCC SEG SEG C2P NC SEG SEG CP TR SEG SEG CP TR SEG SEG CP TR SEG SEG CP TR SEG SEG CN TR SEG SEG CN VSS VCC SEG CN TR VCC SEG VBAT TR VCC SEG VBAT TR VCC SEG VBAT TR VCOMH SEG VCC TR VCOMH SEG VCC NC COM SEG VCC NC COM SEG VCOMH NC COM SEG VCOMH NC COM SEG VCOMH NC COM SEG VLSS NC COM SEG VLSS NC COM SEG VLSS VCC COM SEG VLSS VCC COM SEG VSS VCC COM SEG VSS SEG COM SEG VSS SEG COM SEG VSS SEG COM SEG VDD SEG COM SEG VDD SEG COM SEG FR SEG COM SEG VSS SEG COM SEG CS# SEG COM SEG RES# SEG COM SEG D/C# SEG COM SEG VSS SEG COM SEG R/W#(WR#) SEG COM SEG E/RD# SEG COM SEG D SEG COM SEG D SEG COM SEG D SEG COM SEG D SEG COM SEG VSS SEG COM SEG D SEG COM SEG D SEG COM VCC D SEG COM VCC D SEG COM VCC CL SEG COM NC VSS SEG COM NC CLS SEG COM NC VDD SEG COM NC VDD SEG COM NC BS SEG COM NC VSS SEG COM BS SEG VCOMH VDD SEG VCOMH BS SEG VCC VSS SEG VCC BGGND SEG VCC VSS SEG VCC VSS SEG SEG VSS SEG SEG VLSS SEG SEG VLSS SEG SEG VLSS SEG SEG VLSS SEG SEG VBREF SEG SEG VSS SEG SEG VSS SEG SEG GPIO SEG SEG GPIO SEG SEG VDD SEG SEG VDD SEG SEG NC SEG SEG IREF SEG SEG Solomon Systech Mar 25 P /63 Rev 4 SSD36

11 6 PIN DESCRIPTION Key: Pin Name Type Description I = Input O =Output I/O = Bi-directional (input/output) P = Power pin Table 6- : Pin Description V DD P Power supply pin for core logic operation NC = Not Connected Pull LOW= connect to Ground Pull HIGH= connect to V DD V CC P Power supply for panel driving voltage This is also the most positive power voltage supply pin V SS P This is a ground pin V LSS P This is an analog ground pin It should be connected to V SS externally V COMH O The pin is for COM signal deselected voltage level A capacitor should be connected between this pin and V SS When external V COMH is selected, this pin must be connected to V CC Refer to command ADh for details V BAT P Power supply for charge pump regulator circuit Status V BAT V DD V CC Enable charge pump Connect to external V BAT source Connect to external V DD source A capacitor should be connected between this Disable charge pump Keep float Connect to external V DD source pin and V SS Connect to external V CC source BGGND P Reserved pin It should be connected to V SS externally CP/CN C2P/C2N O CP/CN Pin for charge pump capacitor; Connect to each other with a capacitor C2P/C2N Pin for charge pump capacitor; Connect to each other with a capacitor V BREF O Reserved pin It should be kept NC BS[2:] I MCU bus interface selection pins Please refer to Table 6-2 for the details of setting I REF I This is segment output current reference pin When external I REF is used, a resistor should be connected between this pin and V SS to maintain the I REF current at ua Please refer to Figure 7-4 for the details of resistor value When internal I REF is used, this pin should be kept NC FR O This pin outputs RAM write synchronization signal Proper timing between MCU data writing and frame display timing can be achieved to prevent tearing effect It should be kept NC if it is not used CL I This is external clock input pin When internal clock is enabled (ie HIGH in CLS pin), this pin is not used and should be connected to V SS When internal clock is disabled (ie LOW in CLS pin), this pin is the external clock source input pin SSD36 Rev 4 P /63 Mar 25 Solomon Systech

12 Pin Name Type Description CLS I This is internal clock enable pin When it is pulled HIGH (ie connect to V DD), internal clock is enabled When it is pulled LOW, the internal clock is disabled; an external clock source must be connected to the CL pin for normal operation RES# I This pin is reset signal input When the pin is pulled LOW, initialization of the chip is executed Keep this pin HIGH (ie connect to V DD) during normal operation CS# I This pin is the chip select input (active LOW) D/C# I This is Data/Command control pin When it is pulled HIGH (ie connect to V DD), the data at D[7:] is treated as data When it is pulled LOW, the data at D[7:] will be transferred to the command register In I 2 C mode, this pin acts as SA for slave address selection When 3-wire serial interface is selected, this pin must be connected to V SS E (RD#) I When interfacing to a 68-series microprocessor, this pin will be used as the Enable (E) signal Read/write operation is initiated when this pin is pulled HIGH (ie connect to V DD) and the chip is selected When connecting to an 88-series microprocessor, this pin receives the Read (RD#) signal Read operation is initiated when this pin is pulled LOW and the chip is selected When serial interface is selected, this pin must be connected to V SS R/W#(WR#) I This is read / write control input pin connecting to the MCU interface When interfacing to a 68-series microprocessor, this pin will be used as Read/Write (R/W#) selection input Read mode will be carried out when this pin is pulled HIGH (ie connect to V DD) and write mode when LOW When 88 interface mode is selected, this pin will be the Write (WR#) input Data write operation is initiated when this pin is pulled LOW and the chip is selected When serial or I 2 C interface is selected, this pin must be connected to V SS D[7:] IO These are 8-bit bi-directional data bus to be connected to the microprocessor s data bus When serial interface mode is selected, D will be the serial clock input: SCLK; D will be the serial data input: SDIN and D2 should be kept NC When I 2 C mode is selected, D2, D should be tied together and serve as SDA out, SDA in in application and D is the serial clock input, SCL GPIO/GPIO IO Reserved pin It should be kept NC TR[9:] IO Reserved pin It should be kept NC SEG ~ SEG27 COM ~ COM38 O O These pins provide Segment switch signals to OLED panel These pins are V SS state when display is OFF These pins provide Common switch signals to OLED panel They are in high impedance state when display is OFF NC - This is dummy pin Do not group or short NC pins together SSD36 Pin Name Table 6-2 : MCU Bus Interface Pin Selection I 2 C Interface 68-parallel interface (8 bit) 88-parallel interface (8 bit) 4-wire Serial interface BS BS BS2 Note () is connected to V SS (2) is connected to V DD 3-wire Serial interface Solomon Systech Mar 25 P 2/63 Rev 4 SSD36

13 7 FUNCTIONAL BLOCK DESCRIPTIONS 7 MCU Interface selection SSD36 MCU interface consist of 8 data pins and 5 control pins The pin assignment at different interface mode is summarized in Table 7- Different MCU mode can be set by hardware selection on BS[2:] pins (please refer to Table 6-2 for BS[2:] setting) Table 7- : MCU interface assignment under different bus interface mode Pin Name Data/Command Interface Control Signal Bus Interface D7 D6 D5 D4 D3 D2 D D E R/W# CS# D/C# RES# 8-bit 88 D[7:] RD# WR# CS# D/C# RES# 8-bit 68 D[7:] E R/W# CS# D/C# RES# 3-wire SPI Tie LOW NC SDIN SCLK Tie LOW CS# Tie LOW RES# 4-wire SPI Tie LOW NC SDIN SCLK Tie LOW CS# D/C# RES# I 2 C Tie LOW SDA OUT SDA IN SCL Tie LOW SA RES# 7 MCU Parallel 68-series Interface The parallel interface consists of 8 bi-directional data pins (D[7:]), R/W#, D/C#, E and CS# A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write The E input serves as data latch signal while CS# is LOW Data is latched at the falling edge of E signal Note () stands for falling edge of signal H stands for HIGH in signal L stands for LOW in signal Table 7-2 : Control pins of 68 interface Function E R/W# CS# D/C# Write command L L L Read status H L L Write data L L H Read data H L H In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read This is shown in Figure 7- SSD36 Rev 4 P 3/63 Mar 25 Solomon Systech

14 Figure 7- : Data read back procedure - insertion of dummy read R/W# E Databus N n n+ n+2 Write column address Dummy read Read st data Read 2nd data Read 3rd data 72 MCU Parallel 88-series Interface The parallel interface consists of 8 bi-directional data pins (D[7:]), RD#, WR#, D/C# and CS# A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW CS# Figure 7-2 : Example of Write procedure in 88 parallel interface mode WR# D[7:] D/C# RD# high low Figure 7-3 : Example of Read procedure in 88 parallel interface mode CS# RD# D[7:] D/C# WR# high low Solomon Systech Mar 25 P 4/63 Rev 4 SSD36

15 Table 7-3 : Control pins of 88 interface Function RD# WR# CS# D/C# Write command H L L Read status H L L Write data H L H Read data H L H Note () stands for rising edge of signal (2) H stands for HIGH in signal (3) L stands for LOW in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read This is shown in Figure 7-4 Figure 7-4 : Display data read back procedure - insertion of dummy read WR# RD# Databus N n n+ n+2 Write column address Dummy read Read st data Read 2nd data Read 3rd data 73 MCU Serial Interface (4-wire SPI) The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS# In 4-wire SPI mode, D acts as SCLK, D acts as SDIN For the unused data pins, D2 should be left open The pins from D3 to D7, E and R/W# (WR#)# can be connected to an external ground Note () H stands for HIGH in signal (2) L stands for LOW in signal (3) stands for rising edge of signal Table 7-4 : Control pins of 4-wire Serial interface Function E R/W# CS# D/C# D Write command Tie LOW Tie LOW L L Write data Tie LOW Tie LOW L H SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, D D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data RAM (GDDRAM) or command register in the same clock Under serial mode, only write operations are allowed SSD36 Rev 4 P 5/63 Mar 25 Solomon Systech

16 Figure 7-5 : Write procedure in 4-wire Serial interface mode CS# D/C# SDIN/ SCLK DB DB2 DBn SCLK (D) SDIN(D) D7 D6 D5 D4 D3 D2 D D 74 MCU Serial Interface (3-wire SPI) The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS# In 3-wire SPI mode, D acts as SCLK, D acts as SDIN For the unused data pins, D2 should be left open The pins from D3 to D7, R/W# (WR#)#, E and D/C# can be connected to an external ground The operation is similar to 4-wire serial interface while D/C# pin is not used There are altogether 9-bits will be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D bit The D/C# bit (first bit of the sequential data) will determine the following data byte in the shift register is written to the Display Data RAM (D/C# bit = ) or the command register (D/C# bit = ) Under serial mode, only write operations are allowed Table 7-5 : Control pins of 3-wire Serial interface Function E(RD#) R/W#(WR#) CS# D/C# D Note () Write command Tie LOW Tie LOW L Tie LOW L stands for LOW in signal (2) stands for rising edge of signal Write data Tie LOW Tie LOW L Tie LOW CS# Figure 7-6 : Write procedure in 3-wire Serial interface mode SDIN/ SCLK DB DB2 DBn SCLK (D) SDIN(D) D/C# D7 D6 D5 D4 D3 D2 D D Solomon Systech Mar 25 P 6/63 Rev 4 SSD36

17 75 MCU I 2 C Interface The I 2 C communication interface consists of slave address bit SA, I 2 C-bus data signal SDA (SDA OUT/D 2 for output and SDA IN/D for input) and I 2 C-bus clock signal SCL (D ) Both the data and clock signals must be connected to pull-up resistors RES# is used for the initialization of device a) Slave address bit (SA) SSD36 has to recognize the slave address before transmitting or receiving any information by the I 2 C-bus The device will respond to the slave address following by the slave address bit ( SA bit) and the read/write select bit ( R/W# bit) with the following byte format, b 7 b 6 b 5 b 4 b 3 b 2 b b SA R/W# SA bit provides an extension bit for the slave address Either or, can be selected as the slave address of SSD36 D/C# pin acts as SA for slave address selection R/W# bit is used to determine the operation mode of the I 2 C-bus interface R/W#=, it is in read mode R/W#=, it is in write mode b) I 2 C-bus data signal (SDA) SDA acts as a communication channel between the transmitter and the receiver The data and the acknowledgement are sent through the SDA It should be noticed that the ITO track resistance and the pulled-up resistance at SDA pin becomes a voltage potential divider As a result, the acknowledgement would not be possible to attain a valid logic level in SDA SDA IN and SDA OUT are tied together and serve as SDA The SDA IN pin must be connected to act as SDA The SDA OUT pin may be disconnected When SDA OUT pin is disconnected, the acknowledgement signal will be ignored in the I 2 C-bus c) I 2 C-bus clock signal (SCL) The transmission of information in the I 2 C-bus is following a clock signal, SCL Each transmission of data bit is taken place during a single clock period of SCL SSD36 Rev 4 P 7/63 Mar 25 Solomon Systech

18 75 I 2 C-bus Write data The I 2 C-bus interface gives access to write data and command into the device Please refer to Figure 7-7 for the write mode of I 2 C-bus in chronological order Figure 7-7 : I 2 C-bus data format Write mode Note: Co Continuation bit D/C# Data / Command Selection bit ACK Acknowledgement SA Slave address bit R/W# Read / Write Selection bit S Start Condition / P Stop Condition S ACK R/W# SA D/C# Co Control byte Data byte Control byte ACK D/C# Co ACK ACK Data byte P ACK Slave Address m words byte n bytes MSB LSB R/W# SA SSD36 Slave Address D/C Co ACK Control byte 752 Write mode for I2C ) The master device initiates the data communication by a start condition The definition of the start condition is shown in Figure 7-8 The start condition is established by pulling the SDA from HIGH to LOW while the SCL stays HIGH 2) The slave address is following the start condition for recognition use For the SSD36, the slave address is either b or b by changing the SA to LOW or HIGH (D/C pin acts as SA) 3) The write mode is established by setting the R/W# bit to logic 4) An acknowledgement signal will be generated after receiving one byte of data, including the slave address and the R/W# bit Please refer to the 5) 6) Figure 7-9 for the graphical representation of the acknowledge signal The acknowledge bit is defined as the SDA line is pulled down during the HIGH period of the acknowledgement related clock pulse 7) After the transmission of the slave address, either the control byte or the data byte may be sent across the SDA A control byte mainly consists of Co and D/C# bits following by six s a If the Co bit is set as logic, the transmission of the following information will contain data bytes only b The D/C# bit determines the next data byte is acted as a command or a data If the D/C# bit is set to logic, it defines the following data byte as a command If the D/C# bit is set to logic, it defines the following data byte as a data which will be stored at the GDDRAM The GDDRAM column address pointer will be increased by one automatically after each data write 8) Acknowledge bit will be generated after receiving each control byte or data byte 9) The write mode will be finished when a stop condition is applied The stop condition is also defined in Figure 7-8 The stop condition is established by pulling the SDA in from LOW to HIGH while the SCL stays HIGH Solomon Systech Mar 25 P 8/63 Rev 4 SSD36

19 Figure 7-8 : Definition of the Start and Stop Condition t HSTART t SSTOP SDA SDA SCL S P SCL START condition STOP condition Figure 7-9 : Definition of the acknowledgement condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Non-acknowledge Acknowledge SCL FROM MASTER S START Condition Clock pulse for acknowledgement Please be noted that the transmission of the data bit has some limitations The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the HIGH period of the clock pulse Please refer to the Figure 7- for graphical representations Except in start or stop conditions, the data line can be switched only when the SCL is LOW 2 Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors Figure 7- : Definition of the data transfer condition SDA SCL Data line is stable Change of data SSD36 Rev 4 P 9/63 Mar 25 Solomon Systech

20 72 Command Decoder This module determines whether the input data is interpreted as data or command Data is interpreted based upon the input of the D/C# pin If D/C# pin is HIGH, D[7:] is interpreted as display data written to Graphic Display Data RAM (GDDRAM) If it is LOW, the input at D[7:] is interpreted as a command Then data input will be decoded and written to the corresponding command register 73 Oscillator Circuit and Display Time Generator Figure 7- : Oscillator Circuit and Display Time Generator CL Internal Oscillator Fosc M U X CLK Divider DCLK Display Clock CLS This module is an on-chip LOW power RC oscillator circuitry The operation clock (CLK) can be generated either from internal oscillator or external source CL pin This selection is done by CLS pin If CLS pin is pulled HIGH, internal oscillator is chosen and CL should be connected to V SS Pulling CLS pin LOW disables internal oscillator and external clock must be connected to CL pins for proper operation When the internal oscillator is selected, its output frequency Fosc can be changed by command D5h A[7:4] The display clock (DCLK) for the Display Timing Generator is derived from CLK The division factor D can be programmed from to 6 by command D5h DCLK = F OSC / D The frame frequency of display is determined by the following formula Fosc FFRM = D K Noof Mux where D stands for clock divide ratio It is set by command D5h A[3:] The divide ratio has the range from to 6 K is the number of display clocks per row The value is derived by K = Phase period + Phase 2 period + K o = = 54 at power on reset (that is K o is a constant that equals to 5) (Please refer to Section 76 for the details of the Phase ) Number of multiplex ratio is set by command A8h The power on reset value is 38 (ie 39MUX) F OSC is the oscillator frequency It can be changed by command D5h A[7:4] The higher the register setting results in higher frequency Solomon Systech Mar 25 P 2/63 Rev 4 SSD36

21 74 FR synchronization FR synchronization signal can be used to prevent tearing effect One frame FR % Memory Access Process % Time Fast write MCU Slow write MCU SSD36 displaying memory updates to OLED screen The starting time to write a new image to OLED driver is depended on the MCU writing speed If MCU can finish writing a frame image within one frame period, it is classified as fast write MCU For MCU needs longer writing time to complete (more than one frame but within two frames), it is a slow write one For fast write MCU: MCU should start to write new frame of ram data just after rising edge of FR pulse and should be finished well before the rising edge of the next FR pulse For slow write MCU: MCU should start to write new frame ram data after the falling edge of the st FR pulse and must be finished before the rising edge of the 3 rd FR pulse 75 Reset Circuit When RES# input is LOW, the chip is initialized with the following status: Display is OFF 2 28 x 39 Display Mode 3 Normal segment and display data column address and row address mapping (SEG mapped to address h and COM mapped to address h) 4 Shift register data clear in serial interface 5 Display start line is set at display RAM address 6 Column address counter is set at 7 Normal scan direction of the COM outputs 8 Contrast control register is set at 7Fh 9 Normal display mode (Equivalent to A4h command) SSD36 Rev 4 P 2/63 Mar 25 Solomon Systech

22 76 Segment Drivers / Common Drivers Segment drivers deliver 28 current sources to drive the OLED panel The driving current can be adjusted by altering the registers of the contrast setting command (8h) Common drivers generate voltage-scanning pulses The segment driving waveform is divided into three phases: In phase, the OLED pixel charges of previous image are discharged in order to prepare for next image content display 2 In phase 2, the OLED pixel is driven to the targeted voltage The pixel is driven to attain the corresponding voltage level from V SS The period of phase 2 can be programmed in length from to 5 DCLKs If the capacitance value of the pixel of OLED panel is larger, a longer period is required to charge up the capacitor to reach the desired voltage 3 In phase 3, the OLED driver switches to use current source to drive the OLED pixels and this is the current drive stage Figure 7-2 : Segment Output Waveform in three phases V SS Phase: 2 3 Time After finishing phase 3, the driver IC will go back to phase to display the next row image data This threestep cycle is run continuously to refresh image display on OLED panel In phase 3, if the length of current drive pulse width is set to 5, after finishing 5 DCLKs in current drive phase, the driver IC will go back to phase for next row display Solomon Systech Mar 25 P 22/63 Rev 4 SSD36

23 77 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed The size of the RAM is 28 x 39 bits and the RAM is divided into five pages, from PAGE to PAGE4, which are used for monochrome 28 x 39 dot matrix display, as shown in Figure 7-3 When one data byte is written into GDDRAM, all the rows image data of the same page of the current column are filled (ie the whole column (8 bits) pointed by the column address pointer is filled) Data bit D is written into the top row, while data bit D7 is written into bottom row For PAGE4, bit D7 is treated as don t care bit For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software For vertical shifting of the display, an internal register storing the display start line can be set to control the portion of the RAM data to be mapped to the display (command D3h) Figure 7-3 : GDDRAM pages structure of SSD36 Segment remapping (command Ah) SEG27 SEG26 SEG25 SEG24 SEG4 SEG3 SEG2 SEG SEG Segment remapping (command Ah [RESET]) Page SEG COL SEG COL SEG2 COL2 SEG3 COL3 SEG23 COL23 SEG24 COL24 SEG25 COL25 SEG26 COL26 SEG27 COL27 COM Output Scan Direction (command Ch [RESET]) COM Output Scan Direction (command C8h) Data D COM COM38 D COM COM37 D2 COM2 COM36 D3 COM3 COM35 D4 COM4 COM34 D5 COM5 COM33 D6 COM6 COM32 D7 COM7 COM3 D COM8 COM3 D COM9 COM29 D2 COM COM28 D3 COM COM27 D4 COM2 COM26 D5 COM3 COM25 D6 COM4 COM24 D7 COM5 COM23 D COM6 COM22 D Each box represents one bit COM7 COM2 D2 of image data COM8 COM2 D3 COM9 COM9 D4 COM2 COM8 D5 COM2 COM7 D6 COM22 COM6 D7 COM23 COM5 D COM24 COM4 D COM25 COM3 D2 COM26 COM2 D3 COM27 COM D4 COM28 COM D5 COM29 COM9 D6 COM3 COM8 D7 COM3 COM7 D COM32 COM6 D COM33 COM5 D2 COM34 COM4 D3 COM35 COM3 D4 COM36 COM2 D5 COM37 COM D6 COM38 COM D7 Don't care bit SSD36 Rev 4 P 23/63 Mar 25 Solomon Systech

24 78 SEG/COM Driving block This block is used to derive the incoming power sources into the different levels of internal use voltage and current V CC is the most positive voltage supply V LSS is the ground path of the analog and panel current V COMH is the Common deselected level It can be internally regulated or externally connect to V CC Bit A[] of command ADh is used to select external or internal V COMH: A[] = Select internal V COMH regulator [Reset] When internal V COMH is selected, a capacitor should be connected between V COMH and V SS A[] = Select external V COMH When external V COMH is used, V COMH must be connected to V CC I REF is a reference current source for segment current drivers I SEG The relationship between reference current and segment current of a color is: I SEG = Contrast / 256 x I REF x scale factor in which the contrast (~255) is set by Set Contrast command (8h) When internal I REF is used, the I REF pin should be kept NC Bit A[4] of command ADh is used to select external or internal I REF : A[4] = Select external I REF [Reset] A[4] = Enable internal I REF during display ON When external I REF is used, the magnitude of I REF is controlled by the value of resistor, which is connected between I REF pin and VSS as shown in Figure 7-4 It is recommended to set I REF to ± 2uA so as to achieve I SEG = 6uA at maximum contrast 255 Figure 7-4 : I REF Current Setting by Resistor Value SSD36 I REF ~ ua R I REF (voltage at this pin V CC 5) V SS Since the voltage at I REF pin is V CC 5V, the value of resistor R can be found as below: For I REF = ua, V CC =2V: R = (Voltage at I REF V SS) / I REF (2 5) / ua = 7kΩ Solomon Systech Mar 25 P 24/63 Rev 4 SSD36

25 79 Power ON and OFF sequence The following figures illustrate the recommended power ON and power OFF sequence of SSD36 : 79 Power ON and OFF sequence with External VCC Power ON sequence: Power ON V DD 2 After V DD become stable, set RES# pin LOW (logic low) for at least 3us (t ) (4) and then HIGH (logic high) 3 After set RES# pin LOW (logic low), wait for at least 3us (t 2) Then Power ON V CC () 4 After V CC become stable, send command AFh for display ON SEG/COM will be ON after ms (t AF) Figure 7-5 : The Power ON sequence ON V DD RES# ON V CC Send AFh command for Display ON V DD OFF RES# t GND t 2 V CC OFF t AF SEG/COM ON OFF Power OFF sequence: Send command AEh for display OFF 2 Power OFF V CC (2), (3) 3 Power OFF V DD after t OFF (5) (Typical t OFF=5ms) Send command AEh for display OFF V CC Figure 7-6 : The Power OFF sequence OFF V CC OFF V DD OFF V DD OFF Note: () After RES# pin LOW for at least 3us (t 2), V CC should only power ON after RES# pin goes high (2) V CC should be kept float (ie disable) when it is OFF (3) Power Pins (V DD, V CC) can never be pulled to ground under any circumstance (4) The register values are reset after t (5) V DD should not be Power OFF before V CC Power OFF t OFF SSD36 Rev 4 P 25/63 Mar 25 Solomon Systech

26 792 Power ON and OFF sequence with Charge Pump Application Power ON sequence: Power ON V DD 2 Wait for t ON Power ON V BAT (), (2) (where Minimum t ON = ms) 3 After V BAT become stable, set RES# pin LOW (logic low) for at least 3us (t ) (3) and then HIGH (logic high) 4 After set RES# pin LOW (logic low), wait for at least 3us (t 2) Then input commands with below sequence: a 8Dh 4h for enabling charge pump b AFh for display ON 5 SEG/COM will be ON after ms (t AF) Figure 7-7 : The Power ON sequence with Charge Pump Application V DD ON V DD ON V BAT RES# Send 8Dh 4h command for enabling charge pump Send AFh command for display ON OFF V BAT OFF RES# t ON t GND t 2 t AF SEG/COM ON OFF Power OFF sequence: Send command AEh for display OFF 2 Send command 8Dh h to disable charge pump 3 Power OFF V BAT after t OFF (), (2) (Typical t OFF =5ms) 4 Power OFF V DD after t OFF2 (where Minimum t OFF2 = ms (4), Typical t OFF2=5ms) V BAT Figure 7-8 : The Power OFF sequence with Charge Pump Application Send command AEh for display OFF Send command 8Dh h to disable charge pump t OFF OFF V BAT OFF V DD OFF t OFF2 V DD OFF Note: () V BAT should be kept float (ie disable) when it is OFF (2) Power Pins (V DD, V BAT) can never be pulled to ground under any circumstance (3) The register values are reset after t (4) V DD should not be Power OFF before V BAT Power OFF Solomon Systech Mar 25 P 26/63 Rev 4 SSD36

27 7 Charge Pump Regulator The internal regulator circuit in SSD36 accompanying only 2 external capacitors can generate a 9V voltage supply, V CC and a maximum output loading of 2mA from a low voltage supply input, V BAT The V CC is the voltage supply to the OLED driver block This regulator can be turned ON/OFF by software command 8Dh setting 8 COMMAND TABLE Table 8-: SSD36 Command Table (R/W#(WR#) =, E(RD#) = unless specific setting is stated) Fundamental Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description 8 Set Contrast Double byte command to select one of the A[7:] A 7 A 6 A 5 A 4 A 3 A 2 A A Control contrast steps Contrast increases as the value increases (RESET = 7Fh ) A[7:] valid range: h to FFh A4/A5 X Entire Display A4h, X[]: Resume to RAM content display ON (RESET) Output follows RAM content A5h, X[]: Entire display ON Output ignores RAM content A6/A7 X Set Normal/Inver se Display A6h, X[]=b: Normal display (RESET) in RAM: OFF in display panel in RAM: ON in display panel A7h, X[]=b: Inverse display in RAM: ON in display panel in RAM: OFF in display panel AD A[7:] A 4 A External or Internal V COMH Selection / External or internal I REF Selection Select external or internal V COMH : A[] = Select internal V COMH (RESET) A[] = Enable external V COMH Select external or internal I REF : A[4] = Select external I REF (RESET) A[4] = Enable internal I REF during display ON AE AF X Set Display ON/OFF Note () Refer to section 78 for details AEh, X[]=b:Display OFF (sleep mode) (RESET) AFh X[]=b:Display ON in normal mode SSD36 Rev 4 P 27/63 Mar 25 Solomon Systech

28 2 Scrolling Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description 26/27 A[7:] B[2:] C[2:] D[2:] E[7:] F[7:] F 6 F 5 F 4 F 3 B 2 C 2 D 2 F 2 B C D F X B C D F Continuous Horizontal Scroll Setup 26h, X[]=, Right Horizontal Scroll 27h, X[]=, Left Horizontal Scroll (Horizontal scroll by column) A[7:] : Dummy byte (Set as h) B[2:] : Define start page address G[7:] G 6 G 5 G 4 G 3 G 2 G G b b b invalid PAGE PAGE3 b b b invalid PAGE b PAGE2 PAGE4 b invalid C[2:] : Set time interval between each scroll step in terms of frame frequency b 6 frames b 3 frames b 32 frames b 4 frames b 64 frames b 5 frame b 28 frames b 2 frame D[2:] : Define end page address b b b invalid PAGE PAGE3 b PAGE b PAGE4 b invalid b b invalid PAGE2 The value of D[2:] must be larger or equal to B[2:] E[7:] : Dummy byte (Set as h) F[7:] : Define start column address (d-27d) G[7:] : Define end column address (d-27d) The value of G[2:] must be larger or equal to F[2:] 29/2A A[2:] B[2:] C[2:] D[2:] E[5:] F[7:] G[7:] F 6 G 6 E 5 F 5 G 5 E 4 F 4 G 4 E 3 F 3 G 3 B 2 C 2 D 2 E 2 F 2 G 2 X B C D E F G X A B C D E F G Continuous Vertical and Horizontal Scroll Setup 29h, X X =b : Vertical and Right Horizontal Scroll 2Ah, X X =b : Vertical and Left Horizontal Scroll A[7:] : Horizontal scrolling offset A[] =, no offset A[] =, scroll by column Solomon Systech Mar 25 P 28/63 Rev 4 SSD36

29 2 Scrolling Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description B[2:] : Define start page address b PAGE b PAGE3 b invalid b PAGE b PAGE4 b invalid b b invalid PAGE2 C[2:] : Set time interval between each scroll step in terms of frame frequency b 6 frames b 3 frames b 32 frames b 4 frames b 64 frames b 5 frame b 28 frames b 2 frame D[2:] : Define end page address b PAGE b PAGE3 b invalid b PAGE b PAGE4 b invalid b b invalid PAGE2 The value of D[2:] must be larger or equal to B[2:] E[5:] : Vertical scrolling offset eg E[5:]= h refer to offset = row E[5:] =26h refer to offset =38 rows F[7:] : Define start column address (d-27d) G[7:] : Define end column address (d-27d) The value of G[2:] must be larger or equal to F[2:] 2E Deactivate scroll Stop scrolling that is configured by command 26h/27h/29h/2Ah Note () After sending 2Eh command to deactivate the scrolling action, the ram data needs to be rewritten SSD36 Rev 4 P 29/63 Mar 25 Solomon Systech

30 2 Scrolling Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description 2F Activate scroll Start scrolling that is configured by the scrolling setup commands :26h/27h/29h/2Ah with the following valid sequences: Valid command sequence : 26h ;2Fh Valid command sequence 2: 27h ;2Fh Valid command sequence 3: 29h ;2Fh Valid command sequence 4: 2Ah ;2Fh For example, if 26h; 2Ah; 2Fh commands are issued, the setting in the last scrolling setup command, ie 2Ah in this case, will be executed In other words, setting in the last scrolling setup command overwrites the setting in the previous scrolling setup commands A3 A[5:] B[5:] A 5 B 5 A 4 B 4 A 3 B 3 A 2 B 2 A B A B Set Vertical Scroll Area A[5:] : Set No of rows in top fixed area The No of rows in top fixed area is referenced to the top of the GDDRAM (ie row )[RESET = d] B[5:] : Set No of rows in scroll area This is the number of rows to be used for vertical scrolling The scroll area starts in the first row below the top fixed area [RESET = 39d] Note () A[5:]+B[5:] <= MUX ratio (2) B[5:] <= MUX ratio (3a) Vertical scrolling offset (E[5:] in 29h/2Ah) < B[5:] (3b) Set Display Start Line (X5X4X3X2XX of 4h~66h) < B[5:] (4) The last row of the scroll area shifts to the first row of the scroll area (5) For 39d MUX display A[5:] =, B[5:]=39 : whole area scrolls A[5:]=, B[5:] < 39 : top area scrolls A[5:] + B[5:] < 39 : central area scrolls A[5:] + B[5:] = 39 : bottom area scrolls Solomon Systech Mar 25 P 3/63 Rev 4 SSD36

31 2 Scrolling Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description 2C/2D A[7:] B[2:] C[7:] D[2:] E[7:] F[7:] G[7:] F 7 G 7 F 6 G 6 F 5 G 5 F 4 G 4 F 3 G 3 B 2 D 2 F 2 G 2 B D F G X B D F G Content Scroll Setup 2Ch, X[]=, Right Horizontal Scroll by one column 2Dh, X[]=, Left Horizontal Scroll by one column A[7:] : Dummy byte (Set as h) B[2:] : Define start page address b b b invalid PAGE PAGE3 b b b invalid PAGE b PAGE2 PAGE4 b invalid C[7:] : Dummy byte (Set as h) D[2:] : Define end page address b b b invalid PAGE PAGE3 b PAGE b PAGE4 b invalid b b invalid PAGE2 E[7:] : Dummy byte (Set as h) F[7:] : Define start column (RESET = h) G[7:] : Define end column (RESET = 7Fh) Note () The value of D[2:] must be larger than or equal to B[2:] (2) The value of G[7:] must be larger than F[7:] (3) A delay time of 2 frame frequency must be set if sending the command of 2Ch / 2Dh consecutively 3 Addressing Setting Command Table D/C#Hex D7 D6 D5 D4 D3 D2 D D Command Description ~F X 3 X 2 X X Set Lower Column Set the lower nibble of the column start Start Address for Page Addressing Mode address register for Page Addressing Mode using X[3:] as data bits The initial display line register is reset to b after RESET Note () This command is only for page addressing mode SSD36 Rev 4 P 3/63 Mar 25 Solomon Systech

32 3 Addressing Setting Command Table D/C#Hex D7 D6 D5 D4 D3 D2 D D Command Description ~7 X 2 X X Set Higher Column Set the higher nibble of the column start Start Address for Page Addressing Mode address register for Page Addressing Mode using X[2:] as data bits The initial display line register is reset to b after RESET Note () This command is only for page addressing mode 2 A[:] A A Set Memory Addressing Mode A[:] = b, Horizontal Addressing Mode A[:] = b, Vertical Addressing Mode A[:] = b, Page Addressing Mode (RESET) A[:] = b, Invalid 2 A[6:] B[6:] A 6 B 6 A 5 B 5 A 4 B 4 A 3 B 3 A 2 B 2 A B A B Set Column Address Setup column start and end address A[6:] : Column start address, range : -27d, (RESET=d) B[6:]: Column end address, range : -27d, (RESET =27d) Note () This command is only for horizontal or vertical addressing mode 22 A[2:] B[2:] A 2 B 2 A B A B Set Page Address Setup page start and end address A[2:] : Page start Address, range : -4d, (RESET = d) B[2:] : Page end Address, range : -4d, (RESET = 4d) Note () This command is only for horizontal or vertical addressing mode B~B4 X 2 X X Set Page Start Address for Page Addressing Mode Set GDDRAM Page Start Address (PAGE~PAGE4) for Page Addressing Mode using X[2:] Note () This command is only for page addressing mode 4 Hardware Configuration (Panel resolution & layout related) Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description 4~66 X 5 X 4 X 3 X 2 X X Set Display Start Line Set display RAM display offset from d-38d using X 5X 4X 3X 2X X Display offset is reset to b during RESET A/A X Set Segment Remap Ah, X[]=b: column address is mapped to SEG (RESET) Ah, X[]=b: column address 27 is mapped to SEG Solomon Systech Mar 25 P 32/63 Rev 4 SSD36

33 4 Hardware Configuration (Panel resolution & layout related) Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description A8 A[5:] A 5 A 4 A 3 A 2 A A Set Multiplex Ratio Set MUX ratio to N+ MUX N=A[5:] : from 8MUX to 39MUX, RESET= b (ie38d, 39Mux) A[5:] from to 7 are invalid entry C/C8 X 3 Set COM Output Scan Direction Ch, X[3]=b: normal mode (RESET) Scan from COM to COM[N ] C8h, X[3]=b: remapped mode Scan from COM[N-] to COM Where N is the Multiplex ratio D3 A[5:] A 5 A 4 A 3 A 2 A A Set Display Offset Set vertical shift by COM from d~38d The value is reset to h after RESET DA A[5:4] A 5 A 4 Set SEG Pins Hardware Configuration A[4]=b, Sequential SEG pin configuration A[4]=b(RESET), Alternative (odd/even) SEG pin configuration A[5]=b(RESET), Disable SEG Left/Right remap A[5]=b, Enable SEG Left/Right remap Table 8-2 : SEG Pins Hardware Configuration SEG Odd / Even (Left / Right) and Top / Bottom connections are software selectable, thus there are total of 8 cases and they are shown on the followings, Case Oddeven () / Sequential () SEG Remap Left / Right Swap Remark no Command : DAh -> A[4] Command : Ah / Ah Command : DAh -> A[5] Default COL27 COL26 COL27 COL26 COL64 COL64 COL63 COL COL COL63 COL62 COL G M G E O E S SSD36Z C S SEG COM SEG G M G E O E S SSD36Z C S SEG COM SEG () Sequential SEG (2) Sequential SEG & left / right SSD36 Rev 4 P 33/63 Mar 25 Solomon Systech

34 COL COL COL COL COL63 COL64 COL26 COL27 COL63 COL64 COL65 COL G M SSD36Z E S C O G E S SEG COM SEG (3) Sequential SEG & SEG remap G E S M G O E SSD36Z C S SEG COM SEG (4) Sequential SEG & SEG remap & left / right COL27 COL3 COL26 COL2 COL26 COL2 COL27 COL25 COL COL COL COL G E S SEG COM M C O SSD36Z G E S SEG (5) Odd / even SEG (6) Odd / even SEG & left / right G E S M O C SEG COM SSD36Z G E S SEG COL COL2 COL26 COL COL3 COL27 COL COL25 COL27 COL COL2 COL26 G E S M O C SEG COM SSD36Z G E S SEG G E S SEG COM M C O SSD36Z G E S SEG (7) Odd / even SEG & SEG remap (8) Odd / even SEG & SEG remap & left / right Note: () The above eight figures are all with bump pads being faced up Solomon Systech Mar 25 P 34/63 Rev 4 SSD36

35 5 Timing & Driving scheme Setting Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description D5 A[7:] A 7 A 6 A 5 A 4 A 3 A 2 A A Set Display Clock Divide Ratio/Oscillator Frequency A[3:] : Define the divide ratio (D) of the display clocks (DCLK): Divide ratio= A[3:] +, RESET is b (divide ratio = 2) A[7:4] : Set the Oscillator Frequency, F OSC Oscillator Frequency increases with the value of A[7:4] and vice versa RESET is b Range:b~b Frequency increases as setting value increases D9 A[7:] A 7 A 6 A 5 A 4 A 3 A 2 A A Set Pre-charge Period A[3:] : Phase period of up to 5 DCLK clocks is invalid entry (RESET=2h) A[7:4] : Phase 2 period of up to 5 DCLK clocks is invalid entry (RESET=2h ) DB A[6:4] A 6 A 5 A 4 Set V COMH Deselect Level A[6:4] Hex code V COMH deselect level b h ~ 65 x V CC b 2h ~ 77 x V CC (RESET) b 3h ~ 83 x V CC SSD36 Rev 4 P 35/63 Mar 25 Solomon Systech

36 6 Advance Graphic Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description 23 A[6:] A 5 A 4 A 3 A 2 A A Set Fade Out and Blinking A[5:4] = b Disable Fade Out / Blinking Mode[RESET] A[5:4] = b Enable Fade In mode Once Fade In Mode is enabled, contrast increase gradually to original contrast setting Output follows RAM content when Fade mode is disabled A[5:4] = b Enable Fade Out mode Once Fade Out Mode is enabled, contrast decrease gradually to all pixels OFF Output follows RAM content when Fade mode is disabled A[5:4] = b Enable Blinking mode Once Blinking Mode is enabled, contrast decrease gradually to all pixels OFF and than contrast increase gradually to normal display This process loop continuously until the Blinking mode is disabled A[3:] : Set time interval for each fade step A[3:] b b b b Time interval for each fade step 8 Frames 6 Frames 24 Frames : 28 Frames Note () Refer to section 93 for details D6 A[] A Set Zoom In A[] = b Disable Zoom in Mode[RESET] A[] = b Enable Zoom in Mode Note () The panel must be in alternative COM pin configuration (command DAh A[4] =) (2) Refer to section 932 for details Solomon Systech Mar 25 P 36/63 Rev 4 SSD36

37 7 Charge Pump Command Table D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description 8D A[7:] A 2 A Charge Pump Setting A[] = b, Select 9V charge pump output (RESET) A[] = b, Select 75V charge pump output A[2] = b, Disable charge pump(reset) A[2] = b, Enable charge pump during display on Note () The Charge Pump must be enabled by the following command sequence: 8Dh ; Charge Pump Setting 4h / 5h ; Enable Charge Pump AFh; Display ON 8 Others D/C# Hex D7 D6 D5 D4 D3 D2 D D Command Description E3 NOP Command for no operation Note () stands for Don t care Table 8-3 : Read Command Table Bit Pattern Command Description D 7D 6D 5D 4D 3D 2D D Status Register Read D[7] : Reserved D[6] : for display OFF / for display ON D[5] : Reserved D[4] : Reserved D[3] : Reserved D[2] : Reserved D[] : Reserved D[] : Reserved Note () Patterns other than those given in the Command Table are prohibited to enter the chip as a command; as unexpected results can occur 8 Data Read / Write To read data from the GDDRAM, select HIGH for both the R/W# (WR#) pin and the D/C# pin for 68- series parallel mode and select LOW for the E (RD#) pin and HIGH for the D/C# pin for 88-series parallel mode No data read is provided in serial mode operation In normal data read mode the GDDRAM column address pointer will be increased automatically by one after each data read Also, a dummy read is required before the first data read To write data to the GDDRAM, select LOW for the R/W# (WR#) pin and HIGH for the D/C# pin for both 68-series parallel mode and 88-series parallel mode The serial interface mode is always in write mode The GDDRAM column address pointer will be increased automatically by one after each data write Table 8-4 : Address increment table (Automatic) D/C# R/W# (WR#) Comment Address Increment Write Command No Read Status No Write Data Yes Read Data Yes SSD36 Rev 4 P 37/63 Mar 25 Solomon Systech

38 9 COMMAND DESCRIPTIONS 9 Fundamental Command 9 Set Lower Column Start Address for Page Addressing Mode (h~fh) This command specifies the lower nibble of the 8-bit column start address for the display data RAM under Page Addressing Mode The column address will be incremented by each data access Please refer to Table 8- and Section 93 for details 92 Set Higher Column Start Address for Page Addressing Mode (h~7h) This command specifies the higher nibble of the 8-bit column start address for the display data RAM under Page Addressing Mode The column address will be incremented by each data access Please refer to Table 8- and Section 93 for details 93 Set Memory Addressing Mode (2h) There are 3 different memory addressing mode in SSD36: page addressing mode, horizontal addressing mode and vertical addressing mode This command sets the way of memory addressing into one of the above three modes In there, COL means the graphic display data RAM column Page addressing mode (A[:]=xb) In page addressing mode, after the display RAM is read / written, the column address pointer is increased automatically by If the column address pointer reaches column end address, the column address pointer is reset to column start address and page address pointer is not changed Users have to set the new page and column addresses in order to access the next page RAM content The sequence of movement of the PAGE and column address point for page addressing mode is shown in Figure 9- Figure 9- : Address Pointer Movement of Page addressing mode PAGE PAGE PAGE2 PAGE3 PAGE4 COL COL COL 26 COL 27 In normal display data RAM read or write and page addressing mode, the following steps are required to define the starting RAM access pointer location: Set the page start address of the target display location by command Bh to B4h Set the lower start column address of pointer by command h~fh Set the upper start column address of pointer by command h~7h For example, if the page address is set to B2h, lower column address is 3h and upper column address is h, then that means the starting column is SEG3 of PAGE2 The RAM access pointer is located as shown in Figure 9-2 The input data byte will be written into RAM position of column 3 Figure 9-2 : Example of GDDRAM access pointer setting in Page Addressing Mode (No row and column-remapping) SEG SEG3 (Starting column) SEG27 RAM access pointer PAGE2 (Starting page) LSB D MSB D7 Each box represents one bit of image data COM6 COM7 : : : : : COM23 Solomon Systech Mar 25 P 38/63 Rev 4 SSD36

39 Horizontal addressing mode (A[:]=b) In horizontal addressing mode, after the display RAM is read / written, the column address pointer is increased automatically by If the column address pointer reaches column end address, the column address pointer is reset to column start address and page address pointer is increased by The sequence of movement of the page and column address point for horizontal addressing mode is shown in Figure 9-3 When both column and page address pointers reach the end address, the pointers are reset to column start address and page start address (Dotted line in Figure 9-3) Figure 9-3 : Address Pointer Movement of Horizontal addressing mode PAGE PAGE PAGE2 PAGE3 PAGE4 COL COL COL 26 COL 27 Vertical addressing mode: (A[:]=b) In vertical addressing mode, after the display RAM is read / written, the page address pointer is increased automatically by If the page address pointer reaches the page end address, the page address pointer is reset to page start address and column address pointer is increased by The sequence of movement of the page and column address point for vertical addressing mode is shown in Figure 9-4 When both column and page address pointers reach the end address, the pointers are reset to column start address and page start address (Dotted line in Figure 9-4) Figure 9-4 : Address Pointer Movement of Vertical addressing mode COL COL COL 26 COL 27 PAGE PAGE PAGE2 PAGE3 PAGE4 In normal display data RAM read or write and horizontal / vertical addressing mode, the following steps are required to define the RAM access pointer location: Set the column start and end address of the target display location by command 2h Set the page start and end address of the target display location by command 22h Example is shown in Figure Set Column Address (2h) This triple byte command specifies column start address and end address of the display data RAM This command also sets the column address pointer to column start address This pointer is used to define the current read/write column address in graphic display data RAM If horizontal address increment mode is enabled by command 2h, after finishing read/write one column data, it is incremented automatically to the next column address Whenever the column address pointer finishes accessing the end column address, it is reset back to start column address and the row address is incremented to the next row SSD36 Rev 4 P 39/63 Mar 25 Solomon Systech

40 95 Set Page Address (22h) This triple byte command specifies page start address and end address of the display data RAM This command also sets the page address pointer to page start address This pointer is used to define the current read/write page address in graphic display data RAM If vertical address increment mode is enabled by command 2h, after finishing read/write one page data, it is incremented automatically to the next page address Whenever the page address pointer finishes accessing the end page address, it is reset back to start page address The figure below shows the way of column and page address pointer movement through the example: column start address is set to 2 and column end address is set to 97, page start address is set to and page end address is set to 2; Horizontal address increment mode is enabled by command 2h In this case, the graphic display data RAM column accessible range is from column 2 to column 97 and from page to page 2 only In addition, the column address pointer is set to 2 and page address pointer is set to After finishing read/write one pixel of data, the column address is increased automatically by to access the next RAM location for next read/write operation (solid line in Figure 9-5) Whenever the column address pointer finishes accessing the end column 97, it is reset back to column 2 and page address is automatically increased by (solid line in Figure 9-5) While the end page 2 and end column 97 RAM location is accessed, the page address is reset back to and the column address is reset back to 2 (dotted line in Figure 9-5) Figure 9-5 : Example of Column and Row Address Pointer Movement PAGE PAGE PAGE2 PAGE3 PAGE4 Col Col Col 2 Col 97 Col98 Col 26 Col Set Display Start Line (4h~66h) This command sets the Display Start Line register to determine starting address of display RAM, by selecting a value from to 38 With value equal to, RAM row is mapped to COM With value equal to, RAM row is mapped to COM and so on Refer to Table 9- for more illustrations 97 Set Contrast Control (8h) This command sets the Contrast Setting of the display, with a valid range from h to FFh The segment output current increases as the contrast step value increases 98 Set Segment Re-map (Ah/Ah) This command changes the mapping between the display data column address and the segment driver It allows flexibility in OLED module design Please refer to Table 8-2 This command only affects subsequent data input Data already stored in GDDRAM will have no changes Solomon Systech Mar 25 P 4/63 Rev 4 SSD36

41 99 Entire Display ON (A4h/A5h) A4h command enable display outputs according to the GDDRAM contents If A5h command is issued, then by using A4h command, the display will resume to the GDDRAM contents In other words, A4h command resumes the display from entire display ON stage A5h command forces the entire display to be ON, regardless of the contents of the display data RAM 9 Set Normal/Inverse Display (A6h/A7h) This command sets the display to be either normal or inverse In normal display a RAM data of indicates an ON pixel while in inverse display a RAM data of indicates an ON pixel 9 Set Multiplex Ratio (A8h) This command switches the default 39 multiplex mode to any multiplex ratio, ranging from 8 to 39 The output pads COM~COM38 will be switched to the corresponding COM signal 92 External or Internal VCOMH Selection / External or internal IREF Selection (ADh) This double byte command consists of two functions: External or Internal V COMH Selection (A[]) Default A[] =, Select internal V COMH When A[] =, Select external V COMH When external V COMH is selected, the V COMH pin must be connected to V CC External or Internal I REF Selection (A[4]) Default A[4] =, Select external I REF When A[4] =, Select internal I REF during display ON Refer to Section 78 for details 93 Set Display ON/OFF (AEh/AFh) These single byte commands are used to turn the OLED panel display ON or OFF When the display is ON, the selected circuits by Set Master Configuration command will be turned ON When the display is OFF, those circuits will be turned OFF and the segment and common output are in V SS state and high impedance state, respectively These commands set the display to one of the two states: AEh : Display OFF AFh : Display ON Figure 9-6 : Transition between different modes AFh Normal mode Sleep mode AEh 94 Set Page Start Address for Page Addressing Mode (Bh~B4h) This command positions the page start address from to 4 in GDDRAM under Page Addressing Mode Please refer to Table 8- and Section 93 for details SSD36 Rev 4 P 4/63 Mar 25 Solomon Systech

42 95 Set COM Output Scan Direction (Ch/C8h) This command sets the scan direction of the COM output, allowing layout flexibility in the OLED module design Additionally, the display will show once this command is issued For example, if this command is sent during normal display, then the graphic display will be vertically flipped immediately Please refer to Figure 9-7 and Table 9-2 for details Figure 9-7 : Example of row address mapping SEG2 SEG SSD36 COM38 COM37 : : COM COM SEG SEG3 SEG2 SEG SSD36 COM38 COM37 : : COM COM SEG SEG3 Row maps to COM pin Row 38 maps to COM pin 96 Set Display Offset (D3h) This is a double byte command The second command specifies the mapping of the display start line to one of COM~COM38 (assuming that COM is the display start line then the display start line register is equal to ) For example, to move the COM4 towards the COM direction by 4 lines the 6-bit data in the second byte should be given as b To move in the opposite direction by 4 lines the 6-bit data should be given by 39 4, so the second byte would be b The following two tables (Table 9-, Table 9-2) show the examples of setting the command Ch/C8h and D3h Solomon Systech Mar 25 P 42/63 Rev 4 SSD36

43 Table 9- : Example of Set Display Offset and Display Start Line without Remap Output Set MUX ration (A8h) Normal Normal Normal Normal Normal Normal COM normal / remap (Ch / C8h) Hardware 4 4 Display offset (D3h) pin name 4 4 Display start line (4h - 66h) COM ROW RAM ROW4 RAM4 ROW RAM4 ROW RAM ROW4 RAM4 ROW RAM4 COM ROW RAM ROW5 RAM5 ROW RAM5 ROW RAM ROW5 RAM5 ROW RAM5 COM2 ROW2 RAM2 ROW6 RAM6 ROW2 RAM6 ROW2 RAM2 ROW6 RAM6 ROW2 RAM6 COM3 ROW3 RAM3 ROW7 RAM7 ROW3 RAM7 ROW3 RAM3 ROW7 RAM7 ROW3 RAM7 COM4 ROW4 RAM4 ROW8 RAM8 ROW4 RAM8 ROW4 RAM4 ROW8 RAM8 ROW4 RAM8 COM5 ROW5 RAM5 ROW9 RAM9 ROW5 RAM9 ROW5 RAM5 ROW9 RAM9 ROW5 RAM9 COM6 ROW6 RAM6 ROW RAM ROW6 RAM ROW6 RAM6 ROW RAM ROW6 RAM COM7 ROW7 RAM7 ROW RAM ROW7 RAM ROW7 RAM7 ROW RAM ROW7 RAM COM8 ROW8 RAM8 ROW2 RAM2 ROW8 RAM2 ROW8 RAM8 ROW2 RAM2 ROW8 RAM2 COM9 ROW9 RAM9 ROW3 RAM3 ROW9 RAM3 ROW9 RAM9 ROW3 RAM3 ROW9 RAM3 COM ROW RAM ROW4 RAM4 ROW RAM4 ROW RAM ROW4 RAM4 ROW RAM4 COM ROW RAM ROW5 RAM5 ROW RAM5 ROW RAM ROW5 RAM5 ROW RAM5 COM2 ROW2 RAM2 ROW6 RAM6 ROW2 RAM6 ROW2 RAM2 ROW6 RAM6 ROW2 RAM6 COM3 ROW3 RAM3 ROW7 RAM7 ROW3 RAM7 ROW3 RAM3 ROW7 RAM7 ROW3 RAM7 COM4 ROW4 RAM4 ROW8 RAM8 ROW4 RAM8 ROW4 RAM4 ROW8 RAM8 ROW4 RAM8 COM5 ROW5 RAM5 ROW9 RAM9 ROW5 RAM9 ROW5 RAM5 ROW9 RAM9 ROW5 RAM9 COM6 ROW6 RAM6 ROW2 RAM2 ROW6 RAM2 ROW6 RAM6 ROW2 RAM2 ROW6 RAM2 COM7 ROW7 RAM7 ROW2 RAM2 ROW7 RAM2 ROW7 RAM7 ROW2 RAM2 ROW7 RAM2 COM8 ROW8 RAM8 ROW22 RAM22 ROW8 RAM22 ROW8 RAM8 ROW22 RAM22 ROW8 RAM22 COM9 ROW9 RAM9 ROW23 RAM23 ROW9 RAM23 ROW9 RAM9 ROW23 RAM23 ROW9 RAM23 COM2 ROW2 RAM2 ROW24 RAM24 ROW2 RAM24 ROW2 RAM2 ROW24 RAM24 ROW2 RAM24 COM2 ROW2 RAM2 ROW25 RAM25 ROW2 RAM25 ROW2 RAM2 ROW25 RAM25 ROW2 RAM25 COM22 ROW22 RAM22 ROW26 RAM26 ROW22 RAM26 ROW22 RAM22 ROW26 RAM26 ROW22 RAM26 COM23 ROW23 RAM23 ROW27 RAM27 ROW23 RAM27 ROW23 RAM23 ROW27 RAM27 ROW23 RAM27 COM24 ROW24 RAM24 ROW28 RAM28 ROW24 RAM28 ROW24 RAM24 ROW28 RAM28 ROW24 RAM28 COM25 ROW25 RAM25 ROW29 RAM29 ROW25 RAM29 ROW25 RAM25 ROW29 RAM29 ROW25 RAM29 COM26 ROW26 RAM26 ROW3 RAM3 ROW26 RAM3 ROW26 RAM26 ROW3 RAM3 ROW26 RAM3 COM27 ROW27 RAM27 ROW3 RAM3 ROW27 RAM3 ROW27 RAM27 ROW3 RAM3 ROW27 RAM3 COM28 ROW28 RAM28 ROW32 RAM32 ROW28 RAM32 ROW28 RAM ROW28 RAM32 COM29 ROW29 RAM29 ROW33 RAM33 ROW29 RAM33 ROW29 RAM ROW29 RAM33 COM3 ROW3 RAM3 ROW34 RAM34 ROW3 RAM34 ROW3 RAM3 - - ROW3 RAM34 COM3 ROW3 RAM3 ROW35 RAM35 ROW3 RAM35 ROW3 RAM3 - - ROW3 RAM35 COM32 ROW32 RAM32 ROW36 RAM36 ROW32 RAM COM33 ROW33 RAM33 ROW37 RAM37 ROW33 RAM COM34 ROW34 RAM34 ROW38 RAM38 ROW34 RAM COM35 ROW35 RAM35 ROW RAM ROW35 RAM - - ROW RAM - - COM36 ROW36 RAM36 ROW RAM ROW36 RAM - - ROW RAM - - COM37 ROW37 RAM37 ROW2 RAM2 ROW37 RAM2 - - ROW2 RAM2 - - COM38 ROW38 RAM38 ROW3 RAM3 ROW38 RAM3 - - ROW3 RAM3 - - Display examples (a) (b) (c) (d) (e) (f) (a) (b) (c) (d) (e) (f) (RAM) SSD36 Rev 4 P 43/63 Mar 25 Solomon Systech

44 Table 9-2 : Example of Set Display Offset and Display Start Line with Remap Output Set MUX ration (A8h) Remap Remap Remap Remap Remap Remap Remap COM normal / remap (Ch / C8h) Hardware Display offset (D3h) pin name Display start line (4h - 66h) COM ROW38 RAM 38 ROW3 RAM3 ROW38 RAM3 ROW3 RAM3 - - ROW3 RAM COM ROW37 RAM37 ROW2 RAM2 ROW37 RAM2 ROW3 RAM3 - - ROW3 RAM COM2 ROW36 RAM36 ROW RAM ROW36 RAM ROW29 RAM ROW29 RAM COM3 ROW35 RAM35 ROW RAM ROW35 RAM ROW28 RAM ROW28 RAM COM4 ROW34 RAM34 ROW38 RAM38 ROW34 RAM38 ROW27 RAM27 ROW3 RAM3 ROW27 RAM3 ROW3 RAM COM5 ROW33 RAM33 RAM37 RAM37 ROW33 RAM37 ROW26 RAM26 ROW3 RAM3 ROW26 RAM3 ROW3 RAM38 COM6 ROW32 RAM32 RAM36 RAM36 ROW32 RAM36 ROW25 RAM25 ROW29 RAM29 ROW25 RAM29 ROW29 RAM37 COM7 ROW3 RAM3 RAM35 RAM35 ROW3 RAM35 ROW24 RAM24 ROW28 RAM28 ROW24 RAM28 ROW28 RAM36 COM8 ROW3 RAM3 RAM34 RAM34 ROW3 RAM34 ROW23 RAM23 ROW27 RAM27 ROW23 RAM27 ROW27 RAM35 COM9 ROW29 RAM29 RAM33 RAM33 ROW29 RAM33 ROW22 RAM22 ROW26 RAM26 ROW22 RAM26 ROW26 RAM34 COM ROW28 RAM28 RAM32 RAM32 ROW28 RAM32 ROW2 RAM2 ROW25 RAM25 ROW2 RAM25 ROW25 RAM33 COM ROW27 RAM27 RAM3 RAM3 ROW27 RAM3 ROW2 RAM2 ROW24 RAM24 ROW2 RAM24 ROW24 RAM32 COM2 ROW26 RAM26 RAM3 RAM3 ROW26 RAM3 ROW9 RAM9 ROW23 RAM23 ROW9 RAM23 ROW23 RAM3 COM3 ROW25 RAM25 RAM29 RAM29 ROW25 RAM29 ROW8 RAM8 ROW22 RAM22 ROW8 RAM22 ROW22 RAM3 COM4 ROW24 RAM24 RAM28 RAM28 ROW24 RAM28 ROW7 RAM7 ROW2 RAM2 ROW7 RAM2 ROW2 RAM29 COM5 ROW23 RAM23 RAM27 RAM27 ROW23 RAM27 ROW6 RAM6 ROW2 RAM2 ROW6 RAM2 ROW2 RAM28 COM6 ROW22 RAM22 RAM26 RAM26 ROW22 RAM26 ROW5 RAM5 ROW9 RAM9 ROW5 RAM9 ROW9 RAM27 COM7 ROW2 RAM2 RAM25 RAM25 ROW2 RAM25 ROW4 RAM4 ROW8 RAM8 ROW4 RAM8 ROW8 RAM26 COM8 ROW2 RAM2 RAM24 RAM24 ROW2 RAM24 ROW3 RAM3 ROW7 RAM7 ROW3 RAM7 ROW7 RAM25 COM9 ROW9 RAM9 RAM23 RAM23 ROW9 RAM23 ROW2 RAM2 ROW6 RAM6 ROW2 RAM6 ROW6 RAM24 COM2 ROW8 RAM8 RAM22 RAM22 ROW8 RAM22 ROW RAM ROW5 RAM5 ROW RAM5 ROW5 RAM23 COM2 ROW7 RAM7 RAM2 RAM2 ROW7 RAM2 ROW RAM ROW4 RAM4 ROW RAM4 ROW4 RAM22 COM22 ROW6 RAM6 RAM2 RAM2 ROW6 RAM2 ROW9 RAM9 ROW3 RAM3 ROW9 RAM3 ROW3 RAM2 COM23 ROW5 RAM5 RAM9 RAM9 ROW5 RAM9 ROW8 RAM8 ROW2 RAM2 ROW8 RAM2 ROW2 RAM2 COM24 ROW4 RAM4 RAM8 RAM8 ROW4 RAM8 ROW7 RAM7 ROW RAM ROW7 RAM ROW RAM9 COM25 ROW3 RAM3 RAM7 RAM7 ROW3 RAM7 ROW6 RAM6 ROW RAM ROW6 RAM ROW RAM8 COM26 ROW2 RAM2 RAM6 RAM6 ROW2 RAM6 ROW5 RAM5 ROW9 RAM9 ROW5 RAM9 ROW9 RAM7 COM27 ROW RAM RAM5 RAM5 ROW RAM5 ROW4 RAM4 ROW8 RAM8 ROW4 RAM8 ROW8 RAM6 COM28 ROW RAM RAM4 RAM4 ROW RAM4 ROW3 RAM3 ROW7 RAM7 ROW3 RAM7 ROW7 RAM5 COM29 ROW9 RAM9 RAM3 RAM3 ROW9 RAM3 ROW2 RAM2 ROW6 RAM6 ROW2 RAM6 ROW6 RAM4 COM3 ROW8 RAM8 RAM2 RAM2 ROW8 RAM2 ROW RAM ROW5 RAM5 ROW RAM5 ROW5 RAM3 COM3 ROW7 RAM7 RAM RAM ROW7 RAM ROW RAM ROW4 RAM4 ROW RAM4 ROW4 RAM2 COM32 ROW6 RAM6 RAM RAM ROW6 RAM - - ROW3 RAM3 - - ROW3 RAM COM33 ROW5 RAM5 RAM9 RAM9 ROW5 RAM9 - - ROW2 RAM2 - - ROW2 RAM COM34 ROW4 RAM4 RAM8 RAM8 ROW4 RAM8 - - ROW RAM - - ROW RAM9 COM35 ROW3 RAM3 RAM7 RAM7 ROW3 RAM7 - - ROW RAM - - ROW RAM8 COM36 ROW2 RAM2 RAM6 RAM6 ROW2 RAM COM37 ROW RAM RAM5 RAM5 ROW RAM COM38 ROW RAM ROW4 RAM4 ROW RAM Display examples (a) (b) (c) (d) (e) (f) (g) (a) (b) (c) (d) (e) (f) (g) (RAM) Solomon Systech Mar 25 P 44/63 Rev 4 SSD36

45 97 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) This command consists of two functions: Display Clock Divide Ratio (D) (A[3:]) Set the divide ratio to generate DCLK (Display Clock) from CLK The divide ratio is from to 6, with reset value = b Please refer to section 73 for the details relationship of DCLK and CLK Oscillator Frequency (A[7:4]) Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high The 4-bit value results in 6 different frequency settings available as shown below The default setting is b 98 Set Pre-charge Period (D9h) This command is used to set the duration of the pre-charge period The interval is counted in number of DCLK, where RESET equals to 2 DCLKs 99 Set COM Pins Hardware Configuration (DAh) This command sets the COM signals pin configuration to match the OLED panel hardware layout Table 8-2 shows the COM pin configuration under different conditions (for MUX ratio = 39) 92 Set V COMH Deselect Level (DBh) This command adjusts the VCOMH regulator output 92 NOP (E3h) No Operation Command 922 Status register Read This command is issued by setting D/C# ON LOW during a data read (See Figure 2- to Figure 2-2 for parallel interface waveform) It allows the MCU to monitor the internal status of the chip No status read is provided for serial mode 923 Charge Pump Setting (8Dh) This command controls the ON/OFF of the Charge Pump The Charge Pump must be enabled by the following command sequence: 8Dh ; Charge Pump Setting 4h or 5h; Enable Charge Pump at selectable 9V mode or 75V mode AFh; Display ON SSD36 Rev 4 P 45/63 Mar 25 Solomon Systech

46 92 Graphic Acceleration Command 92 Horizontal Scroll Setup (26h/27h) This command consists of 7 consecutive bytes to set up the horizontal scroll parameters and determines the scrolling start page, end page, start column, end column and scrolling speed Before issuing this command the horizontal scroll must be deactivated (2Eh) Otherwise, RAM content may be corrupted The SSD36 horizontal scroll is designed for 28 columns scrolling The following two figures (Figure 9-8, Figure 9-9, and Figure 9-) show the examples of using the horizontal scroll: Figure 9-8 : Horizontal scroll example: Scroll RIGHT by column Original Setting SEG SEG SEG2 SEG3 SEG4 SEG5 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 After one scroll step SEG27 SEG SEG SEG2 SEG3 SEG4 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 Figure 9-9 : Horizontal scroll example: Scroll LEFT by column Original Setting SEG SEG SEG2 SEG3 SEG4 SEG5 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 After one scroll step SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG23 SEG24 SEG25 SEG26 SEG27 SEG Figure 9- : Horizontal scrolling setup example Solomon Systech Mar 25 P 46/63 Rev 4 SSD36

47 922 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah) This command consists of 7 consecutive bytes to set up the continuous vertical scroll parameters and determines the scrolling start page, end page, start column, end column, scrolling speed, horizontal and vertical scrolling offset The bytes A[], B[2:], C[2:], D[2:], E[5:], F[6:] and G[6:] of command 29h/2Ah are for the setting of the continuous horizontal scrolling The byte E[5:] is for the setting of the continuous vertical scrolling offset All these bytes together are for the setting of continuous diagonal (horizontal + vertical) scrolling If the vertical scrolling offset byte E[5:] is set to zero, then only horizontal scrolling is performed (like command 26/27h) Before issuing this command the scroll must be deactivated (2Eh) Otherwise, RAM content may be corrupted The following figure (Figure 9- ) show the example of using the continuous vertical and horizontal scroll: Figure 9- : Continuous Vertical and Horizontal scrolling setup example 923 Deactivate Scroll (2Eh) This command stops the motion of scrolling After sending 2Eh command to deactivate the scrolling action, the ram data needs to be rewritten 924 Activate Scroll (2Fh) This command starts the motion of scrolling and should only be issued after the scroll setup parameters have been defined by the scrolling setup commands: 26h / 27h / 29h / 2Ah The setting in the latest scrolling setup command overwrites the setting in the previous scrolling setup command The following actions are prohibited after the scrolling is activated RAM access (Data write or read) 2 Changing the horizontal scroll setup parameters 925 Set Vertical Scroll Area (A3h) This command consists of 3 consecutive bytes to set up the vertical scroll area For the continuous vertical scroll function (command 29h / 2Ah), the number of rows in the vertical scroll area can be set smaller than or equating to the MUX ratio Figure 9-2 shows some vertical scrolling example with different settings in vertical scroll area SSD36 Rev 4 P 47/63 Mar 25 Solomon Systech

48 Figure 9-2 : Vertical scroll area setup examples 926 Content Scroll Setup (2Ch/2Dh) This command consists of seven consecutive bytes to set up the horizontal scroll parameters and determine the scrolling start page, end page, start column and end column One column will be scrolled horizontally by sending the setting of command 2Ch / 2Dh once When command 2Ch / 2Dh are sent consecutively, a delay time of Frame Frequency of 2 must be set Figure 9-3 shown an example of using 2Dh Content Scroll Setup command for horizontal scrolling to left with infinite content update In there, Col means the graphic display data RAM column Solomon Systech Mar 25 P 48/63 Rev 4 SSD36

49 Figure 9-3: Content Scrolling example (2Dh, Left Horizontal Scroll by one column) Left horizontal scroll Page 3 Solo Page Hav Col 8 Col 2 Page 3 Solomon Sys Page Have a nice Col 8 Col 2 Page 3 Solomon Systech Page Have a nice da Col 8 Col 2 End column Scrolling window Beginning column By using command 2Ch/2Dh, RAM contents are scrolled and updated by one column Table 9-3 is an example of content scrolling setting of SSD36 (scrolling window of 4 pages) The values of registers depend on different conditions and applications Table 9-3 : Content Scrolling software flow example (Page addressing mode command 2h, 2h) Step Action D/C# Code Remarks For i= to n - - Create For loop for infinite content scrolling 2 Set Content scrolling command (scrolling window : Page to 3, Col 8 to Col 2) 2Dh Left Horizontal Scroll by one column h A[7:] : Dummy byte (Set as h) h B[2:] : Define start page address h C[7:] : Dummy byte (Set as h) 3h D[2:] : Define end page address h E[7:] : Dummy byte (Set as h) 8h F[6:] : Define start column address 78h G[6:] : Define end column address 3 Add Delay time of 2 FrameFreq - - Eg Delay 2ms if frame freq Hz 4 Write RAM on the beginning column of the scrolling window Write RAM on (Page, Col 2) (Content update in beginning column) Write RAM on (Page, Col 2) (Content update in beginning column) Write RAM on (Page2, Col 2) (Content update in beginning column) Write RAM on (Page3, Col 2) (Content update in beginning column) Bh Set Page Start Address for Page Addressing Mode 7h Set Higher Column Start Address for Page Addressing Mode 8h Set Lower Column Start Address for Page Addressing Mode - Write data to fill the RAM Bh Set Page Start Address for Page Addressing Mode 7h Set Higher Column Start Address for Page Addressing Mode 8h Set Lower Column Start Address for Page Addressing Mode - Write data to fill the RAM B2h Set Page Start Address for Page Addressing Mode 7h Set Higher Column Start Address for Page Addressing Mode 8h Set Lower Column Start Address for Page Addressing Mode - Write data to fill the RAM B3h Set Page Start Address for Page Addressing Mode 7h Set Higher Column Start Address for Page Addressing Mode 8h Set Lower Column Start Address for Page Addressing Mode - Write data to fill the RAM 5 i=i+ - - Go to next For loop Delay timing - - Set time interval between each scroll step if necessary End SSD36 Rev 4 P 49/63 Mar 25 Solomon Systech

50 There are 3 different memory addressing mode in SSD36: page addressing mode, horizontal addressing mode and vertical addressing mode and it is selected by command 2h Table 9-3 is an example of content scrolling software flow under page addressing mode, while vertical addressing mode example is shown in below Table 9-4 Table 9-4 : Content Scrolling setting example (Vertical addressing mode command 2h, h) Step Action D/C# Code Remarks For i= to n - - Create For loop for infinite content scrolling 2 Set Content scrolling command (scrolling window : Page to 3, Col 8 to Col 2) 2Dh Left Horizontal Scroll by one column h A[6:] : Dummy byte (Set as h) h B[2:] : Define start page address h C[2:] : Dummy byte (Set as h) 3h D[2:] : Define end page address h E[6:] : Dummy byte (Set as h) 8h F[6:] : Define start column address 78h G[6:] : Define end column address 3 Add Delay time of 2 FrameFreq - - Eg Delay 2ms if frame freq Hz 4 Write RAM on the beginning column of the scrolling window (Page to 3, Col 2) (Content update in beginning column) 2h Set Column address 78h Set column start address for Vertical Addressing Mode 78h Set column end address for Vertical Addressing Mode 22h Set Page address h Set start page address for Vertical Addressing Mode 3h Set end page address for Vertical Addressing Mode - Write data to fill the RAM 5 i=i+ - - Go to next For loop Delay timing - - Set time interval between each scroll step if necessary End Solomon Systech Mar 25 P 5/63 Rev 4 SSD36

51 93 Advance Graphic Command 93 Set Fade Out / Fade In and Blinking (23h) This command allow to set the fade mode and adjust the time interval for each fade step Below figures show the example of Fade Out mode and Blinking mode Figure 9-4 : Example of Fade Out mode Figure 9-5 : Example of Fade In mode Figure 9-6 : Example of Blinking mode 932 Set Zoom In (D6h) Under Zoom in mode, one row of display contents is expanded into two rows on the display That is, contents of row~3 fill the whole display panel of 39 rows It should be notice that the panel must be in alternative COM pin configuration (command DAh A[4] =) for zoom in function Figure 9-7 : Example of Zoom In SSD36 Rev 4 P 5/63 Mar 25 Solomon Systech

52 MAXIMUM RATINGS Table - : Maximum Ratings (Voltage Referenced to V SS) Symbol Parameter Value Unit V DD -3 to +4 V V BAT Supply Voltage -3 to +5 V V CC to 6 V V SEG SEG output voltage to V CC V V COM COM output voltage to 9V CC V V in Input voltage V SS-3 to V DD+3 V T A Operating Temperature -4 to +85 ºC T stg Storage Temperature Range -65 to +5 ºC Maximum ratings are those values beyond which damages to the device may occur Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section This device may be light sensitive Caution should be taken to avoid exposure of this device to any light source during normal operation This device is not radiation protected Solomon Systech Mar 25 P 52/63 Rev 4 SSD36

53 DC CHARACTERISTICS Condition (Unless otherwise specified): Voltage referenced to V SS, V DD =65 V to 33V, T A = 25 C Table - : DC Characteristics Symbol Parameter Test Condition Min Typ Max Unit V CC Operating Voltage V V DD Logic Supply Voltage V Charge Pump Regulator V V BAT Charge Pump V CC Supply Voltage Charge Pump Output Voltage ITO resistance <3ohm for charge pump related pins () V BAT = 3V~42V, Output loading = 8mA V BAT = 38V~42V, Output loading = 2mA V V V OH High Logic Output Level I OUT = ua, 33MHz 9 x V DD - - V V OL Low Logic Output Level I OUT = ua, 33MHz - - x V DD V V IH High Logic Input Level - 8 x V DD - - V V IL Low Logic Input Level x V DD V Sleep mode Current V DD = 65V~33V, V CC = 7V~5V - - ua I DD,SLEEP I CC,SLEEP I CC I DD I SEG Dev Adj Dev Sleep mode Current V CC Supply Current V DD = 28V, V CC =2V, Internal I REF, No loading, Display ON, All ON V DD Supply Current V DD =28V, V CC = 2V, Internal I REF, No loading, Display ON, All ON, Segment Output Current, V DD = 28V, V CC=2V, I REF=uA Display ON Segment output current uniformity Adjacent pin output current uniformity (contrast setting = FFh) Display OFF, No panel attached V DD = 65V~33V, V CC = 7V~5V Display OFF, No panel attached Contrast = FFh - - ua Contrast=FFh Contrast=AFh - - Contrast=7Fh Contrast=3Fh Contrast=Fh - - Dev = (I SEG I MID)/I MID I MID = (I MAX + I MIN)/2 I SEG[:27] = Segment current at contrast setting = FFh Adj Dev = (I[n]-I[n+]) / (I[n]+I[n+]) ua ua ua -3-3 % -2-2 % Remarks: () Charge pump related pins include: V BAT, CP, CN, C2P, C2N, V LSS SSD36 Rev 4 P 53/63 Mar 25 Solomon Systech

54 2 AC CHARACTERISTICS Conditions: Voltage referenced to V SS V DD=65 to33v T A = 25 C Table 2- : AC Characteristics Symbol Parameter Test Condition Min Typ Max Unit F () OSC Oscillation Frequency of V DD = 28V khz Display Timing Generator FFRM Frame Frequency for 39 28x39 Graphic Display Mode, - F OSC x - Hz MUX Mode Display ON, Internal Oscillator Enabled /(DxKx39) (2) RES# Reset low pulse width us Note () FOSC stands for the frequency value of the internal oscillator and the value is measured when command D5h A[7:4] is in default value (2) D: divide ratio (default value = 2) K: number of display clocks per row period (default value = 54) Table 2-2 : 68-Series MCU Parallel Interface Timing Characteristics (V DD - V SS = 65V to 33V, T A = 25 C) Symbol Parameter Min Typ Max Unit t cycle Clock Cycle Time ns t AS Address Setup Time - - ns t AH Address Hold Time - - ns t DSW Write Data Setup Time ns t DHW Write Data Hold Time ns t DHR Read Data Hold Time ns t OH Output Disable Time ns t ACC Access Time ns PW CSL PW CSH Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) ns - - ns t R Rise Time ns t F Fall Time ns Solomon Systech Mar 25 P 54/63 Rev 4 SSD36

55 Figure 2- : 68-series MCU parallel interface characteristics D/C# t AS t AH R/W# E t cycle PW CSH CS# PW CSL t R t F t DSW t DHW D[7:](WRITE) Valid Data t ACC t DHR D[7:](READ) Valid Data t OH SSD36 Rev 4 P 55/63 Mar 25 Solomon Systech

56 Table 2-3 : 88-Series MCU Parallel Interface Timing Characteristics (V DD - V SS = 65V ~33V, T A = 25 C) Symbol Parameter Min Typ Max Unit t cycle Clock Cycle Time ns t AS Address Setup Time - - ns t AH Address Hold Time - - ns t DSW Write Data Setup Time ns t DHW Write Data Hold Time ns t DHR Read Data Hold Time ns t OH Output Disable Time ns t ACC Access Time ns t PWLR Read Low Time ns t PWLW Write Low Time ns t PWHR Read High Time ns t PWHW Write High Time ns t R Rise Time ns t F Fall Time ns t CS Chip select setup time - - ns t CSH Chip select hold time to read signal - - ns t CSF Chip select hold time ns Figure 2-2 : 88-series parallel interface characteristics CS# Write cycle t CS t CSF D/C# t AS t AH WR# t F t PWLW t R t cycle t PWHW t DSW t DHW D[7:] Read Cycle CS# t CSH t CS D/C# t AS t AH RD# t F t PWLR t R t cycle t PWHR t ACC t DHR D[7:] t OH Solomon Systech Mar 25 P 56/63 Rev 4 SSD36

57 Table 2-4 : Serial Interface Timing Characteristics (4-wire SPI) (V DD - V SS = 65V~33V, T A = 25 C) Symbol Parameter Min Typ Max Unit t cycle Clock Cycle Time - - ns t AS Address Setup Time ns t AH Address Hold Time ns t CSS Chip Select Setup Time ns t CSH Chip Select Hold Time ns t DSW Write Data Setup Time ns t DHW Write Data Hold Time ns t CLKL Clock Low Time ns t CLKH Clock High Time ns t R Rise Time ns t F Fall Time ns Figure 2-3 : Serial interface characteristics (4-wire SPI) D/C# t AS t AH CS# t CSS t CSH t CLKL t cycle t CLKH SCLK(D) t F t R t DSW t DHW SDIN(D) Valid Data CS# SCLK(D) SDIN(D) D7 D6 D5 D4 D3 D2 D D SSD36 Rev 4 P 57/63 Mar 25 Solomon Systech

58 (V DD - V SS = 65V~33V, T A = 25 C) Table 2-5 : Serial Interface Timing Characteristics (3-wire SPI) Symbol Parameter Min Typ Max Unit t cycle Clock Cycle Time - - ns t CSS Chip Select Setup Time ns t CSH Chip Select Hold Time - - ns t DSW Write Data Setup Time ns t DHW Write Data Hold Time ns t CLKL Clock Low Time ns t CLKH Clock High Time ns t R Rise Time ns t F Fall Time ns Figure 2-4 : Serial interface characteristics (3-wire SPI) CS# t CSS t CSH SCLK (D) t CLKL t CYCLE t CLKH t F t DSW t R t DHW CS# SDIN (D) Valid Data SCLK (D) SDIN (D) D/C# D7 D6 D5 D4 D3 D2 D D Solomon Systech Mar 25 P 58/63 Rev 4 SSD36

59 Conditions: V DD - V SS = 65V ~ 33V T A = 25 C Table 2-6 : I 2 C Interface Timing Characteristics Symbol Parameter Min Typ Max Unit t cycle Clock Cycle Time us t HSTART Start condition Hold Time us t HD Data Hold Time (for SDA OUT pin) - - ns Data Hold Time (for SDA IN pin) ns t SD Data Setup Time - - ns t SSTART Start condition Setup Time (Only relevant for a repeated Start condition) us t SSTOP Stop condition Setup Time us t R Rise Time for data and clock pin ns t F Fall Time for data and clock pin ns t IDLE Idle Time before a new transmission can start us Figure 2-5 : I 2 C interface Timing characteristics SDA // // thstart thd tr tf tsd tsstart tsstop tidle SCL tcycle SSD36 Rev 4 P 59/63 Mar 25 Solomon Systech

60 3 APPLICATION EXAMPLES Figure 3- : Application Example of SSD36Z with External V CC and I 2 C Interface The configuration for I 2 C interface mode is shown in the following diagram: (V DD=28V, V CC =2V, I REF=uA) DISPLAY PANEL 28 x 39 SEG26 SEG24 SEG2 SEG COM COM COM37 COM38 SEG SEG3 SEG25 SEG27 SSD36Z V V CC V COMH I REF D2 D D RES# V DD V SS V LSS C C2 R C3 R P R P VCC SDA SCL RES# VDD GND Pin connected to MCU interface: D[2:], RES# Pin internally connected to V SS: D[7:3], BS, BS2, E, R/W#, CS#, CL, BGGND Pin internally connected to V DD: BS, CLS VBREF, FR should be left open D/C# acts as SA for slave address selection (3) C, C2: 22uF () C3: uf () place close to IC VDD and VSS pins on PCB R P : Pull up resistor Voltage at I REF = V CC 5V For V CC = 2V, I REF = ua: R = (Voltage at I REF - V SS) / I REF (2-5)V / ua = 7KΩ Note () The capacitor value is recommended value Select appropriate value against module application (2) Die gold bump face down (3) Refer to Section 75 for details (4) VLSS and VSS are not recommended to be connected on the ITO routing, but connected together in the PCB level at one common ground point for better grounding and noise insulation Solomon Systech Mar 25 P 6/63 Rev 4 SSD36

61 Figure 3-2 : Application Example of SSD36Z with Internal Charge Pump, Internal IREF and I 2 C interface The configuration for I 2 C interface mode is shown in the following diagram: (V DD=28V, V BAT =38V, Internal I REF) DISPLAY PANEL 28 x 39 COM62 COM6 COM2 COM SEG SEG27 COM COM3 COM6 COM63 SSD36Z V CC V COMH D2 D D RES# V DD V SS V LSS V BAT CN CP C2P C2N C2 C C3 C4 C5 C6 R P R P SDA SCL RES# V DD GND V BAT Pin connected to MCU interface: RES#, D[2:] Pin internally connected to V SS: BS, BS2, CL, D[7:3], E, R/W#, CS#, D/C#, BGGND Pin internally connected to V DD: BS, CLS I REF, V BREF, FR should be left open C, C2: 22uF () C3, C4 : uf () C5, C6: uf/v () R P : Pull up resistor Note () The capacitor value is recommended value Select appropriate value against module application (2) VLSS and VSS are not recommended to be connected on the ITO routing, but connected together in the PCB level at one common ground point for better grounding and noise insulation SSD36 Rev 4 P 6/63 Mar 25 Solomon Systech

62 4 PACKAGE INFORMATION 4 DIE TRAY DIMENSIONS Figure 4- : SSD36Z die tray information Solomon Systech Mar 25 P 62/63 Rev 4 SSD36

63 Solomon Systech reserves the right to make changes without notice to any products herein Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters, including Typical must be validated for each customer application by the customer s technical experts Solomon Systech does not convey any license under its patent rights nor the rights of others Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part The product(s) listed in this datasheet comply with Directive 2/65/EU of the European Parliament and of the council of 8 June 2 on the restriction of the use of certain hazardous substances in electrical and electronic equipment and People s Republic of China Electronic Industry Standard SJ/T Requirements for concentration limits for certain hazardous substances in electronic information products ( 电子信息产品中有毒有害物质的限量要求 ) Hazardous Substances test report is available upon request With collaboration of SSD36 Rev 4 P 63/63 Mar 25 Solomon Systech