CS252 S05 1. Review from last lecture. CSE820 Lec 2 - Introduction. Outline. Review: Computer Architecture brings. Moore s Law: 2X transistors / year

Transcription

1 Review from last lecture CSE80 Lec - Introduction Rich Enbody ased on slides by David Patterson Computer rchitecture >> instruction sets Computer rchitecture skill sets are different 5 Quantitative principles of design Quantitative approach to design Solid interfaces that really work Technology tracking and anticipation Computer Science at the crossroads from sequential to parallel computing Salvation requires innovation in many fields, including computer architecture Review: Computer rchitecture brings Other fields often borrow ideas from architecture Quantitative Principles of Design. Take dvantage of Parallelism. Principle of Locality 3. Focus on the Common Case 4. mdahl s Law 5. The Processor Performance Equation Careful, quantitative comparisons Define, quantity, and summarize relative performance Define and quantity relative cost Define and quantity dependability Define and quantity power Culture of anticipating and exploiting advances in technology Culture of well-defined interfaces that are carefully impleed and thoroughly checked 3 Outline Technology Trends: Culture of tracking, anticipating and exploiting advances in technology. Define, quantity, and summarize relative performance. Define and quantity relative cost 3. Define and quantity dependability 4. Define and quantity power 4 Moore s Law: X transistors / year Cramming More Components onto Integrated Circuits Gordon Moore, Electronics, 965 # on transistors / cost-effective integrated circuit double every N months ( N 4) 5 Tracking Technology Performance Trends Drill down into 4 technologies: s, Memory, Network, Processors Compare ~980 rchaic (Nostalgic) vs. ~000 Modern (Newfangled) Performance Milestones in each technology Compare for andwidth vs. Latency improves in performance over time andwidth: number of events per unit time E.g., M bits / second over network, M bytes / second from disk Latency: elapsed time for a single event E.g., one-way network delay in microseconds, average disk access time in milliseconds 6 CS5 S05

2 s: rchaic(nostalgic) v. Modern(Newfangled) Latency Lags andwidth (for last ~0 years) CDC Wren I, RPM 0.03 Gytes capacity Tracks/Inch: 800 its/inch: 9550 Three 5.5 platters andwidth: 0.6 Mytes/sec Latency: 48.3 ms Cache: none Seagate , RPM (4X) 73.4 Gytes (500X) Tracks/Inch: (80X) its/inch: 533,000 (60X) Four.5 platters (in 3.5 form factor) andwidth: 86 Mytes/sec (40X) Latency: 5.7 ms (8X) Cache: 8 Mytes Relative W : 3600, 5400, 700, 0000, 5000 RPM (8x, 43x) (latency = simple operation w/o contention W = best-case) 8 Memory: rchaic (Nostalgic) v. Modern (Newfangled) 980 DRM (asynchronous) 0.06 Mbits/chip 64,000 xtors, 35 mm 6-bit data bus per module, 6 pins/chip 3 Mbytes/sec Latency: 5 ns (no block transfer) 000 Double Data Rate Synchr. (clocked) DRM Mbits/chip (4000X) 56,000,000 xtors, 04 mm 64-bit data bus per DIMM, 66 pins/chip (4X) 600 Mbytes/sec (0X) Latency: 5 ns (4X) lock transfers (page mode) 9 Latency Lags andwidth (last ~0 years) Relative Memory W Memory Module: 6bit plain DRM, Page Mode DRM, 3b, 64b, SDRM, DDR SDRM (4x,0x) : 3600, 5400, 700, 0000, 5000 RPM (8x, 43x) (latency = simple operation w/o contention W = best-case) 0 LNs: rchaic (Nostalgic)v. Modern (Newfangled) Ethernet 80.3 Year of Standard: Mbits/s link speed Latency: 3000 µsec Shared media Coaxial cable Coaxial Cable: Plastic Covering raided outer conductor Insulator Copper core Ethernet 80.3ae Year of Standard: 003 0,000 Mbits/s (000X) link speed Latency: 90 µsec (5X) Switched media Category 5 copper wire "Cat 5" is 4 twisted pairs in bundle Twisted Pair: Copper, mm thick, twisted to avoid antenna effect Latency Lags andwidth (last ~0 years) Relative Memory W 00 0 Network 0 00 Ethernet: 0Mb, 00Mb, 000Mb, 0000 Mb/s (6x,000x) Memory Module: 6bit plain DRM, Page Mode DRM, 3b, 64b, SDRM, DDR SDRM (4x,0x) : 3600, 5400, 700, 0000, 5000 RPM (8x, 43x) (latency = simple operation w/o contention W = best-case) CS5 S05

3 CPUs: rchaic (Nostalgic) v. Modern (Newfangled) Latency Lags andwidth (last ~0 years) 98 Intel MHz MIPS (peak) Latency 30 ns 34,000 xtors, 47 mm 6-bit data bus, 68 pins Microcode interpreter, separate FPU chip (no caches) 00 Intel Pentium MHz (0X) 4500 MIPS (peak) (50X) Latency 5 ns (0X) 4,000,000 xtors, 7 mm 64-bit data bus, 43 pins 3-way superscalar, Dynamic translate to RISC, Superpipelined ( stage), Out-of-Order execution On-chip 8K Data caches, 96K Instr. Trace cache, 56K L cache CPU high, Memory low ( Memory Wall ) 000 Relative Memory W 00 0 Processor Network 0 00 Processor: 86, 386, 486, Pentium, Pentium Pro, Pentium 4 (x,50x) Ethernet: 0Mb, 00Mb, 000Mb, 0000 Mb/s (6x,000x) Memory Module: 6bit plain DRM, Page Mode DRM, 3b, 64b, SDRM, DDR SDRM (4x,0x) : 3600, 5400, 700, 0000, 5000 RPM (8x, 43x) 4 Rule of Thumb for Latency Lagging W In the time that bandwidth doubles, latency improves by no more than a factor of. to.4 (and capacity improves faster than bandwidth) Stated alternatively: andwidth improves by more than the square of the improve in Latency Computers in the News Intel loses market share in own backyard, y Tom Krazit, CNET News.com, /8/006 Intel's share of the U.S. retail PC market fell by percentage points, from 64.4 percent in the fourth quarter of 004 to 53.3 percent. Current nalysis' market share numbers measure U.S. retail sales only, and therefore exclude figures from Dell, which uses its Web site to sell directly to consumers. MD chips were found in 5.5 percent of desktop PCs sold in U.S. retail stores during that period. Technical advantages of MD Opteron/thlon vs. Intel Pentium 4 as we ll see in this course Reasons Latency Lags andwidth. Moore s Law helps W more than latency Faster transistors, more transistors, more pins help andwidth» MPU Transistors: 0.30 vs. 4 M xtors (300X)» DRM Transistors: vs. 56 M xtors (4000X)» MPU Pins: 68 vs. 43 pins (6X)» DRM Pins: 6 vs. 66 pins (4X) Smaller, faster transistors but communicate over (relatively) longer lines: limits latency» Feature size:.5 to 3 vs. 0.8 micron (8X,7X)» MPU Die Size: 35 vs. 04 mm (ratio sqrt X)» DRM Die Size: 47 vs. 7 mm (ratio sqrt X) 6 Reasons Latency Lags andwidth (cont d). Distance limits latency Size of DRM block long bit and word lines most of DRM access time Speed of light and computers on network. &. explains linear latency vs. square W? 3. andwidth easier to sell ( bigger=better ) E.g., 0 Gbits/s Ethernet ( 0 Gig ) vs. 0 µsec latency Ethernet 4400 M/s DIMM ( PC4400 ) vs. 50 ns latency Even if just marketing, customers now trained Since bandwidth sells, more resources thrown at bandwidth, which further tips the balance 7 8 CS5 S05 3

4 6 Reasons Latency Lags andwidth (cont d) 4. Latency helps W, but not vice versa Spinning disk faster improves both bandwidth and rotational latency» 3600 RPM 5000 RPM = 4.X» verage rotational latency: 8.3 ms.0 ms» Things being equal, also helps W by 4.X Lower DRM latency More access/second (higher bandwidth) Higher linear density helps disk W (and capacity), but not disk Latency» 9,550 PI 533,000 PI 60X in W 6 Reasons Latency Lags andwidth (cont d) 5. andwidth hurts latency Queues help andwidth, hurt Latency (Queuing Theory) dding chips to widen a memory module increases andwidth, but higher fan-out on address lines may increase Latency 6. Operating System overhead hurts Latency more than andwidth Long messages amortize overhead; overhead bigger part of short messages 9 0 Summary of Technology Trends For disk, LN, memory, and microprocessor, bandwidth improves by square of latency improve In the time that bandwidth doubles, latency improves by no more than.x to.4x Lag probably even larger in real systems, as bandwidth gains multiplied by replicated components Multiple processors in a cluster or even in a chip Multiple disks in a disk array Multiple memory modules in a large memory Simultaneous communication in switched LN HW and SW developers should innovate assuming Latency Lags andwidth If everything improves at the same rate, then nothing really changes When rates vary, requires real innovation Outline Technology Trends: Culture of tracking, anticipating and exploiting advances in technology. Define and quantity power. Define and quantity dependability 3. Define, quantity, and summarize relative performance 4. Define and quantity relative cost Define and quantify power ( / ) For CMOS chips, traditional dominant energy consumption has been in switching transistors, called dynamic power = / CapacitiveLoad Voltage FrequencySwitched For mobile devices, energy better metric Energydynamic = CapacitiveLoad Voltage For a fixed task, slowing clock rate (frequency switched) reduces power, but not energy Capacitive load a function of number of transistors connected to output and technology, which determines capacitance of wires and transistors Dropping voltage helps both, so went from 5V to V To save energy & dynamic power, most CPUs now turn off clock of inactive modules (e.g. Fl. Pt. Unit) Powerdynamic 3 Example of quantifying power Suppose 5% reduction in voltage results in a 5% reduction in frequency. What is impact on dynamic power? Power dynamic = / CapacitiveLoad Voltage = /.85 CapacitiveLoad (.85 Voltage) FrequencySwitched 3 = (.85) OldPower " 0.6 OldPower dynamic dynamic FrequencySwitched 4 CS5 S05 4

5 Define and quantity power ( / ) ecause leakage current flows even when a transistor is off, now static power important too Power Current static = static Voltage Leakage current increases in processors with smaller transistor sizes Increasing the number of transistors increases power even if they are turned off In 006, goal for leakage is 5% of total power consumption; high performance designs at 40% Very low power systems even gate voltage to inactive modules to control loss due to leakage Outline Technology Trends: Culture of tracking, anticipating and exploiting advances in technology. Define and quantity power. Define and quantity dependability 3. Define, quantity, and summarize relative performance 4. Define and quantity relative cost 5 6 Define and quantity dependability (/3) How to decide when a system is operating properly? Infrastructure providers now offer Service Level grees (SL) to guarantee that their networking or power service would be dependable. Systems alternate between two states of service with respect to an SL:. Service accomplish, where the service is delivered as specified in SL. Service interruption, where the delivered service is different from the SL» Failure = transition from state to state» Restoration = transition from state to state Define and quantity dependability (/3) Module reliability = measure of continuous service accomplish (or time to failure). Two metrics. Mean Time To Failure (MTTF) measures Reliability. Failures In Time (FIT) = /MTTF, the rate of failures Traditionally reported as failures per billion hours of operation Mean Time To Repair (MTTR) measures Service Interruption Mean Time etween Failures (MTF) = MTTF+MTTR Module availability measures service as alternate between the two states of accomplish and interruption (number between 0 and, e.g. 0.9) Module availability = MTTF / ( MTTF + MTTR) 7 8 Example calculating reliability If modules have exponentially distributed lifetimes (age of module does not affect probability of failure), overall failure rate is the sum of failure rates of the modules Calculate FIT and MTTF for 0 disks (M hour MTTF per disk), disk controller (0.5M hour MTTF), and power supply (0.M hour MTTF): FailureRate = MTTF= 9 Example calculating reliability If modules have exponentially distributed lifetimes (age of module does not affect probability of failure), overall failure rate is the sum of failure rates of the modules Calculate FIT and MTTF for 0 disks (M hour MTTF per disk), disk controller (0.5M hour MTTF), and power supply (0.M hour MTTF): FailureRate =0 " (/,000,000) +/500,000 +/00,000 = /,000,000 =7 /,000,000 =7,000FIT MTTF=,000,000,000 /7,000 # 59,000hours # 6.7years 30 CS5 S05 5

6 Outline Technology Trends: Culture of tracking, anticipating and exploiting advances in technology. Define and quantity power. Define and quantity dependability 3. Define, quantity, and summarize relative performance 4. Define and quantity relative cost Definition: Performance Performance is in units of things per sec bigger is better If we are primarily concerned with response time performance(x) = execution_time(x) " X is n times faster than Y" means Performance(X) Execution_time(Y) n = = Performance(Y) Execution_time(X) 3 3 Performance: What to measure Usually rely on benchmarks vs. real workloads To increase predictability, collections of benchmark applications, called benchmark suites, are popular SPECCPU: popular desktop benchmark suite CPU only, split between integer and floating point programs SPECint000 has integer, SPECfp000 has 4 integer pgms SPECCPU006 released in ugust 006 SPECSFS (NFS file server) and SPECWeb (WebServer) added as server benchmarks Transaction Processing Council measures server performance and cost-performance for databases TPC-C Complex query for Online Transaction Processing TPC-H models ad hoc decision support TPC-W a transactional web benchmark TPC-pp application server and web services benchmark 33 How Summarize Suite Performance (/5) rithmetic average of execution time of all pgms? ut they vary by 4X in speed, so some would be more important than others in arithmetic average Could add a weights per program, but how to pick weight? Different companies want different weights for their products SPECRatio: Normalize execution times to reference computer, yielding a ratio proportional to performance = time on reference computer time on computer being rated 34 How Summarize Suite Performance (/5) If program SPECRatio on Computer is.5 times bigger than Computer, then SPECRatio.5 = SPECRatio = Performance = Performance reference = reference Note that when comparing computers as a ratio, execution times on the reference computer drop out, so choice of reference computer is irrelevant 35 How Summarize Suite Performance (3/5) Since ratios, proper mean is geometric mean (SPECRatio unitless, so arithmetic mean meaningless) n GeometricM ean = n i= SPECRatio i. Geometric mean of the ratios is the same as the ratio of the geometric means. Ratio of geometric means = Geometric mean of performance ratios choice of reference computer is irrelevant These two points make geometric mean of ratios attractive to summarize performance 36 CS5 S05 6

7 How Summarize Suite Performance (4/5) Does a single mean well summarize performance of programs in benchmark suite? Can decide if mean a good predictor by characterizing variability of distribution using standard deviation. Like geometric mean, geometric standard deviation is multiplicative rather than arithmetic. Can simply take the logarithm of SPECRatios, compute the standard mean and standard deviation, and then take the exponent to convert back: n & GeometricMean = exp$ '( ln % n i= GeometricStDev = exp # " ( SPECRatioi) ( StDev( ln( SPECRatioi ) 37 How Summarize Suite Performance (5/5) Standard deviation is more informative, if you know the distribution has a standard form bell-shaped normal distribution, whose data are symmetric around mean lognormal distribution, where logarithms of data--not data itself--are normally distributed (symmetric) on a logarithmic scale For a lognormal distribution, we expect that 68% of samples fall in range [ mean / gstdev, mean gstdev] 95% of samples fall in range mean / gstdev, mean gstdev Note: Excel provides functions EXP(), LN(), and STDEV() that make calculating geometric mean and multiplicative standard deviation easy [ ] 38 Example Standard Deviation (/) GM and multiplicative StDev of SPECfp000 for Itanium Example Standard Deviation (/) GM and multiplicative StDev of SPECfp000 for MD thlon SPECfpRatio GM = 7 GSTEV = SPECfpRatio GM = 086 GSTEV = wupwise swim mgrid applu mesa galgel art equake facerec ammp lucas fma3d sixtrack apsi wupwise swim mgrid applu mesa galgel art equake facerec ammp lucas fma3d sixtrack apsi Coms on Itanium and thlon Standard deviation of.98 for Itanium is much higher-- vs..40--so results will differ more widely from the mean, and therefore are likely less predictable Falling within one standard deviation: 0 of 4 benchmarks (7%) for Itanium of 4 benchmarks (78%) for thlon Thus, the results are quite compatible with a lognormal distribution (expect 68%) nd in conclusion Tracking and extrapolating technology part of architect s responsibility Expect andwidth in disks, DRM, network, and processors to improve by at least as much as the square of the improve in Latency Quantify dynamic and static power Capacitance x Voltage x frequency, Energy vs. power Quantify dependability Reliability (MTTF, FIT), vailability (99.9 ) Quantify and summarize performance Ratios, Geometric Mean, Multiplicative Standard Deviation Read ppendix, record bugs online 4 4 CS5 S05 7