AC '97 Six Channel CNR Audio Reference Design with PLL. Description ORDERING INFO MIC IN LINE LINE OUT HEADPH OUT SURR OUT CNT/LFE OUT S/PDIF OUT

Transcription

1 CRD0- AC '97 Six Channel CNR Audio Reference Design with PLL Features Phase Locked Loop (PLL) Codec Operation Six Channel Analog Audio Outputs Headphone Sense using GPIO CS0 codec and two CS DACs 0-bit D to A conversion (DAC) 8-bit A to D conversion (ADC) S/PDIF (IEC-958) optical digital output Complete suite of Analog I/O connections: Line, Mic, CD, Video, Modem, and Aux Inputs Modem, Headphone, Line Front, Line Rear and Line Center/Sub-Woofer Outputs -layer low cost PC board Complies with Intel AC '97 revision. Exceeds Microsoft s PC 00 audio performance requirements. Description The CRD0- reference design eliminates the cost of the.567 MHz crystal by operating the CS0 in Phase Locked Loop (PLL) mode. This reference design also features six channel analog audio outputs, an optical S/PDIF digital output, and Communication and Networking Riser (CNR) interface. This design uses the CS0 audio codec which has several advanced features including a built-in headphone amplifier, simultaneous six channel analog and S/PDIF optical digital output, GPIO for headphone detection, and up to 0 db of internal microphone boost. The CRD0- reference design is available by ordering the CMK0- manufacturing kit. This kit includes the CRD0- board, a full set of schematic design files (OrCAD format), PCB job files (PADS ASCII), PCB artwork files, and bill of materials. This reference design offers significant cost savings over competing solutions and can be easily modified to meet your specific design goals. ORDERING INFO CMK0- (Manufacturing Kit) Microphone Input Line Input Line Output MIC IN LINE IN LINE OUT INT MODEM CD IN VIDEO IN AUX IN Cirrus Logic CRD0- Headphone Output Rear Channel Output Center / Sub-Woofer Output HEADPH OUT SURR OUT CNT/LFE OUT CS0 S/PDIF Digital Optical Output S/PDIF OUT Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. P.O. Box 787, Austin, Texas (5) 5 7 FAX: (5) Copyright Cirrus Logic, Inc. 00 (All Rights Reserved) MAR 0 DS59RDB

2 CRD0- TABLE OF CONTENTS LIST OF FIGURES. GENERAL INFORMATION.... SCHEMATIC DESCRIPTION.... CS0 Audio Codec.... Analog Inputs.... Center, LFE, and Surround Outputs.... Front Channel and Headphone Outputs....5 S/PDIF Optical Output....6 CNR Connector and EEPROM....7 Auto Demotion Circuit....8 Phase Locked Loop....9 Component Selection EMI Components...5. GROUNDING AND LAYOUT...5. Partitioned Voltage and Ground Planes...5. AC-Link...5. CS0 Layout Notes...5. REFERENCES...6. ADDENDUM BILL OF MATERIALS... Figure. Block Diagram...7 Figure. CS0 Audio Codec...8 Figure. Analog Inputs...9 Figure. Center Channel, Surround, and Sub-Woofer Outputs...0 Figure 5. Front Channel and Headphone Sense Output... Figure 6. S/PDIF Optical Output... Figure 7. CNR Connector... Figure 8. Phase Locked Loop... Figure 9. Auto Demotion and Serial Buffers...5 Figure 0. PCB Layout: Top Assembly Drawing...6 Figure. PCB Layout: Top Layer...7 Figure. PCB Layout: Bottom Layer...8 Figure. PCB Layout: Drill Drawing...9 Figure. PCB Layout: Top Silkscreen...0 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: Microsoft, Windows 95, Windows 98 and Windows Millennium and WHQL is registered trademark of Microsoft. CrystalClear is a trademark of Cirrus Logic, Inc. Intel is a registered trademark of Intel Corporation. OrCAD is a registered trademark of OrCAD, Inc. PADS is a registered trademark of, PADS Software, Inc. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided AS IS without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at DS59RDB

3 CRD0-. GENERAL INFORMATION The CRD0- CNR reference design features six channel CD quality analog and S/PDIF digital audio outputs. The card includes the CS0 AC '97 audio codec operating in PLL mode, and two CS -bit serial stereo DACs. This combination gives the CRD0- a rich feature set and industry leading audio performance. The CS0 audio codec includes a stereo 0-bit DAC, a stereo 8-bit ADC, and a very flexible analog audio mixer. The serial data outputs are paired with two CS DACs to provide four additional channels of analog audio. The CS0 also features three stereo pairs of line level analog inputs, a microphone input, and a stereo pseudo-differential CD input. The input signals can be routed to the ADC for recording or mixed together for recording and direct playback. The CS0 has internal registers that are used to control its various features such as volume levels, audio muting, and signal routing. The CS0 maintains high audio quality and exceeds the Microsoft PC 00 audio performance specifications. The CS0 audio codec communicates to the audio controller across the CNR interface using the AC-Link. The AC-Link is a 5-wire serial digital interface that transfers digital audio data and GPIO control/status data between the two devices, sends commands from the audio controller to the codec, and provides codec status information to the controller. For additional information on the AC-Link, see the Intel AC '97 revision. specification.. SCHEMATIC DESCRIPTION The block diagram in Figure illustrates the interconnections between the schematic pages found at the end of this document. Sections. through.8 describe the circuitry contained in these schematics.. CS0 Audio Codec The CS0 audio codec is shown in Figure. The analog input signals to the CS0 originate from the inputs in Figure, while the analog outputs are shown in Figure and Figure 5. AFLT and AFLT (pins 9, 0) require 000 pf /C0G capacitors connected to analog ground. These capacitors provide a single pole lowpass filter to the inputs of the CS0 ADC. No other input filtering is required. The AC-Link may require series termination resistors to prevent reflections. These are normally placed as close as possible to the transmitting end of the AC-Link signal. The CS0 SDATA_IN (pin 8) and BIT_CLK (pin 6) outputs have 7 Ω series termination resistors. The CS0 is powered by separate analog and digital power supplies, each with their own respective grounds. The symbols refer to analog ground and symbols refer to digital ground. For best results, connect the grounds together at a single point with a inch trace underneath the CS0. Each power pin requires an individual decoupling capacitor. These decoupling capacitors are placed as close as possible to their respective pins. The CS0 audio codec uses a 0. µf ceramic capacitor for each of the. V digital and 5 V analog supply pins.. Analog Inputs The LINE_IN, VIDEO_IN, and AUX_IN stereo inputs shown in Figure are AC-coupled to the CS0 codec with µf capacitors to minimize low frequency roll-off. The pull down resistors are recommended to prevent noise from coupling to the analog inputs when they are not in use. Locations for 6 db dividers were provided for.0 Vrms input compatibility, but are not required for PC 00 compliance. The microphone input is AC-coupled with a µf capacitor to minimize low frequency roll-off. The DS59RDB

4 CRD0- microphone circuit provides low voltage phantom power for electret microphones. Phantom power is derived from the 5 V analog supply and provides a maximum of. V under no load and a minimum of.0 V under a 0.8 ma load, as required by PC 00 specifications. The CS0 features a pseudo-differential CD input that minimizes common mode noise and interference. Each CD signal acts as one side of the differential input and CD_C acts as the other side. CD_C is used as the common return path for both the left and right channels.. Center, LFE, and Surround Outputs The audio outputs in Figure drive the rear speakers (surround), center speaker (CNT), and subwoofer (LFE) in six channel applications. These four outputs are driven digitally from the CS0 through two serial output ports and converted to analog audio through two high-performance CS -bit stereo DACs.. Front Channel and Headphone Outputs Figure 5 details the Headphone and Line Output circuits. The Line Outputs are the main analog outputs in a two channel system, and become the Front Outputs in a six channel audio system. The CS0 has a built in headphone amplifier on pins 9 and. These outputs are capable of driving headphones with impedances as low as Ω. The headphone outputs are AC-coupled through 0 µf capacitors. These large capacitor values create excellent low frequency response even under Ω loads..5 S/PDIF Optical Output The S/PDIF (IEC-958) digital output shown in Figure 6 is compatible with digital inputs on consumer devices such as Mini Disk recorders and consumer stereo receivers. The S/PDIF output operates at a fixed sampling frequency of 8 khz. It uses an industry standard Toshiba TOTX-7 optical TOSLINK transmitter..6 CNR Connector and EEPROM The CNR connector is shown in Figure 7. CNR is a motherboard interface that supports audio, modem, and LAN subsystems. CNR applications are targeted at OEMs, system manufacturers, and system integrators who wish take advantage of physically separating their audio, modem, or LAN circuitry from the PC motherboard. CNR accomplishes this without the additional cost associated with the interface circuitry required for a PCI bus add-in card. The CRD0- uses the AC-Link, SMBus, and power supply pins. The SMBus signals are connected to an ATC0 EEPROM to provide Plugand-Play functionality for the CNR card. The EE- PROM holds the Subsystem Vendor ID and Subsystem ID. It also contains other information for implementing a Plug-and-Play CNR card. For additional information on the CNR design specifications, programming utilities, and information on programming the EEPROM, visit the Intel Communications and Network Riser (CNR) homepage at Auto Demotion Circuit The configuration of the codec on the CRD0- will always be set as the primary audio codec in PLL mode. In crystal mode operation it can automatically demote to a secondary codec in the presence of a motherboard codec when R5 is changed to 00 kω (Figure 9). This feature is in accordance with the AC '97 Codec Disable and Demotion Rules..8 Phase Locked Loop The CRD0- reference design is configured to operate the CS0 in Phase Locked Loop (PLL) mode as the primary codec. The external clock must be one of the three supported rates, and the codec ID pins must be properly configured to identify DS59RDB

5 CRD0- the input clock frequency. Location Y in Figure 8 is populated with a.88 MHz surface mounted clock oscillator (test clock) to demonstrate the CS0 PLL operation..9 Component Selection Great attention was given to the particular components used on the CRD0- board with cost, performance, and package selection as the most important factors. Listed are some of the guidelines used in the selection of components: No components smaller than 0805 SMT package. Only single package passive components. No resistor packs. This reduces the risk of crosstalk between analog audio signals. All components except connectors are in surface mount packages..0 EMI Components Optional capacitors or inductors may be included to help the board meet EMI compliance tests, such as FCC Part 5. Choose these component values according to individual requirements.. GROUNDING AND LAYOUT The component layout and signal routing of the CRD0- provide a good model for developing new CNR add-in card designs.. Partitioned Voltage and Ground Planes It is critical for good audio performance to separate digital and analog sections to prevent digital noise from affecting the performance of the analog circuits. The analog section of the CRD0- is physically isolated from the digital section with a 0.0 inch partition. Partitioning is defined as the absence of copper on all PCB signal layers. The analog and digital sections have their own separate ground planes. All analog components, power traces, and signal traces are routed over the analog ground plane. Digital components, power traces, and signal traces are not allowed to crossover into the analog section. The CS0 audio codec is placed at the transition point between the analog and digital ground planes. The analog and digital ground planes must be tied together externally for the CS0 to maintain proper voltage references. For best results, the two ground planes are tied together with a single inch trace under the CS0 near its digital ground pins. Data converters are generally susceptible to noise on the crystal pins. In order to reduce noise from coupling onto these pins, the area around the.576 MHz crystal and its signal traces are filled with copper on the top and bottom of the PCB and attached to digital ground. A separate chassis ground provides a noise-free reference point for all of the EMI suppression components. The chassis ground plane is connected to the analog ground plane at the external jacks.. AC-Link According to the AC '97 revision. specification, the AC-Link signals can have a maximum capacitance (including traces, connectors, and circuitry) of 7.5 pf on BIT CLK and SDATA_IN (assuming a single codec). If this capacitance is exceeded, timing violations may occur and cause the system to malfunction. In order to avoid adding excessive capacitance, do not add any EMI capacitors to ground on any of the AC-Link lines. In addition, keep the trace length of the AC-Link as short as possible. Keeping the AC-Link trace length under 8 inches is strongly recommend.. CS0 Layout Notes Refer to the CS0 Data Sheet for analog and digital partitioning guidelines and bypass capacitor placement. Pay special attention to the location of bypass capacitors on REFFLT, AFLT, AFLT, and the placement of the power supply capacitors. DS59RDB 5

6 CRD0-. REFERENCES ) Intel, Audio Codec '97 Component Specification, Revision., September, ) Intel, CNR Specification, Revision., October 8, ) Cirrus Logic, CS0 Audio Codec '97 Data Sheet ) Steve Harris, Clif Sanchez, Personal Computer Audio Quality Measurements, Version.0 5) Microsoft, PC Design Guidelines, 6) M. Montrose, Printed Circuit Board Design Techniques for EMC Compliance (nd edition), IEEE Press, New York: ADDENDUM Schematic drawings Layout drawings Bill of materials 6 DS59RDB

7 CRD0- DS59RDB 7 CNR_BUS ASYNC PRIM_DN# ASDOUT ABITCLK ASDIN ASDIN0 ARST# ANALOG_OUT HP_OUT_R HP_OUT_L HP_OUT_C LINE_OUT_R LINE_OUT_L GPIO SPDIF_OUT SPDIF_TX PRIM_SEC_SWITCH ASDIN PRIM_DN# ASDIN ASDIN0 ANALOG_IN CD_IN_R MONO_OUT PHONE_IN LINE_IN_R PC_BEEP LINE_IN_L CD_C CD_IN_L MIC_IN VIDEO_IN_L VIDEO_IN_R AUX_IN_L AUX_IN_R SERIAL_PORT MCLK LRCLK SCLK SDOUT SDOUT0 CS0 ABITCLK LINE_IN_R ASYNC ASDOUT PRIM_DN# ASDIN ARST# XTAL_IN LINE_OUT_L LINE_OUT_R LINE_IN_L XTAL_OUT LRCLK SPDIF_OUT SDOUT HP_OUT_C SDOUT0 HP_OUT_R MONO_OUT GPIO HP_OUT_L SCLK ID# ID0# AUX_IN_L MIC CD_IN_R AUX_IN_R PHONE_IN CD_IN_L VIDEO_IN_L PC_BEEP VIDEO_IN_R CD_C PLL (optional) XTAL_OUT XTAL_IN ID# ID0# Figure. Block Diagram

8 CRD0-8 DS59RDB C5 NO POP C NO POP C 0.uF Z5U C 0.uF Z5U C 0.uF Z5U R55 NO POP C 0.uF Z5U R 7 R 7 Y NO POP C5.uF Y5V U CS0 LINE_OUT_R 6 MONO_OUT 7 AVdd 8 HP_OUT_L 9 GPIO/SDOUT HP_OUT_R AVss GPIO0/LRCLK HP_OUT_C 0 GPIO/SDO GPIO GPIO HPCFG DVdd XTL_IN XTL_OUT DVss SDATA_OUT 5 BIT_CLK 6 DVss 7 SDATA_IN 8 SYNC 0 DVdd 9 RESET# PC_BEEP PHONE AUX_L AUX_R 5 VIDEO_IN_L 6 VIDEO_IN_R 7 CD_L 8 CD_C 9 CD_R 0 MIC MIC LINE_IN_L LINE_IN_R AVdd 5 AVss 6 REFFLT 7 Vrefout 8 AFLT 9 AFLT 0 SPDIF_OUT 8 EAPD/SCLK 7 ID# 6 ID0# 5 LINE_OUT_L 5 C8 000pF C7 000pF C6 0.uF X7R C 000pF C 000pF C 000pF LINE_OUT_L LINE_OUT_R MONO_OUT.VD 5VA ABITCLK LINE_IN_R ASYNC ASDOUT PRIM_DN# ASDIN ARST# XTAL_IN LINE_OUT_L LINE_OUT_R LINE_IN_L XTAL_OUT LRCLK SPDIF_OUT SDOUT HP_OUT_C SDOUT0 HP_OUT_R MONO_OUT GPIO HP_OUT_L SCLK ID# ID0# AUX_IN_L MIC CD_IN_R AUX_IN_R PHONE_IN CD_IN_L VIDEO_IN_L PC_BEEP VIDEO_IN_R CD_C For 6 channel Operation, pinispulledlow. TIE inches Figure. CS0 Audio Codec

9 DS59RDB 9 CD IN LINE IN L J L R 0 C uf J R.K R9 7K Connect C to at the jack uf R6 00K 5 L5 R8 0 C5 uf C6 C7 00pF 00pF VIDEO_IN_L Connect R9 00K to at the jack C BEEP IN L6 R0 0 C0 uf L7 R 7K J5 AUX_IN_R R R.7K L8 R 0 C uf R5 00K L9 L0 R5 00K C8 R9 00K C R 00K R6 0 C uf C6 uf J CD_IN_R VIDEO IN MIC IN AUX IN INTERNAL MODEM CONNECTION uf R7 00K R8 0 C5 uf CD_C PHONE_IN MONO_OUT Figure. Analog Inputs 5 C9 C0 00pF 00pF C C8 0uF C C 700pF X7R R 0 R6 00K R8 0 R0 00K R5.5K 0.uF Z5U 5VA C C7 C PC_BEEP uf - db corners at 60 Hz and.8khz (Ri >= 8 kohm) uf uf LINE_IN_R LINE_IN_L MIC_IN CRD0-

10 0 DS59RDB SDOUT0 SDOUT SCLK LRCLK MCLK 5VA U SDATA DEM#/SCLK LRCK MCLK CS AOUTR VA AOUTL C0 C C 0uF 0.uF 0.uF Z5U Z5U U SDATA DEM#/SCLK LRCK MCLK CS AOUTR VA AOUTL VA R 0K R8 0K C6 C7 R 0K C C R9 0K uf uf uf uf R 7K R0 7K R0 560 R 560 R5 7K R6 560 R7 560 Figure. Center Channel, Surround, and Sub-Woofer Outputs R 7K C8 700pF X7R C C5 700pF X7R C C9 700pF X7R C6 700pF X7R 5 5 SURROUND JACK J8 Connect C to at the jack CNT/LFE JACK J9 Connect C to at the jack CRD0-

11 DS59RDB LINE_OUT_R LINE_OUT_L GPIO HP_OUT_L HP_OUT_R HP_OUT_C C8 C9 C5 C55 C56 uf uf 0uF 0uF uf R 0K R8 0K R5 0K R9 0K Figure 5. Front Channel and Headphone Sense Output C50 00pF C C57 00pF C C5 00pF 5VA C58 00pF R56 0K LINE OUT JACK J0 Connect C to at the jack HEADPHONE JACK J Connect C to at the jack CRD0-

12 CRD0- SPDIF_TX J 5VD 5 C59 R50 8.K 0.uF Z5U 6 TOTX-7 Figure 6. S/PDIF Optical Output DS59RDB

13 DS59RDB PRIM_DN# ASYNC ASDOUT ABITCLK.VD VD C6 0.uF Z5U C65 0.uF Z5U P B A B reserved reserved A B reserved reserved A B reserved A B5 reserved A5 B6 reserved reserved A6 B7 reserved A7 B8 LAN_TXD A8 B9 LAN_TXD LAN_TXD0 A9 B0 LAN_RSTSYNC A0 B LAN_CLK A B LAN_RXD LAN_RXD A B LAN_RXD0 reserved A B USB A B5 reserved A5 VD C6 C6 USB_OC# V 0uF B7 A7 0.uF B8 A8 Z5U -V.Vdual B9 A9 B6 5Vdual USB- A6.VD 5VD C66 0uF B0 B B B B B5 B6 B7 B8 B9 B0 EE_DOUT EE_SHCLK SMB_A0 SMB_SCL CDC_DN_ENAB# AC97_SYNC AC97_SDATA_OUT AC97_BITCLK CNR Connector C67 0uF EE_DIN EE_CS SMB_A SMB_A SMB_SDA AC97_RESET# AC97_SDATA_IN AC97_SDATA_IN AC97_SDATA_IN0 TP TP TP TP TP5 TP6 U6 OUT MC78M05C Connect to with a 50 mil trace near the codec. Connect C to with a 50 mil trace near the finger edge of the board. IN 5VA A0 A A A A A5 A6 A7 A8 A9 A0 Figure 7. CNR Connector ARST# ASDIN ASDIN0 5VD C6 0uF 5 6 U5 A A SDA SCL A0 ATC0 Vcc WP Vss.VD 8 7 C60 0.uF Z5U CRD0-

14 CRD0- Test Clock Only XTAL_IN XTAL_OUT PLL (Phase Locked Loop) ID# ID0# For PLL operation: ) Populate R5 = K (Disable MB audio).vd ) DO NOT populate: Y, C, C5, and R55 R5.K C68.0 uf C69 0 pf R5 NO POP R5 0 ) ) Apply external oscillator to XTAL_IN (pin ) (CRD0- will use.8 MHz test oscillator ECS-8FA) Populate R5, R5, R5, C68, and C69 according to the desired input clock rate: Y.8 MHz Clock rate (MHz) R5 R5 R5 C68 C69.88.K NO POP 0 ohm 0.0uF 0pF.576 NO POP NO POP NO POP NO POP NO POP 7.K 0 ohm NO POP 0.0uF 0pF 8.K 0 ohm 0 ohm 0.0uF 0pF Figure 8. Phase Locked Loop DS59RDB

15 CRD0-.VD R5 = K forces motherboard codec(s) to be held in RESET R5 K U7 TC7SZ5FU 5 C70 0.uF X7R ASDIN PRIM_DN#.VD U8 TC7SZ6FU 5 C7 0.uF X7R ASDIN ASDIN0 DO NOT use this circuit for motherboard designs. This circuit is strictly for CNR cards. For motherboard designs: connect ASDIN to ASDIN0 if primary codec, connect ASDIN to ASDIN if secondary codec. Replace R5 with 00K for automatic demotion when used with primary motherboard codec(s). Figure 9. Auto Demotion and Serial Buffers DS59RDB 5

16 CRD0- Figure 0. PCB Layout: Top Assembly Drawing 6 DS59RDB

17 CRD0- Figure. PCB Layout: Top Layer DS59RDB 7

18 CRD0- Figure. PCB Layout: Bottom Layer 8 DS59RDB

19 CRD0- Figure. PCB Layout: Drill Drawing DS59RDB 9

20 CRD0- Figure. PCB Layout: Top Silkscreen 0 DS59RDB

21 DS59RDB 5. BILL OF MATERIALS Item Quantity Reference Manufacturer Part Number Description C,C,C,C,C,C, C,C59,C60,C6,C6,C65 KEMET C0805C0M5UAC CAP, 0805, Z5U, 0. µf, 0%, 50V C5 KEMET C06C5M8VAC CAP, 06, Y5V,. µf, 0%, 0V C6,C70,C7 KEMET C0805C0K5RAC CAP, 0805, X7R, 0. µf, 0%, 50V 5 C7,C8,C,C,C KEMET C0805C0K5GAC CAP, 0805, C0G, 000 pf, 0%, 50V 5 C,C5 KEMET C0805C0K5GAC DO NOT POPULATE 6 9 C6,C7,C8,C,C, C,C,C5,C0,C, C,C5,C6,C7,C, C,C8,C9,C C9,C0,C6,C7,C50, C5,C57,C58 PANASONIC ECE-VHA00R CAP, SMT B,, µf, 0%, 50V KEMET C0805C0J5GAC CAP, 0805, COG, 00 pf, 5%, 50V 8 6 C8,C0,C6,C6,C66,C67 PANASONIC ECE-VCA00R CAP, SMT B,, 0 µf, 0%, 6V 9 5 C,C8,C9,C5,C6 KEMET C0805C7K5RAC CAP, 0805, X7R, 700 pf, 0%, 50V 0 C5,C55 PANASONIC ECE-V0GAP CAP, SMT D,, 0 µf, 0%, V C68 KEMET C805CK5RAC CAP, 0805, X7R, 0.0 µf 0%, 50V C69 KEMET C805CK5RAC CAP, 0805, X7R, 0 pf, 0%, 50V 5 J,J,J8,J9,J0 A/D - TRONICS CONN, /8" DOUBLE SW. STEREO PHONE JACK J,J,J5,J7 MOLEX HDR, X, 0.05" PIN, 0." CTR, 5u" AU 5 J6 MOLEX HDR, X, 0.05" PIN, 0." CTR, 50u" SN/PB 6 J SINGATRON SJ-09075N5 CONN, /8" SINGLE SW. STEREO PHONE JACK W/INSULATOR 7 J TOSHIBA TOTX7 CONN, OPTICAL TOSLINK TRANSMITTER 8 0 L,L,L,L,L5,L6,L7,L8, L9,L0 TDK HF50ACB6-T IND, FBEAD, 5% CRD0-

22 DS59RDB 9 P NONE NONE CNR BUS CONNECTOR 0 R,R PHILIPS 9C0805A7R0J RES, SO, 0805, 7, 5%, /0W, METAL FILM 9 R,R8,R,R8,R0,R, R6,R8,R5 0 R5,R6,R9,R0,R,R6, R9,R,R5,R7 PHILIPS 9C0805A0R00J RES, SO, 0805, 0, 5%, /0W, METAL FILM PHILIPS 9C0805A00J RES, SO, 0805, 00K, 5%, /0W, METAL FILM R,R5 PHILIPS 9C0805A0J RES, SO, 0805,.K, 5%, /0W, METAL FILM R5 PHILIPS 9C0805A50J RES, SO, 0805,.5K, 5%, /0W, METAL FILM 5 6 R,R9,R,R5,R0,R PHILIPS 9C0805A70J RES, SO, 0805, 7K, 5%, /0W, METAL FILM 6 R PHILIPS 9C0805A70J RES, SO, 0805,.7K, 5%, /0W, METAL FILM 7 R0,R,R6,R7 PHILIPS 9C0805A5600J RES, SO, 0805, 560, 5%, /0W, METAL FILM 8 6 R,R,R8,R9,R,R5 PHILIPS 9C0805A0J RES, SO, 0805, 0K, 5%, /0W, METAL FILM 9 R8,R9,R56 PHILIPS 9C0805A00J RES, SO, 0805, 0K, 5%, /0W, METAL FILM 0 R50 PHILIPS 9C0805A80J RES, SO, 0805, 8.K, 5%, /0W, METAL FILM R5,R55 PHILIPS 9C0805A0R00J DO NOT POPULATE R5 PHILIPS 9C0805A00J RES, SO, 0805, K, 5%, /0W, METAL FILM 6 TP,TP,TP,TP,TP5,TP6 KEYSTONE 505 MINI SMT TEST POINT U Cirrus Logic CS0-JQ IC, TQFP, AC '97. SERIAL CODEC W/ HP AMP SRC 5 U,U Cirrus Logic CS-KS IC, SO, SOIC8, STEREO DAC, BITS 6 U5 ATMEL ATC0N-0SC-.7 IC, SO, SOIC8, SERIAL EEPROM, 56 x 8,.7V 7 U6 MOTOROLA MC78M05CDT IC, SO, 5V REGULATOR, DPAK, %, 500mA 8 U7 TOSHIBA TC7SZ5FU IC, SSOP5-P-0.65A, single state buffer,.6ns 9 U8 TOSHIBA TC7SZ6FU IC, SSOP5-P-0.65A, single state buffer,.6ns 0 Y FOX FS.576 DO NOT POPULATE Y ECS ECS-8FA Clock OSC,.88MHz, SMT CRD0-

23 Notes

24

25 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic: CMK0-