PCB Layout and Design Guide for CH7101B HDMI to VGA Converter

Transcription

1 Chrontel AN-B0 Application Notes PCB Layout and Design Guide for CH0B HDMI to VGA Converter.0 INTRODUCTION The CH0B is a low-cost, low-power semiconductor device, which can convert HDMI signals into VGA outputs with IIS or SPDIF audio output. This application note focuses only on the basic PCB layout and design guidelines for CH0B HDMI to VGA Converter. Guidelines in component placement, power supply decoupling, grounding, input /output signal interface are discussed in this document. The discussion and figures that follow reflect and describe connections based on the 0-pin QFN package of the CH0B. Please refer to the CH0B datasheet for the details of the pin assignments..0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS Components associated with the CH0B should be placed as close as possible to the respective pins. The following discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement and layout of components associated with these pins.. Power Supply Decoupling The optimum power supply decoupling is accomplished by placing a 0.μF ceramic capacitor to each of the power supply pins as shown in Figure. These capacitors (C, C, C, C, C, C, C0, C) should be connected as close as possible to their respective power and ground pins using short and wide traces to minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the decoupling capacitors to the CH0B ground pins, in addition to ground vias... Ground Pins The grounds of the CH0B should be connected to a common ground plane to provide a low impedance return path for the supply currents. Whenever possible, each of the CH0B ground pins should be connected to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a ground via. Short and wide traces should be used to minimize the lead inductance. Refer to Table for the Ground pins assignment... Power Supply Pins The power supply includes VDDPLL, DVDD, AVCC, AVCC_DAC, and AVDD. Refer to Table for the Power supply pins assignment. Refer to Figure for Power Supply Decoupling Rev.0. 0//0

2 AN-B0 Table : Power Supply Pins Assignment of the CH0B (QFN) Pin Assignment # Of Pins Type Symbol Description Power VDDPLL PLL Power Supply (.V), Power DVDD Digital supply voltage (.V), GND DGND Digital Ground, Power AVCC Analog supply voltage (.V), Power AVCC_DAC DAC power supply (.V~.V) Power AVDD HDMI receiver power supply (.V) Thermal pad Ground GND Power supply ground QFN U, DVDD, DGND AVD D VD DPLL Thermal Pad, AVC C, AVC C_D AC C C 0.uF 0.uF C 0.uF C 0.uF C C 0uF 0uF C C C 0.uF 0.uF0uF C 0.uF C0 0.uF C 0uF C 0uF R 00MHz L R 00MHz L R 00MHz L R 00MHz L R 00MHz L VC C_ VC C_ CH 0B Figure : Power Supply Decoupling and Distribution Note: All the Ferrite Beads described in this document are recommended to have an impedance of less than 0.0 at MHz & at 00MHz. Please refer to Fair Rite part #0 for details or an equivalent part can be used for the diagram.. Internal Reference Pins RBIAS pin This pin sets the DAC current. A 0 KΩ, % tolerance resistor should be connected between RBIAS and GND as shown in Figure. A smaller resistance will create more DAC current. This resistor should be placed with short and wide traces as near as possible to CH0B. U RBIAS QFN R 0K(%) Thermal Pad CH 0B Rev.0. 0//0

3 Figure : RBIAS pin connection AN-B0. General Control Pins RB This pin is the chip reset pin for CH0B, which is internally pulled-up, places the device in the power on reset condition when this pin is low. A power-reset switch can be placed on the RB pin on the PCB as a hardware reset for CH0B as shown in Figure. When the pin is high, the reset function can also be controlled through the serial port. AVCC U RB 0 RB R M SW P0SS-ND C 0.uF CH 0B On chip power-on reset function s sequence Figure : RB pin connection There are two methods for chip power-on reset.. The RB signal can be generated by on board Resistor and Capacitor delay, which can be refer to Figure. For hard ware circuit, please refer to. RB..V <ms.v ResetB Figure : Power-on Reset Function s Sequence on board. RB signal is generate by system global reset. In this case,.v should be earlier than.v, the power supply should be valid and stable for at least 0ms before the reset signal is valid. The pulse width of valid reset signal should be at least 00us. Otherwise, the chip can t work well. The timing is shown in Figure Rev.0. 0//0

4 AN-B0.V >0ms.V >00 us ResetB Figure : Power-on Reset Function s Sequence external globa eset Note:. The rising threshold of RB is.v.. The falling threshold of RB is 0.V. GPIO [:0] These pins are general-purpose input/output. Refer to reference schematic.. Serial Port Control for CH0B SPC0 and SPD0 SPD0 and SPC0 function as a serial interface where SPD0 is bi-directional data and SPC0 is an input only serial clock. In the reference design, SPD0 and SPC0 pins are pulled up to +.V with.k resistors always as shown in Figure. DDC_SCL and DDC_SDA DDC_SCL and DDC_SDA are used to interface with the DDC of HDMI Source or transmitter and the serial PROM. This DDC pair needs to be pulled up to V through KΩ resistors (Refer to Figure ). VGA_SCL and VGA_SDA VGA_SCL and VGA_SDA are used to interface with the DDC of VGA receiver and the serial PROM. This DDC pair needs to be pulled up to V through. KΩ resistors (Refer to Figure ) Rev.0. 0//0

5 CHRONTEL AN-B0 VC C_ U R.K R.K SPC0 SPD0 VD D SPC0 SPD0 QFN DD C_SC L DD C_SD A R K R K DD C_SC L DD C_SD A VD D R.K R.K 0 VGA_SC L VGA_SD A VGA_SC L VGA_SD A CH 0B Figure : Serial Port Control. HDMI receiver Pins The RCP, RCN, RD [:0] P, RD [:0] N signals are high frequency differential signals that need to be routed with special precautions. Since those signals are differential, they must be routed in pairs... Differential Pair Impedance To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the impedance target of 00-Ω ± 0% for the differential data/clock traces. The restriction of this impedance target is to prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired by proper design of trace length, trace width, signal layer thickness, board dielectric, etc. The HDMI differential pairs should be routed on the top layer directly to the HDMI connector pads if possible... Trace Routing Length To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and bends should always be minimized; inductive effects may be introduced, causing spikes in the signals. Trace routing lengths from CH0B to the HDMI connector are limited to a maximum of inches. The CH0B should be as close to the HDMI connector as possible... Length Matching for Differential Pairs The HDMI specifies the intra-pair skew and the inter-pair skew as in Table. The intra-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions between the true and complement signals. The inter-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions between any two single-ended data signals that do not constitute a differential pair. Table : Maximum Skews for the HDMI Transmitter Rev.0. 0//0

6 AN-B0 Skew Type Intra-Pair Skew Inter-Pair Skew Maximum at Transmitter 0. T bit 0.0 T Pixel Where T bit is defined as the reciprocal of Data Transfer Rate and T Pixel is defined as the reciprocal of Clock Rate. Therefore, T Pixels is 0 times T bit. In other words, the intra-pair length matching is much more stringent than the interpair length matching. It is recommended that length matching of both signals of a differential pair be within mils. Length matching should occur on a segment-by-segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be within 00 mils. Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for instance, is electrically considered part of the pad itself... ESD Protection for HDMI Interface In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each HDMI input (data and clock). International standard EN 0: establishes kv as the common immunity requirement for contact discharges in electronic systems. kv is also established as the common immunity requirement for air discharges in electronic systems. International standard EN 000--: / IEC 000--: establishes the immunity testing and measurement techniques. System level ESD testing to International standard EN 000--: / IEC 000--: has confirmed that the proper implementation of Chrontel recommended diode protection circuitry, using BCD AT0 diode array devices, will protect the CH0B device from HDMI transmitter discharges of greater than kv (contact) and 0kV (air). The AT0 have a typical capacitance of only 0.0pF between I/O pins. This low capacitance won t bring too much bad effect on HDMI eye diagram test. Figure (A) and (B) show the connection of HDMI connectors, including the recommended design of AT0 diode array devices. HDMI connector is used to connect the CH0B HDMI inputs from HDMI transmitter. U QFN CH 0B RC N RC P RD 0N RD 0P RD N RD P RD N RD P 0 HPD 0 RC N RC P RD 0N RD 0P RD N RD P RD N RD P HPD Figure (A): The connection of the HDMI input Rev.0. 0//0

7 DDC_SCL DDC_SDA CHRONTEL AN-B0 J RD P RD N RD P RD N RD 0P RD 0N RC P RC N C 0.uF U LIN E NC 0 NC LIN E LIN E NC NC LIN E AT0 VC C_0 U AT0 C 0uF LIN E NC 0 NC LIN E LIN E NC NC LIN E VC C_0 RD P RD N RD P RD N RD 0P RD 0N RC P RC N RD P RD N RD P RD N RD 0P RD 0N RC P RC N DD C_SC L DD C_SD A HPD/SCEN 0 0 DD C_SC L DD C_SD A RX+ RX_shld RX- RX+ RX_shld RX- RX0+ RX0_shld RX0- RXC + RXC _shld RXC - CEC RESERVED SC L SD A DD C_GN D +V HTPLUG GN D GN D GN D GN D HDMI_A JP HEADER HPD/SCEN R k R HD MI R D K K AZ-0H D D AZ-0H AZ-0H HDMI input Figure (B): The connection of the HDMI inputs-ch0b HDMI connectors The following is the description for each HDMI interface pins HDMI Link Data Channel (RD [:0] P and RD [:0] N) These pins provide HDMI differential inputs for data channel 0 (blue), data channel (green) and data channel (red). (Refer to Figure (A)). HDMI Link Clock Outputs (RCP and RCN) These pins provide the HDMI differential clock inputs for HDMI corresponding to data on the RD [:0] P and RD [:0] N inputs (Refer to Figure (A)). HPD (HDMI Hot Plug Detect) This output pin connects to the +V power through a KΩ resistor. Refer to Figure (B) for the design example.. Video Outputs VGA or RGB+CSYNC output Rev.0. 0//0

8 CHRONTEL AN-B0 VGA standard output signal level of Hsync and Vsync is more than.v. CH0B Hsync and Vsync output signal level is +.V. Customer can use ACT0 (AND GATE) to pull high this signal level to V(recommend to add the diode). It is recommended but not necessary. (Refer to Figure ) In RGB+Csync output format, the Csync high level is +.V. Csync pin is a COMS push-pull output pin, customer can use other circuit to change is high level to 0.V or other voltage level according to different Receivers. (Refer to Figure ) RD AC L nh R C 0pF C 0pF D AZ-0H GD AC L R nh C 0pF C 0pF D BD AC R L nh C 0pF C 0pF AZ-0H D P AZ-0H CSYNC CN JA CK-R CA- P HO VO R R C pf D C pf AZ-0H MONR MONG VGA_SD A MONB AZ-0H D HD MI MONVSY NC VGA_SC L D 0 0 VGA OUTPUT AZ-0H D VGA AZ-0H Figure : CH0B VGA or RGB+CSYNC output. Audio Output IIS IIS audio output can be configured through programming CH0B registers. (Refer to Figure ) SPDIF For SPDIF output, CH0B supports audio sample frequencies from Khz to khz. (Refer to Figure ) J HEADER U SPDIF SD /SPD IF WS SC LK MC LK IS DAC CH 0B Figure : CH0B IIS or SPDIF Output Pins Rev.0. 0//0

9 AVCC GPIO0 GPIO RBIAS/ATPG DDC_SCL DDC_SDA AVCC SPC0 SPD0 GPIO0 GPIO VO HO DVDD DGND VGA_SCL 0 AVCC SPC0 SPD0 GPIO0 GPIO VO HO/CSYNC DVDD DGND VGA_SCL RDP RDP RD0P RCP 0 RDP RDN AVCC RDP RDN AVDD RD0P RD0N RCP RCN GND CHRONTEL.0 REFERENCE DESIGN EXAMPLE AN-B0 The figures below are the reference schematic of CH0B, which is provided here for design reference only. Please contact Chrontel Applications group for further support. Table provides the BOM list for the reference schematic.. Reference Schematic VCC_0 VCC_ C 0uF R.K VCC_0 C0 0.uF R 00K % C L.uF.uH R K % C pf U EN SW FB GND VIN VIN GND FB SW EN AT0 R 0K 0 R 00K % C.uF C pf L R.uH 00K % VCC_ C 0uF VCC_ VCC_ L L FB FB AVDD C 0uF AVCC C 0uF C 0.uF C 0.uF C 0.uF VCC_ L FB AVCC_DAC C C 0uF 0.uF VCC_ L C FB 0.uF VCC_ L FB VDDPLL C 0uF DVDD C 0uF C0 0.uF C 0.uF C 0.uF Power of CH0B RDP RDN RDP RDN RD0P RD0N RCP RCN J RDP RX+ RDN RX_shld RDP RX- U RX+ RDN RX_shld RDP RD0P RX- LINE NC 0 RDN RX0+ NC LINE RD0N RX0_shld RDP RCP 0 RX0- LINE NC RDN RXC+ NC LINE RCN RXC_shld RXC- Rclamp0 CEC DDC_SCL RESERVED VCC_0 DDC_SDA SCL SDA R ohm GPIOV DDC_GND C HPD/SCEN +V C 0uF 0 HTPLUG 0.uF GND GND GND GND U HDMI_A LINE NC 0 RD0P RD0N NC LINE JP LINE NC DDC_SCL RCP DDC_SDA RCN NC LINE Rclamp0 VCC_0 HEADER R HDMI k HPD/SCEN R R K K D DGND VDDPLL DVDD DGND DDC_SCL DDC_SDA SD WS SCLK MCLK RB 0 U GND VDDPLL DVDD DGND DDC_SCL DDC_SDA SD/SPDIF WS SCLK MCLK RB CH0B RDN AVCC RDN AVDD RD0N CH0B 0pin QFN RCN HPD/SCEN 0 RBIAS/ATPG RDAC AVCC_DAC GDAC BDAC AVCC_DAC VGA_SDA NC NC VCC_0 HPD/SCEN RBIAS/ATPG RDAC AVCC_DAC GDAC BDAC D SM AVCC_DAC VGA_SDA U SD SCLK SDIN AOUTR 0 WS SCLK VA LRCK GND MCLK MCLK AOUTL VQ FILT+ C C C 0uF CS 0uF 0.uF Audio IS to L, R CHANNEL BDAC RDAC R0 R L nh C 0pF L nh C 0pF VCC_ C C 0uF C C0 0pF C 0pF L0 GDAC nh R C C 0pF 0pF R.K.uF.uF R.K MONB D AZ-0H D AZ-0H J PJ MONR D AZ-0H MONG AZ-0H HDMI D D R R AZ-0H AZ-0H.K.K VGA_SCL HDMI input VGA_SDA Note: SPC0 SPD0 R0.K VCC_ R.K GPIOV R 0K R 0K R K R 0K % RB R M HO VO R R AZ-0H MONR MONG VGA_SDA MONB MONHSYNC MONVSYNC D VGA_SCL D0 D 0 P 0 These pins pass +/-KV ANSI/ESDA/JEDE C standard. Human Body Model JS ESD protection device for option. Reserved C 0.uF VGA OUTPUT C 0pF C 0pF AZ-0H AZ-0H D VGA CH0B interface AZ-0H Rev.0. 0//0

10 AN-B0. Reference Board Preliminary BOM Table : CH0B Reference Design BOM List Item Quantity Reference Part C, C. μf C, C pf C, C, C, C, C, C, C, C, C, C, C 0 μf C, C, C, C, C0, C, C, C, C0, C, C, C 0. μf C, C0, C, C, C, C, C, C 0pF C, C. μf D SM 0 D, D, D, D, D, D, D, D, D0, D AZ-0H JP Header 0 J HDMI_A J PJ L, L, L, L, L _00MHz L, L, L0 nh L, L.μH P VGA R K R, R, R 00K R0, R, R R K 0 R, R, R K R, R 0K R0, R.K R 0K R 0K R, R.K R M R, R R, R.K R 0 R.K U AT0 U, U AT0 U CH0B U CS Rev.0. 0//0

11 AN-B0.0 REVISION HISTORY Rev. # Date Section Description 0. 0//0 All Initial release 0. /0/ Modify VGA_SCL and SDA pull up resistor value Modify Figure (B) Modify Figure Modify reference schematic Modify BOM 0. 0/0/0 All Update for CH0B 0. 0//0. Add RB 0. 0//0.. Modify RB Modify reference schematic Rev.0. 0//0

12 Disclaimer AN-B0 This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. 0 Chrontel - All Rights Reserved. Chrontel Chrontel International Limited Front Street, th floor, Hamilton, Bermuda HM sales@chrontel.com Rev.0. 0//0