YSS920B APPLICATION MANUAL

Transcription

1 YSS920B APPLICATION MANUAL EVE 32-bit DSP Engine for Various sound Effects YSS920B APPLICATION MANUAL CATALOG No.: LSI-6SS920B

2

3 Contents Contents Chapter 1 Outline Features Application Difference between YSS920B and YSS Block Diagram... 5 Chapter 2 Pin Function Pin Configuration Pin Function Pin Description... 9 Chapter 3 Function Description Register Map Register Details Serial Data Interface Format Microprocessor Interface Format Program Download Chapter 4 Basic Design Example Peripheral Circuits (When One YSS920B Is Used) Peripheral Circuits (When Multiple YSS920Bs Are Used) Clock Connection for High fs Chapter 5 Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics AC Characteristics Chapter 6 Package Dimensions APPLICATION NOTES... 56

4 - 4 - Chapter 1 Outline Chapter 1 Outline YSS920B is a 32-bit digital signal processor exclusively designed for sound field processing. As a post-processing DSP after surround sound decoding, YSS920B can process various sound fields such as various simulation surround and virtual surround through user programs, which can provide wide variation of sound field effects on audio equipments. 1.1 Features Basic compatibility with the SubDSP section of YSS922/932 for DSP program High precision processing by 32-bit floating-point operation Capability to process various sound effects by downloading external programs to the built-in RAM 16 channels processing capability (input: 16ch, output: 16ch) Zero data detecting function on each channel 32-bit data transmission ability between multiple YSS920Bs Connectability to most types of ADC, DAC and DIR through control register setting Built-in delay memory with 32 bits 1024 words (Max ms at fs = 48 khz) Ability to execute up to 2.73 seconds delay (at fs = 48 khz) when connected with an external DRAM or SRAM Support for sampling frequencies from 32 khz to 192 khz DSP section specifications Internal operating frequency: to MHz Data bus width: 32 bits MAC: 32 bits (floating-point) 16 bits (fixed-point) + 49 bits 49 bits Program RAM: 50 bits 1024 words Coefficient RAM: 16 bits 1024 words Ability to use up to 20 general-purpose input/output terminals Power supply voltage: 2.5 V (for internal and PLL circuits), 3.3 V (for I/O) Si-gate CMOS process Lead-free 100-pin SQFP package (YSS920B-SZ) 1.2 Application Sound field processing for AV amplifiers and audio mixers such as: 1) Simulation surrounds for Hall, Theater, Church, Stadium, Disco, Jazz, and Live 2) Virtual Surround 3) Bass Management 4) Filtering process for LPF, HPF, equalizer, etc. 5) Fader and Level Meter 6) Generating white noise, pink noise, sine waves, etc. 1.3 Difference between YSS920B and YSS920 The principal differences are as follows. Please sufficiently check that no problem occurs in your product when you replace YSS920 by YSS920B. Item YSS920B YSS920 1 Internal operating frequency to 50.00MHz to 40.96MHz 2 Power consumption (VDD1) 45mW (typ) / 65mW (max) 30mW (typ) / 45mW(max) 3 Power consumption (VDD2/AVDD) 120mW (typ) / 145mW (max) 80mW (typ) / 115mW (max) 4 Power supply start-up order Defined (see Power-on) Undefined

5 Chapter 1 Outline Block Diagram SDO7 SDO6 SDO5 SDO4 SDO3 SDO2 SDO1 SDO0 Address setting RAM for external memories 17 bits 256 words Coefficient RAM 16 bits 1024 words Interface for external memories Program RAM 50 bits 1024 words PLL Control signal Control resister Microcomputer interface SDI7 SDI6 SDI5 SDI4 SDI3 SDI2 SDI1 SDI0 SDWCK SDBCK

6 - 6 - Chapter 2 Pin Function Chapter 2 Pin Function 2.1 Pin Configuration < 100-pin SQFP top view > 32 SDO0 VDD2 RAMD0 RAMD1 RAMD2 VSS VDD1 RAMD10 RAMD11 RAMD12 RAMD13 RAMD14 RAMD15 CASN RAMWEN RAMOEN RASN RAMA8 RAMA7 RAMA0 RAMA6 RAMA1 RAMA5 RAMA2 RAMA9 RAMA4 RAMA3 XI XO IOPORT0 IOPORT1 IOPORT2 IOPORT3 IOPORT4 AVSS CPO AVDD VDD2 RAMA11 RAMA12 RAMA13 RAMA14 RAMA15 RAMA16 RAMA17 VSS /CS SO SI SCK /IC VDD VSS VSS IOPORT5 IOPORT6 IOPORT7 IOPORT8 IOPORT9 IOPORT10 IOPORT11 IOPORT12 IOPORT13 IOPORT14 IOPORT15 SDO1 SDO2 SDO3 SDO4 SDO5 SDO6 SDO7 SDI0 SDI1 SDI2 SDI3 SDI4 SDI5 SDI6 SDI7 IOPORT16 IOPORT17 IOPORT18 IOPORT19 VDD2 (NC) VDD1 SDBCK SDWCK VDD1 RAMA10 VDD1 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7 RAMD8 RAMD9 VDD1

7 Chapter 2 Pin Function Pin Function No. Name I/O Function 1 VSS - Digital ground pin 2 XO O Crystal oscillator connecting pin 3 XI I Crystal oscillator connecting pin ( to MHz) 4 IOPORT0 I+/O General-purpose input/output pin / SDO 0 Lch zero-flag output pin / Program branch condition input/output pin 5 IOPORT1 I+/O General-purpose input/output pin / SDO 0 Rch zero-flag output pin / Program branch condition input/output pin 6 IOPORT2 I+/O General-purpose input/output pin / SDO 1 Lch zero-flag output pin / Program branch condition input/output pin 7 IOPORT3 I+/O General-purpose input/output pin / SDO 1 Rch zero-flag output pin / Program branch condition input/output pin 8 IOPORT4 I+/O General-purpose input/output pin / SDO 2 Lch zero-flag output pin / Program branch condition input/output pin 9 IOPORT5 I+/O General-purpose input/output pin / SDO 2 Rch zero-flag output pin / Program branch condition input/output pin 10 IOPORT6 I+/O General-purpose input/output pin / SDO 3 Lch zero-flag output pin / Program branch condition input/output pin 11 IOPORT7 I+/O General-purpose input/output pin / SDO 3 Rch zero-flag output pin / Program branch condition input/output pin 12 AVSS - Analog ground pin (for PLL) 13 CPO A PLL filter connection pin 14 AVDD V analog power supply pin (for PLL) 15 VDD V digital power supply pin (for input/output pin) 16 (NC) - (No connection) 17 IOPORT8 I+/O General-purpose input/output pin / SDO 4 Lch zero-flag output pin 18 IOPORT9 I+/O General-purpose input/output pin / SDO 4 Rch zero-flag output pin 19 IOPORT10 I+/O General-purpose input/output pin / SDO 5 Lch zero-flag output pin 20 IOPORT11 I+/O General-purpose input/output pin / SDO 5 Rch zero-flag output pin 21 IOPORT12 I+/O General-purpose input/output pin / SDO 6 Lch zero-flag output pin / Chip address setting input pin 0 22 IOPORT13 I+/O General-purpose input/output pin / SDO 6 Rch zero-flag output pin / Chip address setting input pin 1 23 IOPORT14 I+/O General-purpose input/output pin / SDO 7 Lch zero-flag output pin / Chip address setting input pin 2 24 IOPORT15 I+/O General-purpose input/output pin / SDO 7 Rch zero-flag output pin / Chip address setting input pin 3 25 VDD V digital power supply pin (for internal circuits) 26 VSS - Digital ground pin 27 SDO0 O PCM output pin 28 SDO1 O PCM output pin 29 SDO2 O PCM output pin 30 SDO3 O PCM output pin 31 SDO4 O PCM output pin 32 SDO5 O PCM output pin 33 SDO6 O PCM output pin 34 SDO7 O PCM output pin 35 IOPORT16 I+/O General-purpose input/output pin / Overflow detection output pin 36 IOPORT17 I+/O General-purpose input/output pin / Program end detection output pin 37 IOPORT18 I+/O General-purpose input/output pin / 64fs clock output pin 38 IOPORT19 I+/O General-purpose input/output pin / fs clock output pin 39 VDD V digital power supply pin (for input/output pin) 40 RAMD0 I+/O Data input/output pin for external memory 0 41 RAMD1 I+/O Data input/output pin for external memory 1 42 RAMD2 I+/O Data input/output pin for external memory 2 43 RAMD3 I+/O Data input/output pin for external memory 3 44 RAMD4 I+/O Data input/output pin for external memory 4 45 RAMD5 I+/O Data input/output pin for external memory 5 46 RAMD6 I+/O Data input/output pin for external memory 6 47 RAMD7 I+/O Data input/output pin for external memory 7 48 RAMD8 I+/O Data input/output pin for external memory 8 49 RAMD9 I+/O Data input/output pin for external memory 9

8 - 8 - Chapter 2 Pin Function No. Name I/O Function 50 VDD V digital power supply pin (for internal circuits) 51 VSS - Digital ground pin 52 RAMD10 I+/O Data input/output pin for external memory RAMD11 I+/O Data input/output pin for external memory RAMD12 I+/O Data input/output pin for external memory VDD V digital power supply pin (for input/output pin) 56 RAMD13 I+/O Data input/output pin for external memory RAMD14 I+/O Data input/output pin for external memory RAMD15 I+/O Data input/output pin for external memory CASN O Column-address strobe output pin for external DRAM 60 RAMWEN O Write enable output pin for external memory 61 RAMOEN O Output-enable output pin for external memory 62 RASN O Row address strobe output pin for external DRAM 63 RAMA8 O Address output pin for external memory 8 64 RAMA7 O Address output pin for external memory 7 65 RAMA0 O Address output pin for external memory 0 66 RAMA6 O Address output pin for external memory 6 67 RAMA1 O Address output pin for external memory 1 68 VDD V digital power supply pin (for input/output pin) 69 RAMA5 O Address output pin for external memory 5 70 RAMA2 O Address output pin for external memory 2 71 RAMA4 O Address output pin for external memory 4 72 RAMA3 O Address output pin for external memory 3 73 RAMA9 O Address output pin for external memory 9 74 RAMA10 O Address output pin for external memory VDD V digital power supply pin (for internal circuits) 76 VSS - Digital ground pin 77 RAMA11 O Address output pin for external memory RAMA12 O Address output pin for external memory RAMA13 O Address output pin for external memory RAMA14 O Address output pin for external memory RAMA15 O Address output pin for external memory RAMA16 O Address output pin for external memory RAMA17 O Address output pin for external memory VDD V digital power supply pin (for input/output pin) 85 /CS Is Microprocessor interface Chip select input pin 86 SO Ot Microprocessor interface Data output pin 87 SI Is Microprocessor interface Data input pin 88 SCK Is Microprocessor interface Clock input pin 89 /IC Is Initial clear input pin 90 SDWCK I Word clock (fs) input pin for SDI/SDO interface 91 SDBCK Is Bit clock (64fs) input pin for SDI/SDO interface 92 SDI7 I PCM input pin 93 SDI6 I PCM input pin 94 SDI5 I PCM input pin 95 SDI4 I PCM input pin 96 SDI3 I PCM input pin 97 SDI2 I PCM input pin 98 SDI1 I PCM input pin 99 SDI0 I PCM input pin 100 VDD V digital power supply pin (for internal circuits) I : Input terminal Is: Schmitt trigger input terminal I+: Input terminal with pull-up circuit (*) O: Digital output terminal Ot: 3-state digital output terminal A : Analog terminal

9 Chapter 2 Pin Function * Built in pull-up circuit cannot be used for Hi-level output of the LSI, because of this ability is only keep Hi-level for input pin when it is open. Depending on a circuit, please use pull-up resistance. 2.3 Pin Description Serial Data Interface SDI7-0 PCM data input pins for the YSS920B. Up to 16 channels of PCM data can be input. Connect unused pins to VSS. Select the input format by setting the SDI register. SDO7-0 Output pins for the PCM signal processed by the DSP. Up to 16 channels of PCM data can be output. Select the output format by setting the SDO register. SDBCK and SDWCK Clock input pins for SDI input and SDO output. Input clock signals at 64fs to SDBCK and fs to SDWCK. See section 3.3, Serial Data Interface Format for the serial data format External Memory Interface RAMA17-0, RAMD15-0, RAMWEN, RAMOEN, CASN, and RASN Pins for connecting the external memory for data delay. See section 5.4-5, RAM Interface for the access timing Microprocessor Interface /CS, SCK, SI, and SO Four-line serial interfaces for reading/writing of the control register and for program downloading. See section 3.4, Microprocessor Interface Format for the interface format General-Purpose Input/Output Pins IOPORT19-0 IOPORT0 to IOPORT19 can be used as general-purpose input/output ports. Select whether to use the pins as input pins (IPORT) or output pins (OPORT) by setting the IOSEL 19-0 bits of the IOSEL registers (IOSEL_H, IOSEL_M, and IOSEL_L). If configured as an output pin (OPORT), you can select whether to output the value set to registers (OPORT_H, OPORT_M, and OPORT_L) or output various status signals by setting the OPSEL 19-0 bits of registers (OPSEL_H, OPSEL_M, and OPSEL_L). Functions of the IOPORT pins can be set as follows:

10 Chapter 2 Pin Function Bit position IOSEL setting OPSEL setting IOPORT function Remarks General input (IPORT) General input (IPORT) IOPORT7-0 can be used for the conditional branching of DSP programs. See Note 4). Combined use with chip address setting terminal. See Note 1) General input (IPORT) General output (OPORT) 1 1 Zero detection output See Note 2) General output 1 0 (OPORT) 1 1 Zero detection output See Note 2) General output 1 0 (OPORT) 1 1 Status output See Note 3) IOPORT7-0 can be used for the conditional branching of DSP programs. See Note 4). Note 1) Pins for chip address setting (IOPORT 15-12) These pins are also used as chip address setting pins: IOPORT chip address 0 (CA0) IOPORT chip address 1 (CA1) IOPORT chip address 2 (CA2) IOPORT chip address 3 (CA3) Note 2) ZEROF output pins (IOPORT 15-0) By setting the IOSEL and the OPSEL, IOPORT 15-0 operate as digital zero detection pins for SDO output signal. If the SD0 output signal remains at digital zero consecutively for the number of samples specified by the ZEROB register, the flag output pin of the corresponding channel is set to high. This flag output pin can be used for analog mute after DAC. The channels correspond to the pins as follows: IOPORT ZEROF0L (SDO0 Lch) IOPORT ZEROF0R (SDO0 Rch) IOPORT ZEROF1L (SDO1 Lch) IOPORT ZEROF1R (SDO1 Rch) IOPORT ZEROF2L (SDO2 Lch) IOPORT ZEROF2R (SDO2 Rch) IOPORT ZEROF3L (SDO3 Lch) IOPORT ZEROF3R (SDO3 Rch) IOPORT ZEROF4L (SDO4 Lch) IOPORT ZEROF4R (SDO4 Rch) IOPORT ZEROF5L (SDO5 Lch) IOPORT ZEROF5R (SDO5 Rch) IOPORT ZEROF6L (SDO6 Lch) IOPORT ZEROF6R (SDO6 Rch) IOPORT ZEROF7L (SDO7 Lch) IOPORT ZEROF7R (SDO7 Rch)

11 Chapter 2 Pin Function Note 3) Various status signal output pins By setting the IOSEL and the OPSEL, the following status signals will be output from each pin: IOPORT OVF IOPORT END IOPORT SDBCKO (64fs clock) IOPORT SDWCKO (fs clock) OVF END If overflow occurs in the operation result of the DSP, OVF is set to high. The high interval is from the occurrence of the overflow to the output start of the next PCM sample from the SDO interface. When the next PCM sample output starts, OVF is reset to low. This pin is used for DSP programming and debugging. END is set to high when the DSP program counter is active. It is set to low when all processes have been finished and the program counter stops. When the program is operating correctly, the pin is always set to low once per sample. If it is not, this indicates that the program has not finished correctly to the end. This pin is used for DSP programming and debugging. SDBCKO This pin outputs 64fs clock synchronized to the SDO output signal. This clock can be used as a 64fs clock for the devices in subsequent stages. The polarity of the SDBCKO clock can be selected by setting BCKOP of the SDO register. SDWCKO This pin outputs fs clock synchronized to the SDO output signal. This clock can be used as an fs clock for the devices in subsequent stages. The polarity of the SDWCKO clock can be selected by setting WCKOP of the SDO register. The structure of the LSI for each pin of IOPORT 19-0 is shown below: Structure of the LSI IPORT pull-up circuit IOPORT OPORT Zero detection or status signal OPSEL IOSEL Note 4) Branch condition setup When the pins are set to input mode, set a branch condition directly to each pin. When the pins are set to output mode, IOPORT output can be used as the branch condition.

12 Chapter 2 Pin Function Clock XI and XO Pins for connecting a crystal oscillator ( to MHz). Use a crystal oscillator with a fundamental wave. If an external clock is used, connect it to XI. Internal operation clock (ck) is set with the oscillating frequency of this crystal oscillator and the setting of the CKUP bit of the ERAM register. CKUP=0 CKUP=1 XI= MHz CK=30.72 MHz CK=40.96 MHz : : : XI= MHz CK=35.00 MHz CK=46.66MHz : : - XI= MHz CK=37.50 MHz CK=50.00MHz CPO, AVDD, and AVSS Pins for connecting external elements for the PLL used to generate a clock pulse in the DSP section. Connect a resistor and capacitors near the CPO as shown below. Connect decoupling capacitors near the pin between AVDD and AVSS. AVSS CPO AVDD +2.5 V 470 pf 1 kω 4700 pf + 10 µf 0.1 µf

13 Chapter 3 Function Description Chapter 3 Function Description 3.1 Register Map The YSS920B is controlled by reading/writing the registers below through the microprocessor interface (/CS, SCK, SI, and SO). See section 3.4, Microprocessor Interface Format for the microprocessor interface format. All the registers except addresses 0x13 and 0x14 are reset to 0 when initial clear (/IC=L) is executed. The initial values of addresses 0x13 and 0x14 are undefined. Address Name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 CHIP ADR CAE CA3-0 0x01 SDI NOEXP SDIFMT1-0 SDIBIT1-0 SDWP SDBP 0x02 SDO SDOFMT1-0 SDOBIT1-0 WCKOP BCKOP 0x03 ERAM CKUP RASREF ERAMMOD ERAMSEL1-0 0x04 IOSEL_H IOSEL x05 IOSEL_M IOSEL15-8 0x06 IOSEL_L IOSEL7-0 0x07 OPSEL_H OPSEL x08 OPSEL_M OPSEL15-8 0x09 OPSEL_L OPSEL7-0 0x0A OPORT_H OPORT x0B OPORT_M OPORT15-8 0x0C OPORT_L OPORT7-0 0x0D IPORT_H IPORT x0E IPORT_M IPORT15-8 0x0F IPORT_L IPORT7-0 0x10 MPCNT_H MPLOAD MPCLEARN DSPMUTEN MPCNT11-8 0x11 MPCNT_L MPCNT7-0 0x12 ZEROB ZEROB7-0 0x13 ZEROF_H ZEROF7R ZEROF7L ZEROF6R ZEROF6L ZEROF5R ZEROF5L ZEROF4R ZEROF4L 0x14 ZEROF_L ZEROF3R ZEROF3L ZEROF2R ZEROF2L ZEROF1R ZEROF1L ZEROF0R ZEROF0L 0x15 MI STATE MI7S MI6S MI5S MI4S MI3S MI2S MI1S MI0S 0x16 0x17 TEST TEST 0x18 : Invalid Output of SO pin is set to high impedance. 0x1F 0x20 MI00 MI0REG x21 MI01 MI0REG x22 MI02 MI0REG15-8 0x23 MI03 MI0REG7-0 0x24 MI10 MI1REG x25 MI11 MI1REG x26 MI12 MI1REG15-8 0x27 MI13 MI1REG7-0 0x28 MI20 MI2REG x29 MI21 MI2REG x2A MI22 MI2REG15-8 0x2B MI23 MI2REG7-0 0x2C MI30 MI3REG x2D MI31 MI3REG x2E MI32 MI3REG15-8 0x2F MI33 MI3REG7-0 0x30 MI40 MI4REG x31 MI41 MI4REG23-16

14 Chapter 3 Function Description Address Name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x32 MI42 MI4REG15-8 0x33 MI43 MI4REG7-0 0x34 MI50 MI5REG x35 MI51 MI5REG x36 MI52 MI5REG15-8 0x37 MI53 MI5REG7-0 0x38 MI60 MI6REG x39 MI61 MI6REG x3A MI62 MI6REG15-8 0x3B MI63 MI6REG7-0 0x3C MI70 MI7REG x3D MI71 MI7REG x3E MI72 MI7REG15-8 0x3F MI73 MI7REG7-0 0x40 : Invalid Output of SO pin is set to high impedance. 0x7E 0x7F DEVICE ID Note i) Do not write 1 in the shaded area in the above table, because test bits are allocated. ii) Do not access addresses 0x16 and 0x17 because they are test registers.

15 Chapter 3 Function Description Register Details 0x00 CHIP ADR Register CAE CA3 CA2 CA1 CA0 This register can be written only immediately after the falling edge of /CS. Reading is valid only when CAE = 0 or CAE = 1 and IOPORT15-12 = CA3-0. When CAE = 1 and IOPORT15-12 CA3-0, the read data is set to high impedance. bit7: CAE This bit specifies whether to make the CA3-0 settings valid. This bit can be written only immediately after the falling edge of /CS. This bit is cleared (set to 0) when /CS is set high. 0: The CA3-0 settings are invalid. Reading and writing are possible on all registers of the YSS920B. If only one device is used, set this bit to 0. 1: CA3-0 settings are valid. Reading and writing of the register are possible only when the values of IOPORT15-12 pins and the CA3-0 settings of the register are the same. If multiple YSS920B s are used, setting this bit to 1 and setting the chip address of each device to IOPORT15-12 and CA3-0 allow /CS to be shared (no need to prepare /CS for each device). (When /CS is shared, the controlled device is switched by changing the CA3-0 settings. See section 4.2, Peripheral Circuits (When Multiple YSS920Bs Are Used).) In this case, set IOSEL15-12=0 to set the IOPORT15-12 pins to input pins (IPORT). When CAE = 1, fix the values of the IOPORT15-12 pins. When multiple devices are used and /CS is shared, be sure to set CAE = 1 immediately after the falling edge of /CS. If you read the register without setting CAE = 1, the SO pin output of each device will be shorted (because CAE = 0). bit3-0: CA3-0 Chip address setting bits that specify the access rights to the register at address 0x01 and following registers. This bit is valid only when CAE = 1 and can be written only immediately after the falling edge of /CS. When the values of IOPORT15-12 pins and the CA3-0 settings are equal Reading and writing to the register at address 0x01 and following registers are possible. When the values of IOPORT15-12 pins and the CA3-0 settings are not equal Reading and writing to the register at address 0x01 and following registers are invalid and the output from the SO pin is set to high impedance.

16 Chapter 3 Function Description 0x01 SDI Register NOEXP SDIFMT1 SDIFMT0 SDIBIT1 SDIBIT0 SDWP SDBP bit7: NOEXP This bit specifies whether the 4-bit exponent section of the 32-bit floating-point data input through the SDI interface is discarded and handled as 0. 0: Exponent is valid. The input data is a 32-bit floating-point data. 1: Exponent is invalid. The input data is a fixed-point data. If the output data of the device that is connected to the SDI interface is of fixed-point format and the LSB bit and following bits are not 0s, set this bit to 1. If the output data of the device that is connected to the SDI interface is of fixed-point format and the LSB bit and following bits are 0s, set this bit to 0 or 1 (does not matter). If multiple YSS920B s are used and the data sent between the devices is of floating-point format, set this bit to 0. bit5-4: SDIFMT1-0 These bits specify the input format of the PCM input signal. 00: No delay format (left justified). 01: EIAJ format (right justified). 10: 1-bit delay format (left justified with 1-bit delay). 11: Invalid. bit3-2: SDIBIT1-0 These bits specify the data position when SDIFMT1-0 is 01 (right justified). 00: 16-bit mode. 01: 18-bit mode. 10: 20-bit mode. 11: 24-bit mode. bit1: SDWP This bit specifies the polarity of the SDI/SDO interface word clock (SDWCK). 0: SDI is Lch and Rch when the word clock is high and low, respectively. 1: SDI is Lch and Rch when the word clock is low and high, respectively. bit0: SDBP This bit specifies the polarity of the SDI/SDO interface bit clock (SDBCK). 0: The bit clock rises at the front of the input/output signal. 1: The bit clock rises in the middle of the input/output signal. * See section 3.3, Serial Data Interface Format for a description of the SDI interface format.

17 Chapter 3 Function Description x02 SDO Register SDOFMT1 SDOFMT0 SDOBIT1 SDOBIT0 WCKOP BCKOP bit5-4: SDOFMT1-0 These bits specify the output format of the PCM output signal. The format and register bit assignment are the same as SDIFMT : No delay format (left justified). 01: EIAJ format (right justified). 10: 1-bit delay format (left justified with 1-bit delay). 11: Invalid. bit3-2: SDOBIT1-0 These bits specify the data position when SDOFMT1-0 is 01 (right justified). The format and register bit assignment are the same as SDIBIT : 16-bit mode. 01: 18-bit mode. 10: 20-bit mode. 11: 24-bit mode. bit1: WCKOP This bit specifies the polarity of SDWCKO clock (fs). 0: The polarity of SDWCKO is the same as that of SDWCK. 1: The polarity of SDWCKO is opposite to that of SDWCK. The SDWCKO clock is output from the IOPORT19 pin by setting IOSEL19 =1 and OPSEL19 = 1. See AC Characteristics for details on the output timing. bit0: BCKOP This bit specifies the polarity of the SDBCKO clock (64fs). 0: The polarity of SDBCKO is the same as that of SDBCK. 1: The polarity of SDBCKO is opposite to that of SDBCK. The SDBCKO clock is output from the IOPORT18 pin by setting IOSEL18 =1 and OPSEL18 = 1. See AC Characteristics for details on the output timing.

18 Chapter 3 Function Description 0x03 ERAM Register CKUP RASREF ERAMMOD ERAMSEL1 ERAMSEL0 bit7: CKUP This bit controls the DSP s internal operating clock. The DSP s internal operating clock can be changed by setting the XI pin input clock and this bit. 0: Normal mode XI can be changed in the range of MHz to MHz. In this case, the DSP s internal operating clock CK is related to XI as follows: CK = XI*5/2 [MHz] 1: Clock up mode XI can be changed in the range of MHz to MHz. In this case, the DSP s internal operating clock CK is 4/3rds of normal mode. CK = (XI*5/2)*4/3 = XI*10/3 [MHz] The DSP s internal operating clock can be varied in the range of MHz to MHz according to the CKUP setting and XI frequency. XI Frequency CKUP Register CK External Memory MHz MHz DRAM/SRAM enable : 0 XI*5/2 Only SRAM enable MHz MHz Only SRAM enable MHz MHz Only SRAM enable : 1 XI*10/3 Only SRAM enable MHz MHz Only SRAM enable MHz MHz Only SRAM enable The maximum number of steps that can be executed per sample time, maxstep, is expressed as follows: maxstep = CK/fs* where fs is the sampling frequency in khz and CK is the internal clock CK in MHz. And, the processing performance increases as the DSP s internal operating clock is made faster. However, faster access time is also required of the memory. See the section of ERAMSEL1-0 (ERAM Register bit1-0) for details. bit3: RASREF Combined with DSPMUTEN, this bit forcibly performs /RAS only refresh on the external DRAM. /RAS only refresh is activated by setting DSPMUTEN = 0 and RASREF = 1. One cycle of /RAS only refresh is approximately 200 ns. Set RASREF = 0 when not performing /RAS only refresh. [Note] Some DRAMs require a /RAS only refresh cycle as an initial cycle after power on. If so, carry out the following procedure. 1) Power on. 2) Set RASREF = 1 by setting DSPMUTEN = 0 and ERAMSEL = 00. 3) Set RASREF = 0 after waiting for the required cycles.

19 Chapter 3 Function Description bit2: ERAMMOD This bit specifies the data storage mode of the external RAM. This bit is valid for all modes, DRAM/SRAM/fast SRAM, regardless of the ERAMSEL setting. 0: Floating-point mode The data is converted into 32-bit floating-point format consisting of 4-bit exponent and 28-bit mantissa and stored to the external RAM. The 4-bit exponent and the higher 12 bits of the mantissa are input or output from the RAMD7-0 pins; the lower 16 bits of the mantissa are input or output from the RAMD15-8 pins. Use floating-point mode when in DRAM mode (ERAMSEL1-0 = 00) or when in SRAM/fast SRAM mode (ERAMSEL1-0 = 1*) using two SRAM of 8-bit data width or a SRAM of 16-bit data width. 1: Fixed-point mode The data is converted into 16-bit fixed-point format and stored to the external RAM. 16-bit fixed-point data is input or output from the RAMD7-0 pins in two steps. The RAMD15-8 pins are always 0s. In some cases, fixed-point mode may produce better sound quality than floating-point mode when in SRAM/fast SRAM mode (ERAMSEL1-0 = 1*) using a single SRAM of 8-bit data width. Bus Data Sign MSB Mantissa LSB *2-3 Exponent *2-0 ERAMMOD=0 1st 2nd RAMD 7-0 RAMD st 2nd all 0 all ERAMMOD=1 ( via Linear Converter ) bit1-0: ERAMSEL1-0 These bits specify the external RAM type and access mode. 00: DRAM mode DRAM of the following specifications can be connected for the external memory when the DSP s internal operating clock CK is MHz. 4 Mbits or more ( words or more * 16 bits) Row address = A0-A8 or more and column address = A0-A8 or more Refresh = 8 ms or more per 512 cycle Fast page mode Access time 60 ns or less The delay from the rising edge of RAMOEN and CASN to the time when Read DATA is set to high impedance is 20 ns or less. DRAM cannot be used when the DSP s internal operating clock CK is MHz or faster. Use floating-point mode (ERAMMOD = 0) when using DRAM mode. [Connection] Connect the A0-A8, D0-D15, /WE, /RAS, /CAS of the DRAM to the RAMA0-RAMA8, RAMD0-RAMD15, RAMWEN, RASN, CASN pins of the YSS920B, respectively. Connect the /OE pin of the DRAM to the RAMOEN pin or GND of the YSS920B.

20 Chapter 3 Function Description 01: Do not use. 32-bit data is exchanged with the DRAM once every 6 clock cycles of the DSP s internal operating clock. The maximum number of accesses at sampling frequency fs [khz], maxaccess, varies depending on the DSP s internal operating clock CK [MHz] as follows: maxstep = CK/fs* maxaccess = (maxstep-7)/6 10: SRAM mode SRAM of the following specifications can be connected as the external memory. Note that the required access time varies depending on the DSP s internal operating clock CK [MHz]. One or two SRAMs of 2 Mbits or less ( words or less * 8 bits) Or, one SRAM of 4 Mbits or less ( words or less * 16 bits) The delay from the rising edge of RAMOEN to the time when Read DATA is set to high impedance is 1000/CK [ns] or less. Access time derived from the following equation is met. 3000/CK-30 [ns] [Example] 67 ns or less when CK = MHz. 43 ns or less when CK = MHz. [Connection] Connect the A0-A17, D0-D7 (or D0-D15), /WE, and /OE pins of the SRAM to the RAMA0-RAMA17, RAMD0-RAMD7 (or RAMD0-RAMD15), RAMWEN, and RAMOEN pins of the YSS920B, respectively. Leave unused pins of the YSS920B open. When using one SRAM of 8-bit data width, 16-bit data is exchanged with the SRAM once every 6 clock cycles of the DSP s internal operating clock. The maximum number of accesses at sampling frequency fs [khz], maxaccess, varies depending on the DSP s internal operating clock CK [MHz] as follows: maxstep = CK/fs* maxaccess = (maxstep-7)/6 11: Fast SRAM mode SRAM of the following specifications can be connected as the external memory. Note that the required access time varies depending on the DSP s internal operating clock CK. One or two SRAMs of 2 Mbits or less ( words or less * 8 bits) Or, one SRAM of 4 Mbits or less ( words or less * 16 bits) The delay from the rising edge of RAMOEN to the time when Read DATA is set to high impedance is 1000/CK [ns] or less. Access time derived from the following equation is met. 2000/CK-30 [ns] [Example] 35 ns or less when CK = MHz. 18 ns or less when CK = MHz. [Connection] Connect the A0-A17, D0-D7 (or D0-D15), /WE, and /OE pins of the SRAM to the RAMA0-RAMA17, RAMD0-RAMD7 (or RAMD0-RAMD15), RAMWEN, and RAMOEN pins of the YSS920B, respectively. Leave unused pins of the YSS920B open. When using one SRAM of 8-bit data width, 16-bit data is exchanged with the SRAM once every 4 clock cycles of the DSP s internal operating clock. The maximum number of accesses at sampling frequency fs [khz], maxaccess, varies depending on the DSP s internal operating clock CK [MHz] as follows: maxstep = CK/fs* maxaccess = (maxstep-5)/4

21 Chapter 3 Function Description [Note 1] [Note 2] [Note 3] Essentially, the same DSP program can be used in DRAM mode (ERAMSEL = 00) and SRAM mode (ERAMSEL = 10). However, note that in SRAM mode, write command immediately after the read cycle is prohibited. The DSP program for fast SRAM mode (ERAMSEL =11) cannot be used in SRAM mode. If floating-point mode (ERAMMOD = 0) is specified using a single SRAM of 8-bit data width in SRAM mode (ERAMSEL = 10) or fast SRAM mode (SRAMSEL = 11), the data is stored in 16-bit floating-point format consisting of 4-bit exponent and 12-bit mantissa. The mode, floating-point or fixed-point, that produces better sound quality varies depending on the DSP program. Check the actual sound to make the mode selection. If you connect the D0-D7 pins of another equivalent SRAM to the RAMD8-RAMD15 pins of the YSS920B and specify floating-point mode (ERAMMOD = 0), the data is stored in 32-bit floating-point format consisting of 4-bit exponent and 28-bit mantissa. Position the external memory as close to the YSS920B as possible to minimize the wiring capacitance. 0x04 IOSEL_H Register IOSEL19 IOSEL18 IOSEL17 IOSEL16 0x05 IOSEL_M Register IOSEL15 IOSEL14 IOSEL13 IOSEL12 IOSEL11 IOSEL10 IOSEL9 IOSEL8 0x06 IOSEL_L Register IOSEL7 IOSEL6 IOSEL5 IOSEL4 IOSEL3 IOSEL2 IOSEL1 IOSEL0 IOSEL_H, bit3-0: IOSEL19-16 IOSEL_M, bit7-0: IOSEL15-8 IOSEL_L, bit7-0: IOSEL7-0 These bits select whether the general-purpose input/output pins IOPORT19-0 are used as input pins (IPORT) or output pins (OPORT). Set input or output for each pin separately. 0: The pin corresponding to the register bit is set to input (IPORT). [Example] If IOSEL0 = 0, the IOPORT0 pin is set to input. The signal input to the IPORT can be read through IPORT_H, M, and L registers. 1: The pin corresponding to the register bit is set to output (OPORT). [Example] If IOSEL0 = 1, the IOPORT0 pin is set to output. The signal output from the OPORT pin varies depending on OPSEL19-0 of the OPSEL_H, M, and L registers.

22 Chapter 3 Function Description 0x07 OPSEL_H Register OPSEL19 OPSEL18 OPSEL17 OPSEL16 0x08 OPSEL_M Register OPSEL15 OPSEL14 OPSEL13 OPSEL12 OPSEL11 OPSEL10 OPSEL9 OPSEL8 0x09 OPSEL_L Register OPSEL7 OPSEL6 OPSEL5 OPSEL4 OPSEL3 OPSEL2 OPSEL1 OPSEL0 OPSEL_H, bit3-0: OPSEL19-16 OPSEL_M, bit7-0: OPSEL15-8 OPSEL_L, bit7-0: OPSEL7-0 These bits specify the type of signal output from the pins when IOSEL19-0 = 1 and the general-purpose input/output pins IOPORT19-0 are set to output pins (OPORT). Specify the signal for each pin separately. 0: The values set to OPORT19-0 of the OPORT_H, M, and L registers are output from the corresponding pins. [Example] If IOSEL0 =1 and OPSEL0 = 0, the value set to OPORT_L register OPORT0 is output from the IOPORT0 pin. 1: The following signal is output from the corresponding pin. IOPORT0 ZEROF0L (SDO0 Lch zero flag) IOPORT1 ZEROF0R (SDO0 Rch zero flag) IOPORT2 ZEROF1L (SDO1 Lch zero flag) IOPORT3 ZEROF1R (SDO1 Rch zero flag) IOPORT4 ZEROF2L (SDO2 Lch zero flag) IOPORT5 ZEROF2R (SDO2 Rch zero flag) IOPORT6 ZEROF3L (SDO3 Lch zero flag) IOPORT7 ZEROF3R (SDO3 Rch zero flag) IOPORT8 ZEROF4L (SDO4 Lch zero flag) IOPORT9 ZEROF4R (SDO4 Rch zero flag) IOPORT10 ZEROF5L (SDO5 Lch zero flag) IOPORT11 ZEROF5R (SDO5 Rch zero flag) IOPORT12 ZEROF6L (SDO6 Lch zero flag) IOPORT13 ZEROF6R (SDO6 Rch zero flag) IOPORT14 ZEROF7L (SDO7 Lch zero flag) IOPORT15 ZEROF7R (SDO7 Rch zero flag) IOPORT16 OVF (Program overflow) IOPORT17 END (Program end) IOPORT18 SDBCKO (64fs clock) IOPORT19 SDWCKO (fs clock)

23 Chapter 3 Function Description x0A OPORT_H Register OPORT19 OPORT18 OPORT17 OPORT16 0x0B OPORT_M Register OPORT15 OPORT14 OPORT13 OPORT12 OPORT11 OPORT10 OPORT9 OPORT8 0x0C OPORT_L Register OPORT7 OPORT6 OPORT5 OPORT4 OPORT3 OPORT2 OPORT1 OPORT0 OPORT_H, bit3-0: OPORT19-16 OPORT_M, bit7-0: OPORT15-8 OPORT_L, bit7-0: OPORT7-0 When IOSEL19-0 = 1 and OPSEL19-0 = 0, the values set to OPORT19-0 bits are output from the corresponding IOPORT19-0 pins. [Example] If IOSEL0 =1 and OPSEL0 = 0, the value set to OPORT0 is output from the IOPORT0 pin. If IOSEL19-0 = 0, the IOPORT19-0 pins are set to input. Thus, the values set to OPORT19-0 are not output. If OPSEL = 1, various status signals are output. Thus, the values set to OPORT19-0 are not output.

24 Chapter 3 Function Description 0x0D IPORT_H Register IPORT19 IPORT18 IPORT17 IPORT16 0x0E IPORT_M Register IPORT15 IPORT14 IPORT13 IPORT12 IPORT11 IPORT10 IPORT9 IPORT8 0x0F IPORT_L Register IPORT7 IPORT6 IPORT5 IPORT4 IPORT3 IPORT2 IPORT1 IPORT0 IPORT_H, bit3-0: IPORT19-16 IPORT_M, bit7-0: IPORT15-8 IPORT_L, bit7-0: IPORT7-0 The data input to the IOPORT19-0 pins can be read through these registers when IOSEL19-0 = 0. [Example] If IOSEL0 = 0, the IOPORT0 pin input is set to the IPORT0 bit. The data equal to the output of the IOPORT19-0 pins can be read through these registers when IOSEL19-0 = 1. [Example] If IOSEL0 = 1 and OPSEL = 0, the value equal to OPORT0 is set to the IPORT0 bit. IPORT7-0 can be used for conditional branching of the DSP program. By setting IOSEL7-0 = 1, OPORT7-0 or ZEROF3R-0L can also be used for conditional branching. Note that if multiple YSS920Bs are used, IPORT15-12 also function as chip address setting pins. These registers are read-only.

25 Chapter 3 Function Description x10 MPCNT_H Register MPLOAD MPCLEARN DSPMUTEN MPCNT11 MPCNT10 MPCNT9 MPCNT8 0x11 MPCNT_L Register MPCNT7 MPCNT6 MPCNT5 MPCNT4 MPCNT3 MPCNT2 MPCNT1 MPCNT0 MPCNT_H bit7: MPLOAD This bit is set when downloading data to the coefficient RAM, program RAM, and address RAM. After setting this bit to 1, set /CS to low to download the data sequentially from the address specified by MPCNT11-0. This bit is cleared (to 0) when /CS is set high. See section 3.5, Program Download for details. MPCNT_H bit6: MPCLEARN This bit is used to clear all registers coefficient RAM, program RAM, and address RAM to 0s. Set this bit to 0 after setting DSPMUTEN = 0 (or at the same time) and the aforementioned RAMs are cleared 150 s later (be sure to combine with DSPMUTEN = 0). When downloading data to the RAMs and during normal use, be sure to set this bit to 1. MPCNT_H bit5: DSPMUTEN This bit specifies whether to forcibly mute the SDO output. 0: Mutes the SDO7-0 output. 1: Disables the muting of the SDO7-0 output. When DSPMUTEN is set to 0, the SDO7-0 output is muted, and, at the same time, the internal data RAM and external RAM are all cleared to 0. This bit does not clear the coefficient RAM, program RAM, and address RAM. The time it takes to clear the internal data RAM entirely is 70 s. The time it takes to clear the external RAM entirely is 26 ms. When downloading data to the coefficient RAM or address RAM, the DSPMUTEN can remain at 1. However, since noise may be generated depending on the DSP program, it is recommended that DSPMUTEN be set to 0 when downloading data. See section 3.5-5, When Overwriting Only the Coefficient RAM and 3.5-6, When Overwriting Only the Address RAM. Normally, when downloading program data to the program RAM, set DSPMUTEN = 0 in advance. Otherwise, noise may be generated in the SDO7-0 output. For the procedure of downloading the data with DSPMUTEN = 1, see section 3.5-7, When Overwriting Only the Program RAM. MPCNT_H bit3-mpcnt_l bit0: MPCNT11-0 These bits specify the load start address when downloading data to the coefficient RAM, program RAM, or address RAM (see section 3.5, Program Download for details).

26 Chapter 3 Function Description 0x12 ZEROB Register ZEROB7 ZEROB6 ZEROB5 ZEROB4 ZEROB3 ZEROB2 ZEROB1 ZEROB0 bit7-0: ZEROB7-0 When the higher 24 bits of the mantissa of the SDO7-0 L/Rch output are 0s consecutively for the number of samples specified by this register, the ZEROF** register corresponding to the channel is set to 1. The ZEROF** register value is undefined after setting this register until the specified time elapses. The lower 4-bits of the mantissa of the SDO output and the exponent do not take part in the ZEROF** detection. Below is the relationship of this register and the number of samples used for zero detection : 1 sample (when fs=44.1 khz s) : 257 samples (when fs=44.1 khz s) : 513 samples (when fs=44.1 khz s) : : : : samples (when fs=44.1 khz s) (the number of samples) = (ZEROB7-0) *

27 Chapter 3 Function Description x13 ZEROF_H Register ZEROF7R ZEROF7L ZEROF6R ZEROF6L ZEROF5R ZEROF5L ZEROF4R ZEROF4L 0x14 ZEROF_L Register ZEROF3R ZEROF3L ZEROF2R ZEROF2L ZEROF1R ZEROF1L ZEROF0R ZEROF0L ZEROF_H bit7-zerof_l bit0: ZEROF7R-0L When the higher 24 bits of the mantissa of the SDO7-0 L/Rch output are 0s consecutively for the number of samples specified by ZEROB7-0, the bit corresponding to the output channel is set to 1. Otherwise, it is set to 0. The lower 4-bits of the mantissa of the SDO output and the exponent are discarded in the ZEROF** detection. Below is the relationship between the bits and channels. ZEROF7R --- SDO7 Rch ZEROF7L --- SDO7 Lch ZEROF6R --- SDO6 Rch ZEROF6L --- SDO6 Lch ZEROF5R --- SDO5 Rch ZEROF5L --- SDO5 Lch ZEROF4R --- SDO4 Rch ZEROF4L --- SDO4 Lch ZEROF3R --- SDO3 Rch ZEROF3L --- SDO3 Lch ZEROF2R --- SDO2 Rch ZEROF2L --- SDO2 Lch ZEROF1R --- SDO1 Rch ZEROF1L --- SDO1 Lch ZEROF0R --- SDO0 Rch ZEROF0L --- SDO0 Lch If IOSEL15-0 = 1 and OPSE15-0 = 1, the value of these register is output from the IOPORT15-0 pins. These registers are read-only.

28 Chapter 3 Function Description 0x15 MI STATE Register MI7S MI6S MI5S MI4S MI3S MI2S MI1S MI0S bit7: MI7S This bit controls the status of the MI70-MI73 registers (described later). Carry out the procedure below to read the MI70-MI73 registers. 1) Write 0 to MI7S. 2) Read MI7S. MI7S = 0 indicates that the values of the MI70-MI73 registers have not yet been updated. MI7S = 1 indicates that the values of the MI70-MI73 registers have been updated. 3) After confirming that MI7S = 1, read the MI70-MI73 registers. When MI7S = 1, updating of the MI70-73 registers does not occur. bit6: MI6S This bit controls the status of the MI60-MI63 registers. The operation is the same as MI7S. bit5: MI5S This bit controls the status of the MI50-MI53 registers. The operation is the same as MI7S. bit4: MI4S This bit controls the status of the MI40-MI43 registers. The operation is the same as MI7S. bit3: MI3S This bit controls the status of the MI30-MI33 registers. The operation is the same as MI7S. bit2: MI2S This bit controls the status of the MI20-MI23 registers. The operation is the same as MI7S. bit1: MI1S This bit controls the status of the MI10-MI13 registers. The operation is the same as MI7S. bit0: MI0S This bit controls the status of the MI00-MI03 registers. The operation is the same as MI7S.

29 Chapter 3 Function Description x20 MI00 Register MI0REG31 MI0REG30 MI0REG29 MI0REG28 MI0REG27 MI0REG26 MI0REG25 MI0REG24 0x21 MI01 Register MI0REG23 MI0REG22 MI0REG21 MI0REG20 MI0REG19 MI0REG18 MI0REG17 MI0REG16 0x22 MI02 Register MI0REG15 MI0REG14 MI0REG13 MI0REG12 MI0REG11 MI0REG10 MI0REG9 MI0REG8 0x23 MI03 Register MI0REG7 MI0REG6 MI0REG5 MI0REG4 MI0REG3 MI0REG2 MI0REG1 MI0REG0 MI00 bit7- MI03 bit0: MI0REG31-0 By outputting the computed results of the internal DSP to this register, the results can be read via the microprocessor interface. How the results are used depends on the DSP program loading the results. If the DSP computed results are output in floating-point format, 4-bit exponent and 28-bit mantissa are output to MI0REG31-28 and MI0REG27-0, respectively (32 bits total). If the DSP computed results are output in fixed-point format, 0s and 28-bit fixed-point data are output to MI0REG31-28 and MI0REG27-0, respectively. Read these registers by controlling the MI0S bit of the MI STATE register. Using these registers allow debugging of the DSP program, level detection via the microprocessor, and so on. These registers are read-only.

30 Chapter 3 Function Description 0x24 MI10 Register MI1REG31 MI1REG30 MI1REG29 MI1REG28 MI1REG27 MI1REG26 MI1REG25 MI1REG24 0x25 MI11 Register MI1REG23 MI1REG22 MI1REG21 MI1REG20 MI1REG19 MI1REG18 MI1REG17 MI1REG16 0x26 MI12 Register MI1REG15 MI1REG14 MI1REG13 MI1REG12 MI1REG11 MI1REG10 MI1REG9 MI1REG8 0x27 MI13 Register MI1REG7 MI1REG6 MI1REG5 MI1REG4 MI1REG3 MI1REG2 MI1REG1 MI1REG0 MI10 bit7- MI13 bit0: MI1REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI1S bit of the MI STATE register.

31 Chapter 3 Function Description x28 MI20 Register MI2REG31 MI2REG30 MI2REG29 MI2REG28 MI2REG27 MI2REG26 MI2REG25 MI2REG24 0x29 MI21 Register MI2REG23 MI2REG22 MI2REG21 MI2REG20 MI2REG19 MI2REG18 MI2REG17 MI2REG16 0x2A MI22 Register MI2REG15 MI2REG14 MI2REG13 MI2REG12 MI2REG11 MI2REG10 MI2REG9 MI2REG8 0x2B MI23 Register MI2REG7 MI2REG6 MI2REG5 MI2REG4 MI2REG3 MI2REG2 MI2REG1 MI2REG0 MI20 bit7- MI23 bit0: MI2REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI2S bit of the MI STATE register.

32 Chapter 3 Function Description 0x2C MI30 Register MI3REG31 MI3REG30 MI3REG29 MI3REG28 MI3REG27 MI3REG26 MI3REG25 MI3REG24 0x2D MI31 Register MI3REG23 MI3REG22 MI3REG21 MI3REG20 MI3REG19 MI3REG18 MI3REG17 MI3REG16 0x2E MI32 Register MI3REG15 MI3REG14 MI3REG13 MI3REG12 MI3REG11 MI3REG10 MI3REG9 MI3REG8 0x2F MI33 Register MI3REG7 MI3REG6 MI3REG5 MI3REG4 MI3REG3 MI3REG2 MI3REG1 MI3REG0 MI30 bit7- MI33 bit0: MI3REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI3S bit of the MI STATE register.

33 Chapter 3 Function Description x30 MI40 Register MI4REG31 MI4REG30 MI4REG29 MI4REG28 MI4REG27 MI4REG26 MI4REG25 MI4REG24 0x31 MI41 Register MI4REG23 MI4REG22 MI4REG21 MI4REG20 MI4REG19 MI4REG18 MI4REG17 MI4REG16 0x32 MI42 Register MI4REG15 MI4REG14 MI4REG13 MI4REG12 MI4REG11 MI4REG10 MI4REG9 MI4REG8 0x33 MI43 Register MI4REG7 MI4REG6 MI4REG5 MI4REG4 MI4REG3 MI4REG2 MI4REG1 MI4REG0 MI40 bit7- MI43 bit0: MI4REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI4S bit of the MI STATE register.

34 Chapter 3 Function Description 0x34 MI50 Register MI5REG31 MI5REG30 MI5REG29 MI5REG28 MI5REG27 MI5REG26 MI5REG25 MI5REG24 0x35 MI51 Register MI5REG23 MI5REG22 MI5REG21 MI5REG20 MI5REG19 MI5REG18 MI5REG17 MI5REG16 0x36 MI52 Register MI5REG15 MI5REG14 MI5REG13 MI5REG12 MI5REG11 MI5REG10 MI5REG9 MI5REG8 0x37 MI53 Register MI5REG7 MI5REG6 MI5REG5 MI5REG4 MI5REG3 MI5REG2 MI5REG1 MI5REG0 MI50 bit7- MI53 bit0: MI5REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI5S bit of the MI STATE register.

35 Chapter 3 Function Description x38 MI60 Register MI6REG31 MI6REG30 MI6REG29 MI6REG28 MI6REG27 MI6REG26 MI6REG25 MI6REG24 0x39 MI61 Register MI6REG23 MI6REG22 MI6REG21 MI6REG20 MI6REG19 MI6REG18 MI6REG17 MI6REG16 0x3A MI62 Register MI6REG15 MI6REG14 MI6REG13 MI6REG12 MI6REG11 MI6REG10 MI6REG9 MI6REG8 0x3B MI63 Register MI6REG7 MI6REG6 MI6REG5 MI6REG4 MI6REG3 MI6REG2 MI6REG1 MI6REG0 MI60 bit7- MI63 bit0: MI6REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI6S bit of the MI STATE register.

36 Chapter 3 Function Description 0x3C MI70 Register MI7REG31 MI7REG30 MI7REG29 MI7REG28 MI7REG27 MI7REG26 MI7REG25 MI7REG24 0x3D MI71 Register MI7REG23 MI7REG22 MI7REG21 MI7REG20 MI7REG19 MI7REG18 MI7REG17 MI7REG16 0x3E MI72 Register MI7REG15 MI7REG14 MI7REG13 MI7REG12 MI7REG11 MI7REG10 MI7REG9 MI7REG8 0x3F MI73 Register MI7REG7 MI7REG6 MI7REG5 MI7REG4 MI7REG3 MI7REG2 MI7REG1 MI7REG0 MI70 bit7- MI73 bit0: MI7REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI7S bit of the MI STATE register. 0x7F DEVICE ID Register bit7-0 This register indicates the device ID. The device ID of the YSS920B is 0x02. This register is read-only.

37 Chapter 3 Function Description Serial Data Interface Format The PCM signal is input/output via the SDI and SDO interfaces SDI Interface (Serial Data Input) Below are the serial data input formats according to the SDI register settings. The input signal from the SDI7-0 pins is always handled as 32-bit data consisting of 4-bit exponent and 28-bit mantissa regardless of the settings. Lch 1 Frame Rch SDWCK SDWP=0 SDWP=1 SDBCK SDBP=0 SDBP=1 SDIFMT1-0=00 SDIBIT1-0=XX M Lch L M No Delay L Rch M LM L Mantissa Exponent Mantissa Exponent SDIFMT1-0=10 SDIBIT1-0=XX LM Lch 1bit Delay LM L M Rch L M L SDI7 SDI0 SDIFMT1-0=01 SDIBIT1-0=00 Rch LM L M EIAJ Lch Rch LM L M 16 bits 16 bits SDIFMT1-0=01 SDIBIT1-0=01 Rch LM L M Lch Rch L M LM 18 bits 18 bits SDIFMT1-0=01 SDIBIT1-0=10 Rch L M LM Lch Rch L M LM 20 bits 20 bits SDIFMT1-0=01 SDIBIT1-0=11 Rch LM L M Lch Rch L M L M 24 bits 24 bits M : MSB L : LSB

38 Chapter 3 Function Description SDO Interface (Serial Data Output) Below are the serial data output formats according to the SDO register settings. The SDO7-0 pins always output 32-bit data consisting of 4-bit exponent and 28-bit mantissa regardless of the format. If the SDO7-0 output is passed to another device such as a D/A converter, specify fixed-point (linear) output in the DSP program of the YSS920B. In addition, if multiple YSS920Bs are used, you can specify floating-point output to pass 32-bit data consisting of 4-bit exponent and 28-bit mantissa between the devices. Lch 1 Frame Rch SDWCK SDWP=0 SDWP=1 SDBCK SDBP=0 SDBP=1 SDOFMT1-0=00 SDOBIT1-0=XX M Lch L M No Delay L Rch M L M L Mantissa Exponent Mantissa Exponent SDOFMT1-0=10 SDOBIT1-0=XX L M Lch 1bit Delay LM L M Rch L M L SDO7 SDO0 SDOFMT1-0=01 SDOBIT1-0=00 Rch L M L M EIAJ Lch Rch LM L M 16 bits 16 bits SDOFMT1-0=01 SDOBIT1-0=01 Rch LM L M Lch Rch L M LM 18 bits 18 bits SDOFMT1-0=01 SDOBIT1-0=10 Rch L M L M Lch Rch L M LM 20 bits 20 bits SDOFMT1-0=01 SDOBIT1-0=11 Rch L M L M Lch Rch L M L M 24 bits 24 bits M : MSB L : LSB

39 Chapter 3 Function Description Microprocessor Interface Format Reading and writing of registers are performed through the four-wire serial interface indicated below When /CS Is Used Only By One Device /CS SCK write R/W = L SI SO Don't Care A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D3 D4 D5 D6 D7 Don't Care High impedance read R/W = H SI SO Don't Care A0 A1 A2 A3 A4 A5 A6 R/W Don't Care Don't Care High impedance D0 D1 D2 D3 D4 D5 D6 D7 High impedance SO is set to output mode only when all of the conditions below are met. /CS=L Read operation on a valid address setting During (8-bit) data output timing In all other cases, the interface is set to high impedance, and SO, SI, and SCK can be shared with devices having similar interfaces. If multiple YSS920Bs are used, /CS can be shared by specifying the CHIP ADR registers CA3-0. See section If the general-purpose output pins (IOPORT19-0) are used as input pins (IPORT), the value of the IOPORT (IPORT) during the R/W period indicated above is read from the SO pin. If used as output pins (OPORT), the output of the IOPORT (OPORT) switches at time D7 indicated above. [Note] Set /CS = high during initial clear (/IC = low).