EPL COM / 132 SEG LCD

Transcription

1 Crystalfontz Thiscontrolerdatasheetwasdownloadedfrom htp:/wwwcrystalfontzcom/controlers/ EPL COM / 32 SEG LCD Driver Product Specification DOC VERSION 8 ELAN MICROELECTRONICS CORP January 26

2 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM Windows is a trademark of Microsoft Corporation ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation Copyright 26 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification Such information and material may change to conform to each confirmed order In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems Use of ELAN Microelectronics product in such applications is not supported and is prohibited NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS ELAN MICROELECTRONICS CORPORATION Headquarters: No 2, Innovation Road Hsinchu Science Park Hsinchu, Taiwan 377 Tel: Fax: Europe: Elan Microelectronics Corp (Europe) Siewerdtstrasse 5 85 Zurich, SWITZERLAND Tel: Fax: Hong Kong: Elan (HK) Microelectronics Corporation, Ltd Rm 5B, /F Empire Centre 68 Mody Road, Tsimshatsui Kowloon, HONG KONG Tel: Fax: elanhk@emccomhk Shenzhen: Elan Microelectronics Shenzhen, Ltd SSMEC Bldg, 3F, Gaoxin S Ave Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: Fax: USA: Elan Information Technology Group (USA) 82 Saratoga Ave, Suite 25 Saratoga, CA 957 USA Tel: Fax: Shanghai: Elan Microelectronics Shanghai, Ltd 23/Bldg #5 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: Fax:

3 Contents Contents General Description 2 Features 3 Applications 2 4 Pin Configurations 2 4 Pad Coordinates 3 5 Block Diagram 6 6 Pin Description 7 6 Power Supply7 62 LCD Driver Supply 7 63 System Control 8 64 MPU Interface 9 65 LCD Driver Output 7 Function Description 7 MPU Interface 7 Chip Select 72 Selecting the Interface Type2 72 Data Transfer 3 72 Display Data RAM Programmable Duty Ratio6 73 LCD Driver Circuits 8 73 Display Data Latch Circuit8 732 Shift Register Circuit8 734 Common Driver Circuit2 735 Segment Driver Circuit LCD Driving Waveform23 74 Internal Power Circuits23 74 Voltage Converter Circuits Voltage Regulator Circuits Voltage Follower Circuits26 75 LCD Display Circuits Oscillator /DOF Pin Description Display Timing Generator Circuit Oscillator Frequency The Reset Circuit 29 Product Specification (V8) 226 iii

4 Contents 8 Instruction Description 3 8 Read Display Data 3 82 Write Display Data 3 83 Read Status Set Duty Ratio (Two-Byte Instruction)32 84 Set Duty Ratio Mode (First Instruction) Set Duty Ratio Register (Second Instruction) Set Display Clock CL Frequency (Two-Byte Instruction) Set CL Frequency Select Mode (First Instruction) Set CL Frequency Select Register (Second Instruction) Select LCD Bias (Two-Byte Instruction)33 86 Set the LCD Bias Select Mode (First Instruction) Set the LCD Bias Select Register (Second Instruction)33 87 Display On/Off34 88 Initial Display Line Electronic Contrast Control Set (Two-Byte instruction)34 89 Set Contrast Control Mode (First Instruction) Set Contrast Control Register (Second Instruction)34 8 Set Page Address 35 8 Set Column Address ADC Select Inverse Display On/Off36 84 Entire Display On/Off Set Modify-Read Reset Modify-Read Reset37 88 SHL Select Power Control Set High Power Mode Regulator Resistor Select Set Status Indicator (Two-Byte Instruction) Set Status Indicator Mode (First Instruction) Set Static Indicator Register (Second Instruction) Power Save (Compound Instruction) Sleep Mode Standby Mode 4 iv Product Specification (V8) 226

5 Contents 9 Application Information 4 9 Instruction Procedure Examples 4 9 Initial Setup4 92 Program Examples 44 Electrical Characteristics 47 Absolute Maximum Ratings 47 2 Recommended Operating Conditions47 3 DC Characteristics 48 4 AC Characteristics 49 4 Serial Interface Timing Characteristics Family MPU Read/Write Timing Characteristics Family MPU Read/Write Timing Characteristics5 Pin Configuration 52 Input Pin Configuration 52 2 Input/Output Pin Configuration52 3 Output Pin Configuration53 4 Reset Input Pin Configuration 53 5 LCD Output Pin Configuration 54 2 MPU Interface 55 2 Elan 8-bit MPU (with external memory) Serial Interface (SPI) Family MPU Family MPU 56 3 Application Circuits 57 Product Specification (V8) 226 v

6 Contents Specification Revision History Doc Version Revision Description Date Drafting version 2/4/ 2 Initial version 2/4/ Modified the DC and AC characteristics 2 Modified the Select LCD bias instruction 3 Added Set display clock frequency instruction Modified the error of voltage bias divider 2 Modified the voltage follower block diagram Added Regulator resistor select register in reset instruction 2 Added Voltage converter capacitor connection 3 Delete the busy state (without busy check) 4 Add DC current spec Added one more VDD and VSS pad 2 Modified the Pad sequence and configuration Modified the operating temperature range: -3 to 8 C 2 Added program examples Added high power mode instruction 2 Modifed the pad and pitch size 2/5/5 2/6/8 2/9/5 2/3/2 2/9/7 2//3 9 Modified the Pad Coordinates 22/3/7 Modified the DC Characteristics: Reference voltage and Dynamic current consumption 22/3/9 Added LCD power on sequence 22/3/28 2 Add at the DC characteristics: Regulated voltage 2 Added Pin Configuration 22/6/6 3 Added ELAN logo on the Pin Configuration 23/4/3 4 Modified the read timing of /WR 23/8/4 5 Adjusted the Data RAM arrangement 23/2/ Modified the table on the relationship between duty ratio and common output 2 Modified the A voltage level on the Display ON/OFF instruction Added Notes after the Pad Coordinates table 2 Modified the table on the Relationship between Duty Ratio and Common Output Modified the TEST pin description 2 Added V4 voltage range on the AC Characteristics table 24/2/27 24/8/9 26//2 vi Product Specification (V8) 226

7 EPL COM / 32 SEG LCD Driver General Description The EPL6532 is a driver and controller LSI for graphic dot-matrix liquid crystal display systems It can be interfaced to the MPU via serial or 8-bit interface It contains 65 common and 32 segment driver circuits With one chip, it is possible to drive a graphic display system with a maximum of dots 2 Features Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM : 32 x 65 = 858 bits 97 LCD Drivers : 32-seg segment drivers, 64-common drivers and -icon Serial Interface (SPI) or 8-Bit Parallel Interface Mode (8-series, 68-series MPU) On-chip oscillator circuit Multi-chip operation (Master, Slave) available Programmable Duty Ratio : Duty ratio Common Segment : 64 (+ ICON) 64 (+ ICON) 32 : 48 (+ ICON) 48 (+ ICON) 32 : 42 (+ ICON) 42 (+ ICON) 32 : 36 (+ ICON) 36 (+ ICON) 32 : 32 (+ ICON) 32 (+ ICON) 32 : 24 (+ ICON) 24 (+ ICON) 32 : 6 (+ ICON) 6 (+ ICON) 32 : 8 (+ ICON) 8 (+ ICON) 32 Note: ICON = : Pin disable ICON = : Pin enable Selectable LCD driving bias level : /4, /45, /5, /55, /6, /65, /7, /75, /8, /85, /9 bias Selectable LCD display clock frequency Electronic contrast control functions (64 steps) Built-in Instruction Set : Display data read/write, Display on/off, Inverse display, Page address set, Common address set, LCD display contrast control, Set Sleep mode, Standby mode, etc Operating Voltage range : Supply voltage : 22V to 55 V LCD driving voltage : 4V to 5V Product Specification (V8) 226

8 EPL COM / 32 SEG LCD Driver 3 Applications Organizer Scientific calculator Graphic pager Electronic Dictionary Cellular phone Handy Terminals (PDA) 4 Pin Configurations DDRAM Figure Pin Configuration Item Pad No X Size Chip size Pad size (Type A) Pad size (Type B) Pad pitch Y Type A 95 Type B 85 Unit um 2 Product Specification (V8) 226

9 EPL COM / 32 SEG LCD Driver 4 Pad Coordinates Pad No Symbol X Y Pad No Symbol X Y COM MS COM PS COM FR COM C COM /DOF COM CLS COM CL COM OSC COM FRS COM IRS COM /RES COM D COM D COM D COM D COM D COM D COM D COM D COM CS COM /CS COM A COM /WR COM /RD COM TEST COM COM COM COM COM COM COM COM COM COM COM COM COM COM COMI COM VDD COM VDD COM C COM C COM C COM C COM C COM C COM VOUT COM V COM V COM V COM V COM V COM VR COM GND COM GND COM Product Specification (V8) 226 3

10 EPL COM / 32 SEG LCD Driver Pad No Symbol X Y Pad No Symbol X Y COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COMI SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG Product Specification (V8) 226

11 EPL COM / 32 SEG LCD Driver Pad No Symbol X Y 2 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG Note: For PCB layout, the IC substrate must be connected to VSS or floating Refer to the relationship between Duty Ratio and Common Output Product Specification (V8) 226 5

12 EPL COM / 32 SEG LCD Driver 5 Block Diagram SEG SEG3 COM COM63 COMI V V V2 V3 V4 VSS SEGMENT DRIVER CIRCUITS COMMON DRIVER CIRCUITS Voltage Followers LATCH CIRCUIT SHIFT REGISTER VR VOUT C+,C- C2+,C2- C3,C4 Voltage Regulator Voltage Converter PAGE ADDRESS REGISTER LOW ADDRESS DECODER DISPLAY DATA RAM COLUMN ADDRESS DECODER LINE ADDRESS DECODE LINE COUNTER INITIAL DISPLAY LINE REGISTER FR COLUMN ADDRESS COUNTER COLUMN ADDRESS REGISTER Display Timing Generator Circuit CL /DOF FRS M/S Bus holder INSTRUCTION DECODER INSTRUCTION REGISTER STATUS REGISTER Oscillator CLS OSC MPU Interface I/O Buffer ( Serial / Parallel ) IRS /CSCS2 A /RD /WR C86 P/S /RES D7 D6 D5 D4 D3 D2 D (E) (R/W) (SDI)(SCK)(SDO) Figure 2 System Block Diagram D 6 Product Specification (V8) 226

13 EPL COM / 32 SEG LCD Driver 6 Pin Description 6 Power Supply Name I/O Description VDD Power VDD Power Supply VSS Power V (GND) LCD driver supply voltages The voltage applied is determined by the LCD pixel and is changed through changing the impedance using an operational amplifier (OPA) for various applications Voltage levels are determined based on V, and must maintain the relative magnitudes shown below: V V V2 V3 V4 Vss When the internal power circuit is active, these voltages are generated according to the state of the LCD bias, The selection of voltages is determined by the LCD bias select instruction, as shown in the table below V V V2 V3 V4 Power LCD Bias V V2 V3 V4 /9 Bias (8/9) V (7/9) V (2/9) V (/9) V /85 Bias (75/85) V (65/85) V (2/85) V (/85) V /8 Bias (7/8) V (6/8) V (2/8) V (/8) V /75 Bias (65/75) V (55/75) V (2/75) V (/75) V /7 Bias (6/7) V (5/7) V (2/7) V (/7) V /65 Bias (55/65) V (45/65) V (2/65) V (/65) V /6 Bias (5/6) V (4/6) V (2/6) V (/6) V /55 Bias (45/55) V (35/55) V (2/55) V (/55) V /5 Bias (4/5) V (3/5) V (2/5) V (/5) V /45 Bias (35/45) V (25/45) V (2/45) V (/45) V /4 Bias (3/4) V (2/4) V (2/4) V (/4) V 62 LCD Driver Supply Name I/O Description C+ C- O Boosted capacitor connecting terminals used for voltage booster C2+ C2- O Boosted capacitor connecting terminals used for voltage booster C3 C4 O Boosted capacitor connecting terminals used for voltage booster VOUT I/O Voltage converter output VR I V voltage adjustment pin Product Specification (V8) 226 7

14 EPL COM / 32 SEG LCD Driver 63 System Control Name I/O Description Master/slave operation select pin - MS = "H": Master operation - MS = "L": Slave operation M/S P/S FR C68 /DOF I I I/O I I/O M/S CLS OSC Power Supply Circuit CL FR FRS /DOF H H Available Available O O O O L Unavailable Available O O O O L * Unavailable Unavailable I I Hi-Z I Note: * : Don t Care O : Output I : Input Select Interface mode of the MPU When PS = "High": Parallel interface mode When PS = "Low": Serial interface mode LCD AC signal input/output pin When is used in master/slave mode (multi-chip), the FR pins must be connected each other - MS = H : Output - MS = L : Input Select the kind of MPU interface When C68 = "High": 68-series MPU interface mode When C68 = "Low": 8-series MPU interface LCD Display blanking control pin In multi-chip mode, the /DOF pin must be connected to each other M/S = H (Master) : /DOF is output pin Display On = H, Display Off = L M/S = L (Slave) : /DOF is input pin Via external control Refer to the following table Instruction H /DOF Display On On Off Display Off Off Off L CLS I Internal oscillator circuit enable / disable select pin CLS = H : Internal oscillator circuit is enable CLS = L : Internal oscillator circuit is disable (External display clock input to OSC pin) Display clock input/output pin When the EPL6532 is used in master/slave mode (multi-chip), the CL pins must be connected to each other CL I/O M/S H CL Output L Input 8 Product Specification (V8) 226

15 EPL COM / 32 SEG LCD Driver Name I/O Description OSC I When using an external oscillator, input the clock to OSC pin When using an internal oscillator, leave this pin open FRS O Static driver output pin This pin is used in combination with the FR pin Internal resistor select pin This pin selects the resistors for adjusting V voltage level and is available IRS only in master mode I - IRS = "H": The internal resistors are used - IRS = "L": The external resistors are used V voltage is controlled using the external divider resistor connected to the VR pin TEST I Test pin Fixed at VSS 64 MPU Interface Name I/O Description /RES I Hardware reset input The LSI is reset when this signal is pulled low (Active low) These are the chip select signals The Chip Select of the LSI becomes active when CS is "L" and also CS2 is "H" and allows the input/output of data or commands /CS,CS2 I /CS CS2 Status L L The device is not active (D7~D is Hi-Z) L H Data and instruction are available H L The device is not active (D7~D is Hi-Z) H H The device is not active (D7~D is Hi-Z) A /WR (R/W) /RD (E) D to D7 I I I I/O Used as register selection input When A = "High", Data register When A = "Low", Instruction register When C68 = "High" (68-series MPU interfacing), used as read (/WR = "High"), write (/WR = "Low") When C68 = "Low" (8-series MPU interfacing), used as write enable input (/WR) When C68 = "High" (68-series MPU interfacing), used as read/write enable input (E) When C68 = "Low" (8-series MPU interfacing), used as read enable input (/RD) When in serial mode, D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin and the others are not used When in parallel mode, D to D7 are used as bi-directional data bus pin Product Specification (V8) 226 9

16 EPL COM / 32 SEG LCD Driver 65 LCD Driver Output Name I/O Description The LCD common output pins Scan Data FR COMs Output Voltage COM to COM63 O H L H L H L Vss V V V4 Power Save Mode Vss COMI SEG to SEG3 O O These are two icon display pins Both pins output the same signal Leave these pins open when they are not used The LCD segment output pins Display Data H L FR Power Saving Mode SEGs Output Voltage Normal Display Reverse Display H V V2 L Vss V3 H V2 V L V3 Vss Vss Refer to the relationship between Duty Ratio and Common Output Product Specification (V8) 226

17 EPL COM / 32 SEG LCD Driver 7 Function Description INSTRUCTION DECODER Bus holder INSTRUCTION REGISTER STATUS REGISTER MPU Interface I/O Buffer ( Serial/Parallel ) /CS CS2 A /RD /WR C86 P/S /RES D7 D6 D5 D4 D3 D2 D D (E) (R/W) (SDI)(SCK)(SDO) Figure 3 System Interface 7 MPU Interface 7 Chip Select The EPL6532 has two chip select pins /CS and CS2 When /CS="L" and CS2= H, MPU interface is available When the chip select pin is inactive (other /CS and CS2 condition), D7 to D are high impedance (invalid) and input of A, /RD, or /WR inputs are not effective If serial interface is selected, the shift register and counter are both reset However, reset is always operated in any conditions of /CS and CS2 P/S C68 A /WR /RD D~D4 D5 D6 D7 Serial Mode (L) Parallel mode SPI interface ( ) A R/W - * SDO SCK SDI 8-series (L) A /WR /RD D~D7 (H) 68-series (H) A R/W E D~D7 Note: * Don t care ( High, Low or Open ) Indicates that it is fixed to either High (VDD) or Low (VSS) Product Specification (V8) 226

18 EPL COM / 32 SEG LCD Driver 72 Selecting the Interface Type The EPL6532 can be operated with serial interface (SPI) and parallel interface (8- series or 68-series) as selected by the P/S pin Serial Interface (SPI) When serial mode (PS = "L"), D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin When the LSI is active (/CS= L, CS2= H ), serial data input (D7), serial clock input (D6) inputs and serial data output (D5) are enabled The 8-bit shift register and 3-bit counter are reset to the initial condition when the chip is not selected The data input/output from SDI/SDO terminal is MSB first as in the order of D7, D6 D, and is latched at the rising edge of the serial clock SCK Serial input data is display data when A="H" and instruction when A="L" The A input is read and identified at the rising edge of the (8 n) serial clock pulse Since the clock signal (D6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended /CS CS2 SCK (D6) SDI (D7) D7 D6 D5 D4 D3 D2 D D D7 SDO (D5) D7 D6 D5 D4 D3 D2 D D D7 A Figure 4 Serial Interface Signal Chart A /WR (R/W) D7 (SDI) D5 (SDO) Instruction Write Status Read Invalid Status Read Display Data Write Status Read Invalid Display Data Read 2 Product Specification (V8) 226

19 EPL COM / 32 SEG LCD Driver Parallel Interface (8-bit Length) Parallel mode (8-bit length): When parallel input is selected (PS = H ), D~D7 can be connected directly to the 8-series or 68-series MPU by setting the C86 pin to high or low A /RD /WR D7~D N D(N) D(N+) D(N+2) D(N+3) D(N+4) Writing Timing A /RD /WR D7~D N Dummy D(N) D(N+) D(N+2) D(N+3) Reading Timing Figure 5 Write and Read Timing Diagrams Common 8-Series 68-Series A /RD /WR R/W Description H L H H Display data read H H L L Display data write L L H H Register status read L H L L Writes to Instruction register 72 Data Transfer The EPL6532 uses a bus holder and an internal data bus for data transfer with MPU When writing data from the MPU to the DDRAM, data is automatically transferred from the bus holder to the DDRAM When reading data from the DDRAM to MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and MPU reads this stored data from bus holder for the next data read cycle Product Specification (V8) 226 3

20 EPL COM / 32 SEG LCD Driver 72 Display Data RAM PAGE ADDRESS REGISTER LOW ADDRESS DECODER DISPLAY DATA RAM LINE ADDRESS DECODE LINE COUNTER INITIAL DISPLAY LINE REGISTER COLUMN ADDRESS DECODER COLUMN ADDRESS COUNTER COLUMN ADDRESS REGISTER Figure 6 Display Data RAM Diagram The display data RAM (DDRAM) stores pixel data for the LCD It is a 65-row ((8- page 8-bit + ) x 32-column addressable array It is possible to access any required bit by specifying the page address and the column address The 65 rows are divided into 8 pages of 8 lines and the ninth page with a single line (D only) Each bit in the Display Data RAM corresponds to each pixel of the LCD panel Each bit in the Display Data RAM corresponds to each pixel of the LCD panel and controls the display by applying the following bit data When in Normal Display : On="", Off="" When in Inverse Display : On="", Off="" (Refer to the Inverse Display On/Off instruction for more details) Display Data RAM Normal Display Inverse Display Figure 7 Display Data RAM, Normal and Inverse Liquid Crystal Display Diagrams 4 Product Specification (V8) 226

21 EPL COM / 32 SEG LCD Driver Page Address Data P3, P2, P, P The microprocessor (MPU) can read from and write to the RAM through the I/O buffer Since the LCD controller operates independently, data can be written into the RAM at the same time as data is being displayed without causing the LCD to flicker Column Address Line Address (HEX) Common Output (/65,/64) Common Output (/49,/48) Common Output (/42,/36) Common Output (/33,/32) D Page COM COM COM COM D COM COM COM COM D2 2 COM2 COM2 COM2 COM2 D3 3 COM3 COM3 COM3 COM3 D4 4 COM4 COM4 COM4 COM4 D5 5 COM5 COM5 COM5 COM5 D6 6 COM6 COM6 COM6 COM6 D7 7 COM7 COM7 COM7 COM7 D Page 8 COM8 COM8 COM8 COM8 D 9 COM9 COM9 COM9 COM9 D2 A COM COM COM COM D3 B COM COM COM COM D4 C COM2 COM2 COM2 COM2 D5 D COM3 COM3 COM3 COM3 D6 E COM4 COM4 COM4 COM4 D7 F COM5 COM5 COM5 COM5 D Page 2 COM6 COM6 COM6 COM6 D COM7 COM7 COM7 COM7 D2 2 COM8 COM8 COM8 COM8 D3 3 COM9 COM9 COM9 COM9 D4 4 COM2 COM2 COM2 COM2 D5 5 COM2 COM2 COM2 COM2 D6 6 COM22 COM22 COM22 COM22 D7 7 COM23 COM23 COM23 COM23 D Page 3 8 COM24 COM24 COM24 COM24 D 9 COM25 COM25 COM25 COM25 D2 A COM26 COM26 COM26 COM26 D3 B COM27 COM27 COM27 COM27 D4 C COM28 COM28 COM28 COM28 D5 D COM29 COM29 COM29 COM29 D6 E COM3 COM3 COM3 COM3 D7 F COM3 COM3 COM3 COM3 D Page 4 2 COM32 COM32 COM32 D 2 COM33 COM33 COM33 D2 22 COM34 COM34 COM34 D3 23 COM35 COM35 COM35 D4 24 COM36 COM36 COM36 D5 25 COM37 COM37 COM37 D6 26 COM38 COM38 COM38 D7 27 COM39 COM39 COM39 D Page 5 28 COM4 COM4 COM4 D 29 COM4 COM4 COM4 D2 2A COM42 COM42 D3 2B COM43 COM43 D4 2C COM44 COM44 D5 2D COM45 COM45 D6 2E COM46 COM46 D7 2F COM47 COM47 Product Specification (V8) 226 5

22 EPL COM / 32 SEG LCD Driver Page Address Data P3, P2, P, P Column Address Line Address (HEX) Common Output (/65,/64) Common Output (/49,/48) Common Output (/42,/36) Common Output (/33,/32) D Page 6 3 COM48 D 3 COM49 D2 32 COM5 D3 33 COM5 D4 34 COM52 D5 35 COM53 D6 36 COM54 D7 37 COM55 D Page 7 38 COM56 D 39 COM57 D2 3A COM58 D3 3B COM59 D4 3C COM6 D5 3D COM6 D6 3E COM62 D7 3F COM63 D Page 8 COMI COMI COMI ADC Column = Address(HEX) ADC = LCD Output 8 3 S E G 8 2 S E G 2 8 S E G S E G S E G S E G 3 3 S E G Programmable Duty Ratio The duty ratio is selected by using the Set Duty Ratio instruction The common output circuits are shown in the following figure They are separated into three shift registers and controlled by the "duty ratio register" COM COM3 COM32 COM63 COMI COMMON DRIVER (32) COMMON DRIVER (32) COMMON DRIVER () 32-Bit SHIFT REGISTER 32-Bit SHIFT REGISTER -bit SHIFT REGISTER 4 DUTY RATIO REGISTER Figure 8 Common Output Circuits 6 Product Specification (V8) 226

23 EPL COM / 32 SEG LCD Driver Duty SHL Common Output Pins (COMxx, refer to the Pad No) COM ~ 3 ~7 ~ ~5 ~7 ~2 ~23 ~ 4~ 43~ 46~ 48~ 52~ 56~ COM6 ~ 63 COMI /9 CCOM[3] CCOM[47] COMI /8 CCOM[74] CCOM[3] /7 CCOM[7] CCOM[85] COMI /6 CCOM[58] CCOM[7] /25 CCOM[] CCOM[223] COMI /24 CCOM[232] CCOM[] Line Address (Pages ~7) /33 CCOM[5] CCOM[63] COMI /32 CCOM[36] CCOM[5] /37 CCOM[7] CCOM[835] COMI /36 CCOM[358] CCOM[7] /43 CCOM[ 2] CCOM[2 4] COMI /42 COM[4 2] CCOM[2 ] /49 CCOM[ 23] CCOM[24 47] COMI /48 CCOM[47 24] CCOM[23 ] /65 /64 CCOM[63] CCOM[63] COMI Relationship between Duty Ratio and Common Output Initial Display Line Register The initial display line register assigns a DDRAM line address which corresponds to COM by using the Initial display line set instruction It is used for not only normal display but also vertical display scrolling and page switching without changing the contents of the DDRAM However, the 65th address for icon display cannot be assigned for the initial display line address Line Counter The line counter provides a DDRAM line address It initializes its contents at the switching of frame reversal signal (FR), and also counts-up in synchronization with common timing signal Column Address Counter The column address counter is an 8-bit preset counter which provides a DDRAM column address, and is independent of the page address register It will increment (+) the column address whenever display data read or display data write instructions are issued However, the incrementing of the column address is stopped at column address 83H The count-lock will be released by the column address set instruction again The counter can invert the correspondence between the column address and segment driver direction by means of ADC select instruction Product Specification (V8) 226 7

24 EPL COM / 32 SEG LCD Driver Page Address Register The page address register provides a DDRAM page address The Page Address 8 is used for icon display, and only D is valid 73 LCD Driver Circuits COM COM63 COMI SEG SEG3 V V V2 V3 V4 VSS Commom Driver Circuits Segment Driver Circuits Shift Register Latch Circuit Display Timing Generator Circuit From the Display Data RAM Figure 9 LCD Driver Circuits This driver circuit is configured by 64-common drivers, 32-segment drivers and - icon-common driver This LCD panel driver voltage depends on the combination of display data and FR (internal) signal 73 Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM Display on/off, Inverse display on/off and Entire display on/off instructions control only the contents of this latch circuit, they cannot change the contents of the DDRAM 732 Shift Register Circuit The circuit contains a 64-bit shift register to shift and turn-on data required for the LCD drive common signals and -bit shift register used for icon The clock of this shift register is generated by display clock CL 8 Product Specification (V8) 226

25 EPL COM / 32 SEG LCD Driver Example of /33 and /65 duty (ICON enable) driving waveform CL /33 Duty /65 Duty FR COM COM COM3 (COM63) COMI Figure /33 and /65 Duty Driving Waveform Product Specification (V8) 226 9

26 EPL COM / 32 SEG LCD Driver Example of /32 duty and /64 Duty (Icon disable) driving waveform CL /32 Duty /64 Duty FR COM COM COM3 (COM62) COM3 (COM63) Figure /32 and /64 Duty Driving Waveform 2 Product Specification (V8) 226

27 EPL COM / 32 SEG LCD Driver 734 Common Driver Circuit The Common driver circuit consists of 65 drive circuits One of the four LCD driving level is selected by the combination of FR and data from the shift register V VCON VSS COM~63,COMI V4 V Shift Data VCOFF Scan Data FR H H L H L L Power save mode COMs Output Voltage VSS V V V4 VSS FR Figure 2 Common Driver Circuit 735 Segment Driver Circuit The Segment driver circuit consists of 32 driver circuits One of the four LCD driving level is selected by the combination of FR and the display data transferred from the latch circuit VSS V V3 V2 VSON Display Data VSOFF SEG~3 Display Data FR SEGs Output Voltage Normal Display Inverse Display H V V2 H L VSS V3 H V2 V L L V3 VSS Power save mode VSS FR Figure 3 Common Driver Circuit Product Specification (V8) 226 2

28 EPL COM / 32 SEG LCD Driver 736 LCD Driving Waveform The following illustration is an example of how the common and segment drivers are attached to an LCD panel CL SEG COM COM FR V V COM V4 VSS V COM V V4 VSS V V2 SEG V3 VSS V SEG-COM -V Figure 4 LCD Driver Waveform 22 Product Specification (V8) 226

29 EPL COM / 32 SEG LCD Driver 74 Internal Power Circuits LCD Driving Voltage Supply Voltage Followers VR Voltage Regulator IRS VOUT C+,C- C2+,C2- C3,C4 Voltage Converter Internal Power Circuits Figure 5 Internal Power Circuits The internal power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components There are voltage converter (V/C) circuits, voltage regulator (V/R) circuits, and voltage follower (V/F) circuits They are valid only in master operation and controlled by Power Control instruction For details, refers to "Instruction Description" User Setup Only the internal power supply circuits are used Only the voltage Regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power Control (VC VR VF) V/C Circuits V/R Circuits V/F Circuits VOUT V V to V4 On On On Open Open Open Off On On External input Off Off On Open Off Off Off Open Open External input External input Open Open External input Product Specification (V8)

30 EPL COM / 32 SEG LCD Driver 74 Voltage Converter Circuits These circuits boost up the electric potential between VDD and VSS to 2, 3, 4, or 5 times toward positive side and the boosted voltage is outputted from VOUT pin The boosting magnitude of internal booster circuit is selected by the means of the capacitor connection (Refer Figure 6 below) The internal oscillator is required to be operating when using this converter, since the divided signal provided from the oscillator is used for the internal timing of this circuit C+ C- C+ C- C+ C- Cb C+ C- OPEN C3 C3 C3 Cb C3 OPEN C4 OPEN C4 C4 Cb C4 OPEN C2- C2+ C2- C2+ C2- C2+ Cb C2- C2+ VOUT VOUT VOUT VOUT Cout 2X 3X 4X 5X Boost Capacitors (Cb)= uf Vout Capacitor (Cout)=22 uf~47 uf Figure 6 Capacitor Connections 742 Voltage Regulator Circuits The voltage regulator determines the LCD driving voltage V, by adjusting resistors, Ra and Rb, within the range of V < VOUT Since VOUT is the operating voltage of the operational-amplifier circuits, it is necessary to be applied internally or externally For Equation, we determine V by Ra, Rb and VEV Ra and Rb are connected internally or externally by the IRS pin VEV which is the voltage of the electronic volume is determined by Equation 2, where the parameter α is the value selected by instruction, "Set Contrast Control Mode", within the range to 63 VREF, a constant voltage source is about 2V at TA=25 24 Product Specification (V8) 226

31 EPL COM / 32 SEG LCD Driver VOUT V VEV (Constant reference voltage + electronic volume) Rb VR Ra VSS Figure 7 Resistor Connection Register Value (R2, R, R) Rb V = ( + ) VEV Equation Ra (63 VEV = α) ( ) VREF Equation (Rb/Ra) Value Small Large Refer to Regulator Resistor Select instruction for details α D5 D4 D3 D2 D D Refer to Set Contrast Control Mode instruction for details Product Specification (V8)

32 EPL COM / 32 SEG LCD Driver Using Internal Resistors, Ra and Rb (IRS = "H") When the IRS pin is H, resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V and VR V is determined by using the two instructions, "Regulator Resistor Select" and "Set Reference Voltage" Using External Resistors, Ra and Rb ( IRS = "L") When IRS pin is L, it is necessary to connect the external regulator resistor Ra between VR and VSS, and Rb between V and VR For a particular liquid, the optimum V LCD can be calculated for a given multiplex rate For a /65 duty ratio, the optimum operating voltage of the liquid can be calculated as: + 65 V LCD = Vth = 6 85 V 2 65 where V th is the threshold voltage of the liquid crystal material used 743 Voltage Follower Circuits th From Voltage Regulator V V 89xV 88xV V2 Total Req = 4M Switching Network 2xV xv V3 V4 Bypass Capacitor = uf~33uf OTP Type Voltage Follower Figure 8 OTP Voltage Follower Circuit The VLCD voltage (V) is resistively divided into four voltage levels (V, V2, V3, V4), and those output impedance are converted by the voltage follower (OPA) to increase the drive capability A total of six levels LCD reference voltage (V, V, V2, V3, V4, VSS) is generated by the voltage follower circuits 26 Product Specification (V8) 226

33 EPL COM / 32 SEG LCD Driver LCD Bias V V2 V3 V4 /9 89*V 78*V 22*V *V /85 88*V 765*V 235*V 2*V /8 875*V 75*V 25*V 25*V /75 865*V 735*V 265*V 35*V /7 855*V 75*V 285*V 45*V /65 845*V 69*V 3*V 55*V /6 835*V 665*V 335*V 65*V /55 82*V 635*V 365*V 8*V /5 8*V 6*V 4*V 2*V /45 78*V 555*V 445*V 22*V /4 75*V 5*V 5*V 25*V Different duty radio requires different bias level For optimum bias level, B L can be calculated from: B L = Duty ratio + Changing the bias system from the optimum will have a consequence on the contrast and viewing angle The LCD Bias affects the display quality But for the purpose of reducing the current consumption, the unsuitable bias may be selected Hence, the LCD Bias could be selected by Select LCD bias instruction 75 LCD Display Circuits FR Display Timing Generator Circuit CL /DOF FRS M/S Oscillator CLS OSC Figure 9 LCD Display Circuit Product Specification (V8)

34 EPL COM / 32 SEG LCD Driver 75 Oscillator The on-chip RC type oscillator provides the display clock and voltage converter timing clock It has low power consumption and its frequency is nearly independent of VDD When M/S = H and CLS = H, the oscillator circuit is enabled When CLS= L, the oscillator is stopped, and the oscillator clock has to be input to the OSC pin RC Oscillator To the Internal Circuit CLS OSC Sleep Mode Figure 2 RC Oscillator The oscillator circuit is available in master mode only The oscillator signal is divided and output as display clock at the CL pin 752 /DOF Pin Description The pin is used to control the blinking of the LCD display Instruction M/S= H M/S= L /DOF (Output) /DOF (Input) = H /DOF (Input) = L Display ON H LCD On LCD Off Display OFF L LCD Off LCD Off When the Power Save Instruction is activated, the /DOF pin is set to low level 753 Display Timing Generator Circuit This circuit generates some signals to be used to display the LCD When used in master/slave mode (multi-chip), some pins must be connected to each other That is due to synchronization output The display clock (CL) generated by the oscillation clock, generates a clock for the line counter and a latch signal for the display data latch The line address of the on-chip RAM is generated in synchronization with the display clock (CL) While the 32-bit display data is latched by the display data latch circuit in synchronization with the display clock, the display data which is read to the LCD driver is completely independent from any access to the display data RAM from the microprocessor 28 Product Specification (V8) 226

35 EPL COM / 32 SEG LCD Driver The display clock generates an LCD frame reversal signal (FR) which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver When this EPL6532 is used as a multi-chip, the slave chip must receive the FR, CL, /DOF signals from the master Master (M/S= H ) Slave (M/S= L ) Operation Mode FR CL /DOF FRS OSC Internal oscillator is enabled (CLS= H ) Internal oscillator is disable (CLS= L ) Note: Open means leave this pin open Output Output Output Output Open Output Output Output Output Input Internal oscillator is disabled Input Input Input Hi-Z Open (CLS = L or H ) Input Input Input Hi-Z Open 754 Oscillator Frequency The EPL6532 contains an RC oscillator The frame frequency (f FM ) is derived from the RC circuit s oscillation frequency (f OSC ) by giving it an appropriate value The relationship between the oscillation frequency (f OSC ), display clock frequency (f CL ) and the frame frequency (f FM ) is shown below The f OSC could be selected from an internal or external oscillator via the CLS pin, f CL could be selected using the Set display clock CL frequency instruction, and frame frequency could be calculated using the following equation 76 The Reset Circuit f CL = (Duty ratio) (Frame frequency) When the /RES input comes to the L level, these LSI return to their default state Their default states are as follows: Display OFF 2 Normal display 3 ADC select: Normal (ADC select instruction D = L ) 4 SHL select: Normal (SHL select instruction D3 = L ) 5 Power control register: (D2, D, D) = (,, ) 6 Serial interface internal register data clear 7 Duty ratio = /65 8 CL frequency Register (D4, D3, D2, D, D) = (,,,, ) 9 LCD power supply bias level = (/9) Entire display OFF (Entire display instruction D = L ) Power saving clear Product Specification (V8)

36 EPL COM / 32 SEG LCD Driver 2 Modify-Read OFF 3 Static indicator OFF Static indicator register: (D, D2) = (, ) 4 Display initial line set to first line: 5 Column address set to Address: 6 Page address set to Page: 7 Normal power mode: HP= 8 V voltage regulator internal resistor ratio set mode clear: (R2, R, R) = (,, ) 9 Contrast control set mode clear Contrast control register: (D5, D4, D3, D2, D, D) = (,,,, ) 8 Instruction Description Instruction A /RD /WR D7 D6 D5 D4 D3 D2 D D Description Read Display Data Read Data Read data from DDRAM Write Display Data Write Data Write data into DDRAM Read Status - Status Read the internal status Set Duty Ratio Mode Set duty ratio Mode Duty Ratio Register * * * * ICON D2 D D Select the duty ratio Set CL Frequency Mode Set CL frequency Mode CL Frequency Register * * * D4 D3 D2 D D Set CL frequency Register Set LCD Bias Select Mode Set LCD Bias select Mode LCD Bias Select Register * * * * D3 D2 D D Select the LCD Bias Turn on/off LCD panel Display On/Off Don When DON=: display off When DON=: display on Initial Display Line D5 D4 D3 D2 D D Specify DDRAM line for COM Set Contrast Control Mode Set Contrast Control Mode Set Contrast Control Register * * D5 D4 D3 D2 D D Set Contrast Control Register Set Page Address Page Address Set page address Set Column Address Higher order DDRAM column address of the MSB Column Add Higher 4-bits Set Column Address Lower order DDRAM column address of the LSB column Add lower 4-bits Select segment direction When ADC=: normal direction ADC Select ADC (SEG SEG3) When ADC=: reverse direction (SEG3 SEG) Select normal/inverse display Inverse Display ON/OFF REV : Normal display : Inverse display on 3 Product Specification (V8) 226

37 EPL COM / 32 SEG LCD Driver Instruction A /RD /WR D7 D6 D5 D4 D3 D2 D D Description Entire Display ON/OFF EON Select normal/entire display ON When EON=: normal display When EON=: entire display ON Set Modify-read Set modify-read mode Reset Modify-read Release modify-read mode Reset Initialize the internal functions SHL Select SHL * * * Select COM output direction When SHL=: normal direction (COM OM63) When SHL=: reverse direction (COM63 COM) Power Control VC VR VF Control power circuit operation Set high power mode Regulator Resistor Select Set Static Indicator Mode Set Static Indicator Register HP Select high or normal power mode Select internal resistance ratio R2 R R off the regulator resistor Set static indicator mode SM When SM = : off When SM = : on * * * * * * S S Set static indicator register Power Save Note: * means Don t care Compound display instruction OFF and entire display ON 8 Read Display Data The 8-bit data from the display data RAM specified by the column address and page address can be read by this instruction As the column address is automatically incremented by after each instruction execution, the microprocessor can continuously read data from the addressed page A /RD /WR D7 D6 D5 D4 D3 D2 D D Read Data 82 Write Display Data The 8-bit display data from the microprocessor can be written to the RAM location specified by the column address and page address After writing the display data, the column address is automatically incremented so that the microprocessor can continuously write data to the addressed page A /RD /WR D7 D6 D5 D4 D3 D2 D D Write Data Product Specification (V8) 226 3

38 EPL COM / 32 SEG LCD Driver 83 Read Status This instruction reads out the internal status of the ADC select, Display on/off and Reset A /RD /WR D7 D6 D5 D4 D3 D2 D D - ADC On/Off RESET Flag ADC On/Off RESET Description It shows the correspondence between the column address and segment drivers ADC = : Reverse direction (SEG3 SEG) = : Normal direction (SEG SEG3) This bit indicates the ON/OFF state of the display : Display ON : Display OFF Indicates the initialization is in progress by RESETB signal RESET = : Normal display operation state = : Internal reset operation state with reset command 84 Set Duty Ratio (Two-Byte Instruction) This consists of 2-byte instruction The first instruction sets the duty ratio mode, the second instruction updates the contents of the duty ratio register After the second instruction, the set duty mode is released The LSI cannot accept any instructions except for the Set duty ratio register during the set duty ratio mode 84 Set Duty Ratio Mode (First Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D 842 Set Duty Ratio Register (Second Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D Duty ratio * * * * ICON 8 (+ICON) 6 (+ICON) 24 (+ICON) 32 (+ICON) 36 (+ICON) 42 (+ICON) 48 (+ICON) 64 (+ICON) ICON : Enable COMI (icon display) pin : Disable COMI (icon display) pin 32 Product Specification (V8) 226

39 EPL COM / 32 SEG LCD Driver 85 Set Display Clock CL Frequency (Two-Byte Instruction) The display clock CL affects the current consumption and the frame frequency affects the flicker, so fine adjustments are required for the display clock CL and the frame frequency 85 Set CL Frequency Select Mode (First Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D 852 Set CL Frequency Select Register (Second Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D CL Frequency * * * * * * * f OSC f OSC / 2 f OSC / 3 f OSC / 4 f OSC / 5 f OSC / 6 f OSC / 7 f OSC / 8 f OSC / 9 f OSC / f OSC / f OSC / 2 f OSC / 3 f OSC / 4 f OSC / 5 f OSC / 6 f OSC / Select LCD Bias (Two-Byte Instruction) This instruction selects the LCD bias ratio of the voltage required for driving the LCD 86 Set the LCD Bias Select Mode (First Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D 862 Set the LCD Bias Select Register (Second Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D LCD Bias * * * * /4 /45 /5 /55 /6 /65 /7 /75 /8 /85 /9 Product Specification (V8)

40 EPL COM / 32 SEG LCD Driver 87 Display On/Off This instruction is used to control the turning on or off of the LCD panel regardless of the contents of the DDRAM A /RD /WR D7 D6 D5 D4 D3 D2 D D Display On or Off : Off : On 88 Initial Display Line This instruction sets the line address of the display RAM to determine the initial display line The initial display line corresponds to COM The display area read from the display data RAM corresponds to the number of lines set by the Duty select command A /RD /WR D7 D6 D5 D4 D3 D2 D D Line Address for COM Electronic Contrast Control Set (Two-Byte instruction) This consists of 2-byte instruction The first instruction sets contrast control mode, the second instruction updates the contents of the contrast control register After second instruction, the contrast control mode is released The LSI cannot accept any instructions except for the Set Contrast Control Register during the Contrast Control Mode 89 Set Contrast Control Mode (First Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D 892 Set Contrast Control Register (Second Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D Electronic Volume Value (α) * * Minimum Product Specification (V8) 226

41 EPL COM / 32 SEG LCD Driver 8 Set Page Address This instruction sets the page address of the display data RAM from the microprocessor into the page address register It is possible to access any required bit in the display data RAM by specifying the page address and the column address Along with the column address, the page address defines the address of the display RAM used to write or read the display data Changing the page address does not affect the display status Page 8 is assigned for the icon display Only D is valid A /RD /WR D7 D6 D5 D4 D3 D2 D D Page Address Set Column Address This instruction sets the column address of the display data RAM from the microprocessor into the column address register When accessing the display data RAM from the MPU, the column address is incremented The incrementing of the column address is stopped at address 83H A /RD /WR D7 D6 D5 D4 D3 D2 D D Column Address Setting A7 A6 A5 A4 Upper 4-bit A3 A2 A A Lower 4-bit A7 A6 A5 A4 A3 A2 A A Column Address 3 3 Product Specification (V8)

42 EPL COM / 32 SEG LCD Driver 82 ADC Select This instruction selects the segment driver direction Normal or reverse can be selected in the correlation between the display data RAM column address and the segment output terminal A /RD /WR D7 D6 D5 D4 D3 D2 D D Segment Driver Direction Normal Reverse D = Normal D = Reverse Column addresses H to 83H correspond to segment outputs to 3 Column addresses H to 83H correspond to segment outputs 3 to 83 Inverse Display On/Off This instruction is used to invert the display status of the LCD panel without rewriting the contents of the display data RAM A /RD /WR D7 D6 D5 D4 D3 D2 D D Display Status Normal Inverse D = Normal D = Inverse Display data turns the LCD On Display data turns the LCD On 84 Entire Display On/Off This instruction forces the whole LCD points to be turned on regardless of the contents of the display data RAM At this time, the contents of the display data RAM will be retained This instruction has priority over the Reverse Display On/Off instruction A /RD /WR D7 D6 D5 D4 D3 D2 D D Entire Display On/Off Normal Entire display On 85 Set Modify-Read This instruction stops the automatic increment of the column address by the Read Display Data instruction, but the column address is still incremented by the Write Display Data instruction This instruction can reduce the load of the MPU During the display, the data in a specific DDRAM area is repeatedly changed for cursor blinking or other functions This mode is canceled by the Reset Modify-read instruction A /RD /WR D7 D6 D5 D4 D3 D2 D D 36 Product Specification (V8) 226

43 EPL COM / 32 SEG LCD Driver 86 Reset Modify-Read 87 Reset This instruction cancels the Modify-read mode The column address of the display data RAM returns to the address before the Read Modify Write is executed A /RD /WR D7 D6 D5 D4 D3 D2 D D This instruction resets the initial display line, column address, page address, and the common output status is reset to their initial status, but does not affect the contents of display data RAM This instruction cannot initialize the LCD power supply, which is initialized by the /RES pin A /RD /WR D7 D6 D5 D4 D3 D2 D D Reset status by Reset instruction: Read modify write off 2 Static indicator off and static indicator register: (S,S)=(,) 3 Initial display line address : ()H 4 Column address : ()H 5 Page address : () page 6 SHL select : Normal mode (D3=) 7 Regulator resistor select register: (R2, R, R)=(,,) 8 Sets contrast control set mode off and contrast control register: (2)H 88 SHL Select The COM output scanning direction is selected by this instruction which determines the LCD driver output status A /RD /WR D7 D6 D5 D4 D3 D2 D D Common Driver Direction * * * Normal Reverse Note: * means Don t care D3 = Normal Normal direction (COM COM 63) D3 = Reverse Reverse direction (COM63 COM ) Product Specification (V8)

44 EPL COM / 32 SEG LCD Driver 89 Power Control This instruction is used to select one of the eight power circuit functions by using the 3-bit register An external power supply and part of the internal power supply functions can be used simultaneously A /RD /WR D7 D6 D5 D4 D3 D2 D D VC VR VF VC: Voltage converter VR: Voltage regulator : Off VF: Voltage follower : On 82 Set High Power Mode When driving an LCD panel with large loads, the normal power mode may cause a poorer display quality In such a case, setting to the high mode (HP=) can improve the display quality A /RD /WR D7 D6 D5 D4 D3 D2 D D HP D = Normal power mode D = High power mode 82 Regulator Resistor Select This selects the resistance ratio of the internal resistor used in the internal voltage regulator See voltage regulator section in power supply circuit for more details A /RD /WR D7 D6 D5 D4 D3 D2 D D R2 R R R2 R R [Rb/Ra] Ratio Small Large 38 Product Specification (V8) 226

45 EPL COM / 32 SEG LCD Driver 822 Set Status Indicator (Two-Byte Instruction) This consists of two bytes instruction The first byte instruction (Set Static Indicator Mode) enables the second byte instruction (Set Static Indicator Register) to be valid The first byte sets the static indicator on/off When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this status indicator state is released after setting the data of the indicator register 822 Set Status Indicator Mode (First Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D Status Indicator Off On 8222 Set Static Indicator Register (Second Instruction) A /RD /WR D7 D6 D5 D4 D3 D2 D D Status * * * * * * 823 Power Save (Compound Instruction) Off On (Blink at 4-frame intervals) On (Blink at 2-frame intervals) On (Turn on at all time) The current consumption can be greatly reduced by entering the power save status and inputting the Entire Display ON instruction while the display is in OFF mode According to the status in static indicator mode, power save is entered through one of two modes (sleep and standby mode) Power Save mode is released by the Display ON & Entire Display OFF instructions Static indicator OFF Static indicator ON Power saver (compound command) [ Display OFF ] [ Entire Display ON ] Static Indicator ON Sleep mode Standby mode Reset instruction Power Save OFF ( Compound Instruction ) [ Entire Display OFF ] [ Display ON ] [ Static Indicator ON ] Power Save OFF ( Compound Instruction ) [ Entire Display OFF ] [ Display ON ] Cancel Sleep mode Cancel Standby mode Product Specification (V8)

46 EPL COM / 32 SEG LCD Driver 823 Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current The internal modes during sleep mode are as follows: The oscillator circuit and the LCD power supply circuit are stopped 2 All liquid crystal drive circuits are stopped, and the segment and common driver output VSS level When a static indicator on instruction is issued in the sleep mode, the LSI goes into a standby mode 8232 Standby Mode All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive The internal conditions in the standby state are as follows: The power supply circuit for LCD drive is stopped The oscillator circuit will be operating 2 The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the VSS level The static display section will be operating When a reset instruction is issued in the standby mode, the LSI goes into the sleep mode 4 Product Specification (V8) 226

47 EPL COM / 32 SEG LCD Driver 9 Application Information 9 Instruction Procedure Examples 9 Initial Setup (From power application to display ON using internal power supply circuits) VDD-VSS Power ON P o w e r s ta b iliz a tio n Input Reset Signal W ait fo r m o re th an 2 m s Initial settings state (default) User settings via instruction input () DUTY select LCD bias select CL frequency select ADC select SHL select User settings via com m and input (2) Regulator resistor select Contrast control volum e User settings via com m and input (3) P o w er co n tro l VC,VR,VF=(,,) W ait for m ore than 3m s to stabilize p o w e r le v e ls the LCD E n d o f in itia l s e ttin g s LCD display screen settings Display start line set W riting screen data, etc Display ON Product Specification (V8) 226 4

48 EPL COM / 32 SEG LCD Driver Modify-read Sequence Set Page Address Set Column Address Set modify-read Dummy read Data read Data write NO Change complete YES End 42 Product Specification (V8) 226

49 EPL COM / 32 SEG LCD Driver External Oscillator Input Sequence Set CL frequency select mode Set CL frequency select register Input clock to OSC pin End LCD Power-on Sequence (Use Internal Power Circuit) Sleep m ode Release Sleep m ode Reset VC, VR, VF = (,,) S e t V C, V R, V F = (,, ) Clear VF (Reset to ) Set VF to (Repeat this procedure VF => until all voltage are stable Depends on the outside loading) Voltage Stable LCD display ON Product Specification (V8)

50 EPL COM / 32 SEG LCD Driver 92 Program Examples Use Elan Risc II MCU assembly ;***************************************************************************** ; Initialization Setting Example of EPL6532 ;***************************************************************************** INI_DRIVER_IC: MOV A,#LCD_COM_RESET ;INITIAL SETTINGS STATE (DEFAULT) CALL WRITE_LCD_BYTE MOV A,#LCD_COM_DUTY ;SET DUTY ST INSTRUCTION CALL WRITE_LCD_BYTE MOV A,#DUTY_SET ;SET DUTY 2ND INSTRUCTION CALL WRITE_LCD_BYTE MOV A,#LCD_COM_BIAS ;SET LCD BIAS ST INSTRUCTION CALL WRITE_LCD_BYTE MOV A,BIAS_SET ;SET BIAS 2ND INSTRUCTION CALL WRITE_LCD_BYTE MOV A,#LCD_COM_FREQ ;SET LCD CL FREQUENCY ST INSTRUCTION CALL WRITE_LCD_BYTE MOV A,#CL_FREQ ;SET CL FREQUENCE 2ND INSTRUCTION CALL WRITE_LCD_BYTE MOV A,#LCD_ADC_SET ;SET ADC FUNCTION SELECT CALL WRITE_LCD_BYTE MOV A,#LCD_SHL_SET ;SET SHL FUNCTION SELECT CALL WRITE_LCD_BYTE MOV A,#LCD_REGULATOR_RES_SET ;SET REGULATOR RESISTOR +(Rb/Ra) CALL WRITE_LCD_BYTE MOV A,#LCD_COM_CONTRAST ;SET CONTRAST ST INSTRUCTION CALL WRITE_LCD_BYTE MOV A,#CONTRAST_SET ;SET CONTRAST 2ND INSTRUCTION CALL WRITE_LCD_BYTE MOV A,#LCD_POWER_CONTROL_SET ;SET POWER CONTROL (INTERNAL OR EXTERNAL) CALL WRITE_LCD_BYTE BS REG_CPUCON,F_CKS ;ADD CLOCK BY OSC PIN (CLOCK FROM CPU) MOV A,#5 ;WAIT TO STABILIZE THE LCD POWER CALL WAIT_A_MS CALL LCD_DISPLAY_ON ;TURN ON LCD MOV A,#LCD_DISPLAY_INI_LINE ;SET INITIAL DISPLAY LINE CALL WRITE_LCD_BYTE CALL LCD_DATA_WRITE ;WRITING SCREEN DATA RET 44 Product Specification (V8) 226

51 EPL COM / 32 SEG LCD Driver ************************************************************************************* ; Write Display_Picture Data into Display Data RAM of EPL6532 ;************************************************************************************ DATA_WRITE: TBPTL #DISPLAY_PICTURE*2 ;DEFINE DISPLAY PICTURE DATA INDEX TBPTM #DISPLAY_PICTURE/x8 TBPTH #DISPLAY_PICTURE/x8 DATA_WRITE_6532: MOV A,#LINE_Y_MAX ;MAX PAGES OF DDRAM MOV REG_LCDARH,A DATA_W: MOV A,#LINE_X_MAX ;SET MAX SEGMENTS OF DDRAM MOV REG_LCDARL,A BC REG_PORTB,F_LCD_A ;SET LCD /A= INSTRUCTION OUTPUT MOV A,#LCD_COM_PAGE ADD A,REG_LCDARH CALL WRITE_LCD_BYTE MOV A,#b ;SET LOWER ORDER COLUMN ADDRESS= CALL WRITE_LCD_BYTE MOV A,#b ;SET HIGHER ORDER COLUMN ADDRESS= CALL WRITE_LCD_BYTE BS REG_PORTB,F_LCD_A ;SET LCD /A = DATA OUTPUT DATA_W2: TBRD,REG_ACC ;ACCESS THE DATA OF DISPLAY_PICTURE CALL WRITE_LCD_BYTE DEC REG_LCDARL JBS REG_STATUS,F_C,DATA_W2 ;IDENTIFY RES_STATUS CARRY BIT SET OR NOT DEC REG_LCDARH JBS REG_STATUS,F_C,DATA_W BC REG_PORTB,F_LCD_A ;LCD /A = FOR INSTRUCTION OUTPUT RET Product Specification (V8)

52 EPL COM / 32 SEG LCD Driver ;***************************************************************************** ; Write One Byte Data into DDRAM (Parallel Mode 8 Series) ;***************************************************************************** ;AT FIRST DEFINE A TO IDENTIFY DATA OR INSTRUCTION WRITE WRITE_LCD_BYTE: JBS REG_DCRG,F_LAHEN,WRITE_LCD_BYTE_ ;CHECK REG_DCRG LAHEN BIT= OR NOT BC REG_PORTC,F_LCD_WR ;SET /WR= ENABLE WRITE MOV REG_DATA,A ;MOVE A PORT_G NOP ;Write low pulse( Wait 2 instruction cycles) NOP BS REG_PORTC,F_LCD_WR ;SET /WR= DISABLE WRITE NOP NOP NOP NOP RET WRITE_LCD_BYTE_: MOV REG_DATA, ;MOVE A PORT_G RET ;***************************************************************************** ; Read One Byte Data into DDRAM (Parallel Mode 8 Series) ;***************************************************************************** ;AT FIRST DEFINE A TO IDENTIFY DATA OR INSTRUCTION READ READ_LCD_BYTE: BC REG_PORTB,F_LCD_RD ;SET /RD= ENABLE READ NOP NOP MOV A,REG_DATA ;MOVE PORT_G A NOP BS REG_PORTB,F_LCD_RD ;SET /RD= DISABLE READ NOP RET 46 Product Specification (V8) 226

53 EPL COM / 32 SEG LCD Driver Electrical Characteristics Absolute Maximum Ratings Parameter Applicable Pins Symbol Condition Rated Value Unit Power supply voltage VDD VDD TA=25 C -3 to +7 Driver supply voltage VOUT VLCD TA=25 C -3 to +7 V Input voltage All InpuT VIN TA=25 C -3 to VDD+3 Operating temperature range Storage temperature range - TA - -3 to to +25 C 2 Recommended Operating Conditions Parameter Applicable Pins Symbol Condition Rated Value Min Typ Max Unit Power supply Voltage Voltage converter output voltage Output voltage Input voltage VDD VDD VOUT VOUT VOH - 7VDD - VDD - VOL - VSS - 3VDD - VIH - 7VDD - VDD - VIL - VSS - 3VDD V Operating temperature range - TA C Product Specification (V8)

54 EPL COM / 32 SEG LCD Driver 3 DC Characteristics VSS=V, VDD=27V to 33V, TA=-3 C ~ 8 C Parameter Applicable Pins Symbol Condition Rated Value Min Typ Max Power Supply Voltage VDD VDD Voltage Converter Input voltage VDD VDD2 2 boost VDD VDD3 3 boost 22-5 VDD VDD4 4 boost VDD VDD5 5 boost 22-3 Reference Voltage - V REF TA = 25 C Regulated Voltage V V TA = 25 C V-4% V V+4% Bias Voltage V4 V4 TA = 25 C 75 Output Voltage Voltage Converter Output Voltage LCD Driver ON Resistance - VOH IOH = -5mA 8VDD - VDD - VOL IOL = 5mA VSS - 2VDD VOUT COMn SEGn VOUT R ON Reset Resistor /RES R RESET LCD Voltage Capacitor Boost Capacitor V, V, V2, V3, V4 C, -C, C2, -C2, C3, C4 Unit 2/ 3/ 4/ 5 No load % Current load I load = 5µA VDD = 3V, Vin = V kω VDD = 3V, Vin = 7V Cv - 33 Cb - - Vout Capacitor Vout Cout Input Leakage Current All Input 2 IIL VIN = VDD or V - - ± Output Current (Source and Drain) Output Tri-state Dynamic Current Consumption IDDD V OUT = V DD or V SS ± 5 VDD = 3V, TA = 25 C, Quad boosting, f OSC = 22kHz, /65 duty ratio, All display pattern off ± Current Consumption - IDDs Standby mode - 5 Current Consumption - IDDs2 Sleep mode - 2 Frame Frequency - f FM Hz Internal Oscillator Frequency External Input Oscillator Note : - f OSC TA = 25 C OSC f OSC TA = 25 C Rb (63 V = ( + ) VEV ; VEV α) = ( ) VREF Ra : Input pin D~D7, A, /RD, /WR, /CS, CS2, CLS, M/S, C86, P/S, /RES, IRS, OSC V µf µa khz 3 : Output pin D~D7, FR, FRS, /DOF, CL 48 Product Specification (V8) 226

55 EPL COM / 32 SEG LCD Driver 4 AC Characteristics 4 Serial Interface Timing Characteristics /CS,CS2 tcss tchs A /WR (R/W) tass tcycs tahs D6 (SCK) tclls tclhs D7 (SDI) tdss tdhs tdds tohs D5 (SDO) VSS= V, VDD= 3 V, TA=25 C Parameter Applicable Pins Symbol Condition Rated Value Min Max Unit Chip Select Setup Time Chip Select Hold Time /CS CS2 t CSS t CHS - - Address Setup time Address Hold time A R/W t ASS t AHS - - Data Setup Time Data Hold Time Clock Cycle Time Clock L Time Clock H Time D7 (SDI) D6 (SCK) t DSS t DHS t CYCS t CLLS t CLHS DATA SCK SCK DATA ns Data Delay Time Data Disable Time D5 (SDO) t DDS t OHS CL= pf Product Specification (V8)

56 EPL COM / 32 SEG LCD Driver 42 8-Family MPU Read/Write Timing Characteristics tah8 A /CS (CS2) taw8 tcyc8 /WR, /RD tcc8 D to D7 (Write) tds8 tdh8 D to D7 (Read) tacc8 toh8 VSS= V, VDD= 3 V, TA= 25 C Parameter Applicable Pins Symbol Condition Rated Value Min Max Unit Address Setup Time Address Hold Time A t AW8 t AH8 - - System Cycle Time A t CYC8-5 - Pulse Width(/WR) Pulse Width(/RD) /WR /RD t CC ns Data Setup Time Data Hold Time Read Access Time Output Disable Time D~D7 t DS8 t DH8 t ACC8 t OH8 - CL=pF Product Specification (V8) 226

57 EPL COM / 32 SEG LCD Driver Family MPU Read/Write Timing Characteristics tcyc6 E taw6 tew A R/W tah6 /CS (CS2) D to D7 (Write) tds6 tdh6 D to D7 (Read) tacc6 toh6 VSS= V, VDD= 3 V, TA= 25 C Parameter Applicable Pins Symbol Condition Rated value Min Max Unit Address Setup Time Address Hold Time A R/W t AW6 t AH6 - - System Cycle Time A t CYC6-5 - Pulse Width(/WR) Pulse Width(/RD) E t EW ns Data Setup Time Data Hold Time Read Access Time Output Disable Time D~D7 t DS6 t DH6 t ACC6 t OH6 - CL=pF Product Specification (V8) 226 5

58 EPL COM / 32 SEG LCD Driver Pin Configuration Input Pin Configuration VDD 2 Input/Output Pin Configuration VDD Output data Output enable Input enable 52 Product Specification (V8) 226

59 EPL COM / 32 SEG LCD Driver 3 Output Pin Configuration VDD 4 Reset Input Pin Configuration VDD Product Specification (V8)

60 EPL COM / 32 SEG LCD Driver 5 LCD Output Pin Configuration V V COMMON OUTPUT V SEGMENT OUTPUT V2 V4 V3 VSS VSS 54 Product Specification (V8) 226

61 EPL COM / 32 SEG LCD Driver 2 MPU Interface 2 Elan 8-bit MPU (with external memory) VDD VCC PORT D_ PORT A,B PORT D_4 PORT D_5 RISC2 MPU PORT G PORT D_2 PORT D_3 /RES GND /RESET A /CS CS2 VCC C68 EPL6532 D ~D7 /RD /WR PS /RES GND VDD LCD PANEL VDD VCC FLASH /OE R/W /CE D ~D7 A~An GND 22 Serial Interface (SPI) VDD VCC A A VCC VDD OR VSS PORT3_ MPU PORT2 PORT PORT GND /RES VDD /RESET /CS C68 CS2 EPL6532 SDI (D7) SCK (D6) SDO (D5) PS /RES GND LCD PANEL Product Specification (V8)

62 EPL COM / 32 SEG LCD Driver 23 8-Family MPU VDD VCC A A VCC A~A7 /IORQ DECODER /CS CS2 C68 8 type MPU EPL6532 D ~D7 /RD /WR /RES GND D ~D7 /RD /WR /RES GND PS VDD /RESET Family MPU VDD VCC A A~A5 VMA DECODER A /CS CS2 VCC C68 VDD 68 type MPU EPL6532 D ~D7 E R/W /RES GND D ~D7 /RD /WR /RES GND PS VDD /RESET 56 Product Specification (V8) 226

63 EPL COM / 32 SEG LCD Driver 3 Application Circuits Example : pixels driving application circuits ( Single-chip using internal oscillator) LCD PANEL 64X32 PIXELS WITH ICON DISPLAY COM~63+ COMI SEG~SEG3 /IORQ A An DECODER CLS FR CL /DOF V V MASTER V2 ( EPL6532 ) V3 V4 M/S OSC /CS CS2 A /RD /WR D~D7 /RST A /RD /WR D~D7 /RES RESET CIRCUIT Example 2: pixels driving application circuits ( Multi-chip using external oscillator) LCD PANEL 64X264 PIXELS WITH ICONS DISPLAY COM~3+COMI SEG~SEG3 SEG~SEG3 COM32~63+COMI /IORQ A An DECODER CLS MASTER (E6532) FR CL /DOF V V V2 V3 V4 M/S FR CL /DOF V V V2 V3 V4 M/S SLAVE (E6532) MPU OSC /CS CS2 A /RD /WR D~D7 /RST OSC /CS CS2 A /RD /WR D~D7 /RST CLK A /RD /WR D~D7 /RES RESET CIRCUIT Product Specification (V8)