V50. High Speed Low Cost Platform for SoC IC Test

Transcription

1 V50 High peed Low Cost Platform for oc IC Test

2 Agenda V50 Overview Application Targets Hardware and oftware ummary Q&A

3 eatures of V50 Test ystem 64 to 256 Logic I/O pins with 64-pin increment Parallel test up to 32 site lexible Configuration: Logic, Mixed-ignal, OPM

4 ystem Overview of V50 GPIB Interface R232 Interface TTL Test Controller I/O Interface Board Logic and APG Board Logic APG PPMU UR Channel PMU DP DVM TMU ystem Backplane Mixed-ignal Board AWG DIG VI DVM TMU DAQ VR UR Cable OPM Board AC 110V/220V Auto Ranging Power upply Module channel PMU TMU DVM UR Application pecific Board

5 Electrical pecifications Test Controller CPU Disk torage Monitor Networking Operation ystem Pentium IV or Compatible 40GB 17 color Ethernet, TCP, N Windows XP Electrical pecification AC Power Power Consumption Environmental pecification Operation Temperature torage Temperature Humidity 110V ~ 220V 500W (for 128 channels) 1000W (for 256 channels) 0 ~ ~ 70 50±20% RH

6 Application Targets of V50 Analog ICs Power MO Linear Regulators Audio Op Amps LDO Regulators Voltage References Voltage Detectors Digital ICs Micro Controllers Embedded Memory lash Memories EEPROMs UB2.0 peech ICs Telephone Controller OTP MMC control Mixed-ignal ICs Battery Charger PWM DC-DC Analog witches Analog Multiplexers Audio CODEC Audio DACs Audio ADCs

7 Block Diagram of Logic & APG Board APG Control Logic u-inst Memory Pattern Memory DLOG Memory Per Per Per Per Pin Pin Per Per Pin Pin MT MT Per Per Pin Pin MT MT Pin Pin MT MT TG TG Levels MT MT TG DACs Levels PPMU TG DACs Levels PPMU TG DACs Levels & PPMU TG DACs Levels PPMU TG DACs Levels PPMU TG DACs Levels PPMU DACs Levels PPMU DACs PPMU LA Memory 16 X 16 Y 16 D I/O and Control Logic 32 UR

8 pecifications of Logic &APG Board 1. Logic Pin Configuration Timing ub-system ormat Pin Electronics Driver Pin Electronics Comparator Time Measurement Unit I/O Channels : 64 pins Min. Period : 20 ns Data Rate: 50 MHz Clock Rate: 100 MHz Timing Generators: 6 edges/pin Edge Placement Res:0.5 ns Pattern Memory Depth : 17M RZ, NRZ, RTO, N, BC Change-on-the-fly Driver VR0 VR1 VR2 Comparator VR0 VR1 VR2 Input -2V ~ +10V -0.5V ~ +3.5V -1.0V ~ +7.0V -2.0V ~ +7.0V -0.5V ~ +3.5V -1.0V ~ +7.0V -2.0V ~ +11.0V Bandwidth 200MHz 5.00n 2. APG Address Generator Data Generator Instruction Memory 3. DC 1 Differential Voltage Meter E1:±100mV E2:±10V 32 Utility Relay Output Voltage : 50V (Max) Output Current : 500mA (Max) Utility Power Voltage -5V, +5V, +12V -15A, +15A uV uV X-GEN : 16 bits Y-GEN : 16 bits D-GEN : 16 bits Depth : 1K words Current 1 A 0.3 A ±0.5%±61.04uV ±0.5%±6.104mV

9 pecifications of Logic &APG Board 8 Parametric Measurement Unit (PMU) orce E1:±10V uv I1:±1uA pa I2:±10uA na I3:±100uA na I4:±1 ma na I5:±10mA ua I6:±250mA ua ±0.5% ±6.103mV ±0.5% ±659.17pA ±0.5% ±6.5917nA ±0.5% ±65.917nA ±0.5% ±659.17nA ±0.5% ±7.0312uA ±0.5% ±183.10uA Measure E1:±10V I1:±1uA I2:±10uA I3:±100uA I4:±1 ma I5:±10mA I6:±250mA uv pa na na na ua ua ±0.5% ±6.103mV ±0.5% ±659.17pA ±0.5% ±6.5917nA ±0.5% ±65.917nA ±0.5% ±659.17nA ±0.5% ±7.0312uA ±0.5% ±183.10uA 2 Device Power upply (DP) orce E1:±5V 610uV E2:+15/-10V 1.83mV I1:±827nA nA I2:±8.27uA nA I3:±82.7uA 10.98nA I4:±827uA uA I6:±87.5mA uA I7: ±1.83A uA ±0.5%±3.624mV ±0.5%±7.324mV ±0.5%±659.17pA ±0.5%±6.5917nA ±0.5%±659.17nA ±0.5%±6.7382uA ±0.5%±85.693uA ±0.5%±1.464mA Measure E1:±5V E2:+15/-10V I1:±827nA I2:±8.27uA I3:±82.7uA I4:±827uA I6:±87.5mA I7: ±1.83A 610uV 1.83mV nA nA 10.98nA uA uA uA ±0.5%±3.624mV ±0.5%±7.324mV ±0.5%±659.17pA ±0.5%±6.5917nA ±0.5%±659.17nA ±0.5%±6.7382uA ±0.5%±85.693uA ±0.5%±1.464mA

10 Block Diagram of Mixed-signal Board 32 UR I/O And Control Logic

11 Block Diagram of Mixed-ignal Board 3 Arbitrary Waveform Generator (AWG) 8 Voltage Reference ource (VR) Output ample Rate ±10 V 500 KP 16 bits E:-15V~+40V 6.11mV ±0.5%±36.62mV I:±15mA 1 Waveform Digitizer (DIG) 1 Differential Voltage Meter (DVM) Input ample Rate ±10 V 500KP 16 bits E1:±100mV uV ±0.5%±61.04uV E2:±10V uV ±0.5%±6.104mV 2 Time Measurement Unit (TMU) 1 Root Mean quare Meter (RM) Input Bandwidth ±10 V 30 MHz 8.06 n E1:1.4Vrms 21.36uVrms ±0.5%±128.17uVrms E2:7.0Vrms uVrms ±0.5%±640.87uVrms 1 Data Acquisition (DAQ) Input Mem depth ±10 V 128 K Mem width 16 bits 32 Utility Relay (UR) Output Voltage : 50V (Max) Output Current : 150mA (Max) Voltage Current -5V, +5V, +12V 1 A -15A, +15A 0.3 A

12 Block Diagram of OPM Board Octal PMU ADC DAC DAC DAC DAC DAC DAC DAC DAC MUX MUX MUX MUX MUX MUX MUX MUX PMU PMU PMU PMU PMU PMU PMU PMU 32 UR Diff Amp Gain DVM ADC I/O And Control Logic Trig A Level A Trig B Level B TMU Control Logic Control ignals Trigger lope Control Trigger lope Control TMU Time Interval Measurement Multi- Time Interval Measurement req. Measurement torage Memory torage Memory torage Memory

13 pecification of OPM Board DC Pin Configuration : I/O Channels 64 pins 4 Differential Voltage Meter (DVM) 1Time Measurement Unit (TMU) Input Bandwidth -10V ~ +10V 30 MHz 100.0n E1:±100mV E2:±10V uV uV ±0.5%±61.04uV ±0.5%±6.104mV 8 Voltage/Current ource/meter (V/I ource/meter) Measure E1:±5V ±(0.015% of range % of value) E2:±10V ±(0.015% of range % of value) E3:-15V~+20V ±(0.015% of range % of value) E4:-15V~+40V ±(0.015% of range % of value) I1:±380nA ± 5nA I2:±3.5uA ±(0.1% of range + 0.1% of value) I3:±35.9uA ±(0.1% of range + 0.1% of value) I4:±359uA ±(0.1% of range + 0.1% of value) I5:±3.5mA ±(0.1% of range + 0.1% of value) I6:±32mA ±(0.1% of range + 0.1% of value) I7:±181mA ±(0.1% of range + 0.1% of value) I8:±2A ±(0.2% of range + 0.2% of value) orce E1:±5V E2:±10V E3:-15V~+20V E4:-15V~+40V I1:±380nA I2:±3.5uA I3:±35.9uA I4:±359uA I5:±3.5mA I6:±32mA I7:±181mA I8:±2A ±(0.03% of range % of value) ±(0.03% of range % of value) ±(0.03% of range % of value) ±(0.03% of range % of value) ± 5nA ±(0.1% of range + 0.1% of value) ±(0.1% of range + 0.1% of value) ±(0.1% of range + 0.1% of value) ±(0.1% of range + 0.1% of value) ±(0.1% of range + 0.1% of value) ±(0.1% of range + 0.1% of value) ±(0.2% of range + 0.2% of value)

14 oftware Architecture of V50 Direct Maintenance Entry A50 Entry election Direct Production Entry Maintenance Direct Mode witching with Permission Control Engineering Direct Mode witching with Permission Control Production Diagnostic Tool Calibration Tool Program Compiler Pattern Compiler Integrated Program Debugger Pattern Editor Logic Analyzer hmoo Plot APG imulator etup Library ummary Wafer Map PHI Tool Learn Tool Histogram Tool Pin Margin Analog ignal Analyzer Analog Waveform Editor DP Tools ummary Wafer Map PHI Tool

15 Real-Time Program Editor

16 Logic Analyzer

17 Datalog & ummary Tool

18 Wafer Map

19 ummary Ease of Use riendly Test Development Environment Reduce Learning Curve Improved productivity Multi-ite (up to 32 sites) lexible configuration High Performance Cost

20 Q&A Thank you very much